Hi,
As far as I am aware, GCC 4.4.x now works on Linux through RosBE 1.5 (minus some missing patches for 64-bit hosts), and I've gotten it to work on SnowLeopard with some minor hacks -- ie, all that's missing is for Colin, when he has time, to integrate the little fixes for these non-standard hosts.
As for Windows, I think there is a fully working binary GCC 4.4.x/RosBE that builds trunk just fine.
So what's missing for 4.4.x to become official, RosBE 1.5 to RTM, and for the 4.4.x patch from BZ to be committed (The one that gets trunk building)?
Best regards,
Alex Ionescu
sserapion(a)svn.reactos.org wrote:
> Add definitions for the x86bios emulator.
>
http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/hal/api/x86bi
os/index.htm
>From the link: "The HAL in x86 builds of Windows Vista introduces a set of
functions for accessing the 16-bit firmware that Windows started from."
So you're adding functions from the x86 HAL in NT6 to our NT5.2-targeted
AMD64 HAL? Is it just me who gets confused here?
If it's alright, I'd like to hear some explanations.
Best regards,
Colin
Hello,
I have identified a major deficiency in the x86 kernel that requires minor overhaul of multiple low-level components, and stems from poorly understood implementation details of the x86 architecture, which is NMI support.
NMIs are Non Maskable Interrupts, similar to SMIs (generated for SMM) mode but typically used for critical hardware errors (somewhat a precursor to MCEs).
Most modern operating systems support NMI as a debugging tool: when a system is deadlocked due to interrupt issues or perhaps in a state with interrupts disabled, it is often hard to "break-in" the system to analyze the issue. They are also used as a last resort to terminate the system in case of major hardware error (such as power issues or parity errors).
NMIs can also be generated by external hardware:
This simple circuit generates a tri-state one-cycle SERR# pulse on the PCI bus, which causes an NMI. It can be used as an emergency dump switch, when other methods fail.
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The following issues exist in ReactOS that hinder NMI support:
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- The I/O Privilege Map (IOPM) configuration is done dangerously and incorrectly. A number of misunderstood hardcoded values are used throughout the code, assumptions are made on the number of IOPMs, and IOPM switching is done very poorly during BIOS Calls.
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- BIOS Calls are currently executing on the TSS context of the current state. This works fine with the normal KGDT_TSS that NTOS executes on, but causes dangerous errors on scenarios such as Double Faults (KGDT_DF_TSS) and NMIs (KGDT_NMI_TSS). These TSS segments do not have an IOPM allocated, which causes memory corruption when the BIOS Call code attempts to save and restore the IOPM by assuming it's there. It also causes BIOS code to fail during execution; after tracing with an IDP we discovered that BIOS I/O Port accesses were generating exceptions, which turned out to be due to the fact the BIOS was reading the bogus, non-existing IOPM and thus failing to validate I/O Port access. This is currently a problem in ReactOS as a double-fault trap will trigger massive corruption, as the panic code will attempt to draw the "Blue screen of death", requiring a Video ROM Interrupt 10h through a BIOS Call, which will fail as explained. In an NMI case, the same scenario would also happen.
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- The NMI trap code is not yet implemented.
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- The KeRegisterNmiCallback and KeDeregisterNmiCallback routines are not yet implemented.
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- KPRCB Context-switching is not yet implemented, along with related routines. Only the high-level routines used during debug traps are implemented, but not the support required for resuming after an NMI.
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- HalHandleNMI is subject to recursive NMI scenarios.
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- BIOS Calls do excessive TLB flushing.
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- The logic for IDT write-protection during BIOS Calls is overcomplicated. The IDT should always be made read-only and restore to its previous state.
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- TLB flushing in the HAL appears to be broken when global pages are used. Additionally, the same problem exists in NTOS -- there is no support for TLB flushing when Global Pages are used, even though Global Page support is enabled in the MMU and the bit is used on kernel PTEs. This leads to either over-flushing global pages during context switching, which shouldn't be done, or non-flushing of global pages, when they should be flushed.
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- Tangential issue: I have written a new UNIMPLEMENTED_PATH macro that now describes the exact path that was touched. Previously only the PC was given, which makes it nearly impossible to connect to the line of source causing the issue, especially for non developers. This new macro outputs a string reason. Additionally, an UNIMPLEMENTED_V86_PATH is used for scenarios where the path is only expected in VDM/V8086 scenarios, to differentiate from unlikely paths in normal execution flows.
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These issues have all been fixed in my toilet. All this work stemmed from doing some testing of the new ARM3 section code written recently (never debug other people's code!), which led to significant debugging pains without NMI support. It has nothing to do with the ARM port but since I've written it, I might as well pass it on instead of keeping it locally for eternity.
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Thoughts/comments?
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-r
Dear ReactOS Members,
We'd like to issue you our warmest holiday greetings and a happy new year!
Withal, receive our cordial gratitude for the recent work on getting the ARM tree building again as well as for extending support for Windows and Mac OS X build systems throughout this troubled time.
-r
