Author: greatlrd
Date: Thu Jan 18 18:40:37 2007
New Revision: 25511
URL: http://svn.reactos.org/svn/reactos?rev=25511&view=rev
Log:
Fixing some ppc disambler bugs. Li are not 100% test it can contain some fault.
Fixing Li bug the register for dest was wrong calctions see file OpCodePPC.txt.
fixing some meaing in ReadMe.txt
Modified:
trunk/rosapps/devutils/cputointel/From/PPC/PPC.h
trunk/rosapps/devutils/cputointel/From/PPC/PPCBrain.c
trunk/rosapps/devutils/cputointel/From/PPC/PPCBrain.h
trunk/rosapps/devutils/cputointel/From/PPC/PPCopcode.c
trunk/rosapps/devutils/cputointel/OpCodePPC.txt
trunk/rosapps/devutils/cputointel/ReadMe.txt
Modified: trunk/rosapps/devutils/cputointel/From/PPC/PPC.h
URL: http://svn.reactos.org/svn/reactos/trunk/rosapps/devutils/cputointel/From/P…
==============================================================================
--- trunk/rosapps/devutils/cputointel/From/PPC/PPC.h (original)
+++ trunk/rosapps/devutils/cputointel/From/PPC/PPC.h Thu Jan 18 18:40:37 2007
@@ -10,14 +10,11 @@
/* here we put the prototype for the opcode api that brain need we show a example for it */
-CPU_INT PPC_Addx(FILE *out, CPU_BYTE * cpu_buffer, CPU_UNINT cpu_pos, CPU_UNINT cpu_size, CPU_UNINT BaseAddress, CPU_UNINT cpuarch);
CPU_INT PPC_Blr( FILE *out, CPU_BYTE * cpu_buffer, CPU_UNINT cpu_pos, CPU_UNINT cpu_size, CPU_UNINT BaseAddress, CPU_UNINT cpuarch);
-CPU_INT PPC_Ld( FILE *out, CPU_BYTE * cpu_buffer, CPU_UNINT cpu_pos, CPU_UNINT cpu_size, CPU_UNINT BaseAddress, CPU_UNINT cpuarch);
+CPU_INT PPC_Li( FILE *out, CPU_BYTE * cpu_buffer, CPU_UNINT cpu_pos, CPU_UNINT cpu_size, CPU_UNINT BaseAddress, CPU_UNINT cpuarch);
/* Export comment thing see m68k for example
* in dummy we do not show it, for it is diffent for each cpu
*/
-extern CPU_BYTE PPC_D[32];
-extern CPU_BYTE PPC_A[32];
-extern CPU_BYTE PPC_ds[32];
+
Modified: trunk/rosapps/devutils/cputointel/From/PPC/PPCBrain.c
URL: http://svn.reactos.org/svn/reactos/trunk/rosapps/devutils/cputointel/From/P…
==============================================================================
--- trunk/rosapps/devutils/cputointel/From/PPC/PPCBrain.c (original)
+++ trunk/rosapps/devutils/cputointel/From/PPC/PPCBrain.c Thu Jan 18 18:40:37 2007
@@ -59,10 +59,10 @@
cpuint = GetData32Le(&cpu_buffer[cpu_pos]);
- /* 0x38 Ld aslo known as Li */
- if ((cpuint - (cpuint & GetMaskByte32(cpuPPCInit_Ld))) == ConvertBitToByte32(cpuPPCInit_Ld))
+ /* 0xE = Li*/
+ if ((cpuint - (cpuint & GetMaskByte32(cpuPPCInit_Li))) == ConvertBitToByte32(cpuPPCInit_Li))
{
- retsize = PPC_Ld( outfp, cpu_buffer, cpu_pos, cpu_size,
+ retsize = PPC_Li( outfp, cpu_buffer, cpu_pos, cpu_size,
BaseAddress, cpuarch);
if (retsize<0)
retcode = 1;
Modified: trunk/rosapps/devutils/cputointel/From/PPC/PPCBrain.h
URL: http://svn.reactos.org/svn/reactos/trunk/rosapps/devutils/cputointel/From/P…
==============================================================================
--- trunk/rosapps/devutils/cputointel/From/PPC/PPCBrain.h (original)
+++ trunk/rosapps/devutils/cputointel/From/PPC/PPCBrain.h Thu Jan 18 18:40:37 2007
@@ -12,14 +12,17 @@
CPU_BYTE cpuPPCInit_Blr[32] = {0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,1,1,1,0};
-CPU_BYTE cpuPPCInit_Ld[32] = {0,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,1,1,1,0,0,0};
-CPU_BYTE cpuPPCInit_Ldu[32] = {1,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,1,1,1,0,0,0};
+/* xxxx xxxx xxxx xxxx DDD0 0000 xxxx xxDD
+ * 2222 2222 2222 2222 2222 2222 0011 1022 Li
+ */
+CPU_BYTE cpuPPCInit_Li[32] = {2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,1,1, 1,0,2,2};
+
/* mask */
-CPU_BYTE PPC_D[32] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0,0};
-CPU_BYTE PPC_A[32] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0};
-CPU_BYTE PPC_ds[32] = {0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+/*
+ * no mask we implement function getting the reg right
+ */
/* bit index
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
Modified: trunk/rosapps/devutils/cputointel/From/PPC/PPCopcode.c
URL: http://svn.reactos.org/svn/reactos/trunk/rosapps/devutils/cputointel/From/P…
==============================================================================
--- trunk/rosapps/devutils/cputointel/From/PPC/PPCopcode.c (original)
+++ trunk/rosapps/devutils/cputointel/From/PPC/PPCopcode.c Thu Jan 18 18:40:37 2007
@@ -26,7 +26,21 @@
* value 0 : wrong opcode or not vaild opcode
* value +1 and higher : who many byte we should add to cpu_pos
*/
-
+
+/* only for ppc */
+#define PPC_GetBitArray6toA(opcode) (((opcode & 0x3) << 3) | ((opcode & 0xE000) >> 13))
+
+
+
+
+CPU_UNINT PPC_GetBitArrayBto31(CPU_UNINT opcode)
+{
+ CPU_INT x1;
+ /* FIXME make it to a macro
+ * not tested to 100% yet */
+ x1 = ((opcode & 0xFFFF0000)>>16);
+ return x1;
+}
CPU_INT PPC_Blr( FILE *out, CPU_BYTE * cpu_buffer, CPU_UNINT cpu_pos,
@@ -47,23 +61,12 @@
}
-CPU_INT PPC_Ld( FILE *out, CPU_BYTE * cpu_buffer, CPU_UNINT cpu_pos,
+CPU_INT PPC_Li( FILE *out, CPU_BYTE * cpu_buffer, CPU_UNINT cpu_pos,
CPU_UNINT cpu_size, CPU_UNINT BaseAddress, CPU_UNINT cpuarch)
{
- CPU_UNINT formA;
- CPU_UNINT formD;
- CPU_UNINT formDS;
CPU_UNINT opcode;
opcode = GetData32Le(cpu_buffer);
- formD = (opcode & ConvertBitToByte32(PPC_D)) >> 6;
- formA = (opcode & ConvertBitToByte32(PPC_A)) >> 13;
- formDS = (opcode & ConvertBitToByte32(PPC_ds)) >> 15;
-
- if (formD != 0)
- {
- return 0;
- }
BaseAddress +=cpu_pos;
@@ -75,8 +78,8 @@
pMyBrainAnalys->op = OP_ANY_mov;
pMyBrainAnalys->type= 8 + 16; /* 8 dst reg, 16 imm */
pMyBrainAnalys->src_size = 16;
- pMyBrainAnalys->src = formDS;
- pMyBrainAnalys->dst = formA;
+ pMyBrainAnalys->src = PPC_GetBitArrayBto31(opcode);
+ pMyBrainAnalys->dst = PPC_GetBitArray6toA(opcode);
pMyBrainAnalys->memAdr=BaseAddress;
return 4;
Modified: trunk/rosapps/devutils/cputointel/OpCodePPC.txt
URL: http://svn.reactos.org/svn/reactos/trunk/rosapps/devutils/cputointel/OpCode…
==============================================================================
--- trunk/rosapps/devutils/cputointel/OpCodePPC.txt (original)
+++ trunk/rosapps/devutils/cputointel/OpCodePPC.txt Thu Jan 18 18:40:37 2007
@@ -20,14 +20,15 @@
Here how the primary opcode work
xxxx xxxx xxxx xxxx DDDS SSSS 3333 33DD
+
3 = it is the primary opcode
D = Destions register
S = Source reigters
- opcode
- ------------------------
- |bit order: 0123 45 67|
- ------- ------- ----------- ----
+ opcode
+ ------------------------
+ |bit order: 0123 45 67|
+ ------- ------- ----------- ----
34: | 0c 00 | | e1 93 | stw r31,12(r1) 0000 1100 0000 0000 1110 0001 | 1001 00 | 00
38: | 14 00 | | 01 90 | stw r0,20(r1) 0001 0100 0000 0000 0000 0001 | 1001 00 | 11
------- ------- ---------
@@ -41,8 +42,7 @@
\ /
The address offset 12 or 20
-
-
+
---------------------------------------------------------
|bit order: pos 1111 1111 1111 1111 0000 0000 0000 0000 |
| 89AB CDEF 0123 4567 89AB CDEF 0123 4567 |
Modified: trunk/rosapps/devutils/cputointel/ReadMe.txt
URL: http://svn.reactos.org/svn/reactos/trunk/rosapps/devutils/cputointel/ReadMe…
==============================================================================
--- trunk/rosapps/devutils/cputointel/ReadMe.txt (original)
+++ trunk/rosapps/devutils/cputointel/ReadMe.txt Thu Jan 18 18:40:37 2007
@@ -2,22 +2,25 @@
The Idea
-The idea is to convert a binary file or win pe file
+The idea is to converting binary files or win pe files
from one cpu to another cpu, But it does not exists
plan to port over diffent hardware architect like
how diffent hw comucate, example x86 DMA controller
-to PPC like. It is only to convert the the binary or
-pe file to another cpu. it mean a user mode apps
-will always be ported, but if it self modify code
-it will not work. But it exists a idea to deal with
-self modify code.
+to PPC like that stuff. It is only to convert the
+binary or pe files to another cpu. it mean a user
+mode apps will always be ported, but if it self
+modify code it will not work. But it exists idea how
+to deal with self modify code.
The idea to handling self modify code
-The idea is to add a small emulator that
-runing the apps or adding a anylasuing process
-to dectect self modify code and extract it
-this is hard thing todo. almost imposible
+The idea is to add a small emulator or adding
+anaylysing process to dectect self modify code
+and extract it. This is very hard part todo, some say
+imposible, some other say almost imposble. and I say
+it is posible todo but extream hard todo. for it is
+very diffcul to dectect self modify code with a
+analysing process.
Why the name are CpuToIntel
Author: fireball
Date: Thu Jan 18 18:09:04 2007
New Revision: 25510
URL: http://svn.reactos.org/svn/reactos?rev=25510&view=rev
Log:
Merge 25117.
Revision: 25117
Author: greatlrd
Date: 20:39:01, 10 december 2006.
Message:
Commit the patch from bug 1874 even if it does not use the RDMSR and WRMSR measure method, we need to use the RDMSR and WRMSR instructions for dual core and only if CPU supports them (see Intel documentations AP-485 to see how to do it). The patch is from HTO (Dmitry Gorbachev). Bugfix detections of RTSC support for single and dual core by me, adding check if the CPU supports RDMSR and WRMSR and send a true or false value to GetCpuSpeed, so we know which method we should use. HTO patch should be used when it is 'false', otherwise we should use the RDMSR and WRMSR measure method.
Modified:
branches/winldr/arch/i386/hwcpu.c
Modified: branches/winldr/arch/i386/hwcpu.c
URL: http://svn.reactos.org/svn/reactos/branches/winldr/arch/i386/hwcpu.c?rev=25…
==============================================================================
--- branches/winldr/arch/i386/hwcpu.c (original)
+++ branches/winldr/arch/i386/hwcpu.c Thu Jan 18 18:09:04 2007
@@ -24,6 +24,12 @@
#define NDEBUG
#include <debug.h>
+#define HZ (100)
+#define CLOCK_TICK_RATE (1193182)
+#define LATCH (CLOCK_TICK_RATE / HZ)
+#define CALIBRATE_LATCH (5 * LATCH)
+#define CALIBRATE_TIME (5 * 1000020/HZ)
+
#define MP_FP_SIGNATURE 0x5F504D5F /* "_MP_" */
#define MP_CT_SIGNATURE 0x504D4350 /* "PCMP" */
@@ -73,17 +79,44 @@
/* FUNCTIONS ****************************************************************/
static ULONG
-GetCpuSpeed(VOID)
+GetCpuSpeed(BOOLEAN DualCoreSpeedMesure)
{
ULONGLONG Timestamp1;
ULONGLONG Timestamp2;
ULONGLONG Diff;
+ ULONG Count = 0;
+
+ /*
+ FIXME
+ if the DualCoreSpeedMesure is true we need
+ use the wrmsr and rdmsr to mesure the speed
+
+ The rdtc are outdate to use if cpu support
+ the wrmsr and rdmsr, see intel doc AP-485
+ for more informations and how to use it.
+
+ Follow code is good on cpu that does not
+ support dual core or have a mmx unit or
+ more.
+ */
+
+
+ /* Initialise timer channel 2 */
+ /* Set the Gate high, disable speaker */
+ WRITE_PORT_UCHAR((PUCHAR)0x61, (READ_PORT_UCHAR((PUCHAR)0x61) & ~0x02) | 0x01);
+ WRITE_PORT_UCHAR((PUCHAR)0x43, 0xB0); /* binary, mode 0, LSB/MSB, ch 2 */
+ WRITE_PORT_UCHAR((PUCHAR)0x42, CALIBRATE_LATCH & 0xff); /* LSB */
+ WRITE_PORT_UCHAR((PUCHAR)0x42, CALIBRATE_LATCH >> 8); /* MSB */
/* Read TSC (Time Stamp Counter) */
Timestamp1 = RDTSC();
- /* Wait for 0.1 seconds (= 100 milliseconds = 100000 microseconds)*/
- StallExecutionProcessor(100000);
+ /* Wait */
+ do
+ {
+ Count++;
+ }
+ while ((READ_PORT_UCHAR((PUCHAR)0x61) & 0x20) == 0);
/* Read TSC (Time Stamp Counter) again */
Timestamp2 = RDTSC();
@@ -98,7 +131,7 @@
Diff = Timestamp2 + (((ULONGLONG)-1) - Timestamp1);
}
- return (ULONG)(Diff / 100000);
+ return (ULONG)(Diff / CALIBRATE_TIME);
}
@@ -123,7 +156,7 @@
LONG Error;
BOOLEAN SupportTSC = FALSE;
ULONG CpuSpeed;
-
+ BOOLEAN DualCoreSpeedMesure = FALSE;
/* Create the CPU instance key */
Error = RegCreateKey(CpuKey,
@@ -169,8 +202,12 @@
(unsigned int)((eax >> 4) & 0x0F),
(unsigned int)(eax & 0x0F));
FeatureSet = edx;
- if (((eax >> 8) & 0x0F) >= 5)
+
+ if ((FeatureSet & 0x10) == 0x10)
SupportTSC = TRUE;
+
+ if ((FeatureSet & 0x20) == 0x20)
+ DualCoreSpeedMesure = TRUE;
/* Check if Extended CPUID information is supported */
GetCpuid(0x80000000, &eax, &ebx, &ecx, &edx);
@@ -283,7 +320,7 @@
/* Set '~MHz' value (CPU only) */
if (SupportTSC)
{
- CpuSpeed = GetCpuSpeed();
+ CpuSpeed = GetCpuSpeed(DualCoreSpeedMesure);
Error = RegSetValue(CpuInstKey,
L"~MHz",
@@ -467,9 +504,19 @@
/* FIXME: Set 'Update Status' value (CPU only) */
/* Set '~MHz' value (CPU only) */
- if (((CpuEntry->CpuSignature >> 8) & 0x0F) >= 5)
- {
- CpuSpeed = GetCpuSpeed();
+
+
+ if ((CpuEntry->FeatureFlags & 0x10) == 0x10)
+ {
+ if ((CpuEntry->FeatureFlags & 0x20) == 0x20)
+ {
+ CpuSpeed = GetCpuSpeed(TRUE);
+ }
+ else
+ {
+ DbgPrint((DPRINT_HWDETECT, "Does not support MSR that are need for mesure the speed correct\n", (int)Error));
+ CpuSpeed = GetCpuSpeed(FALSE);
+ }
Error = RegSetValue(CpuInstKey,
L"~MHz",
@@ -477,10 +524,11 @@
(PCHAR)&CpuSpeed,
sizeof(ULONG));
if (Error != ERROR_SUCCESS)
- {
- DbgPrint((DPRINT_HWDETECT, "RegSetValue() failed (Error %u)\n", (int)Error));
- }
- }
+ {
+
+ DbgPrint((DPRINT_HWDETECT, "RegSetValue() failed (Error %u)\n", (int)Error));
+ }
+ }
}
Author: greatlrd
Date: Thu Jan 18 16:43:17 2007
New Revision: 25507
URL: http://svn.reactos.org/svn/reactos?rev=25507&view=rev
Log:
Expain how the bit order works and how get the opcode. The IBM and freescale manual for ppc cpu are not good expain it.
now I got less headic, and got understainf how to decoding the manual and how the opcode are store.
Modified:
trunk/rosapps/devutils/cputointel/OpCodePPC.txt
Modified: trunk/rosapps/devutils/cputointel/OpCodePPC.txt
URL: http://svn.reactos.org/svn/reactos/trunk/rosapps/devutils/cputointel/OpCode…
==============================================================================
--- trunk/rosapps/devutils/cputointel/OpCodePPC.txt (original)
+++ trunk/rosapps/devutils/cputointel/OpCodePPC.txt Thu Jan 18 16:43:17 2007
@@ -9,9 +9,44 @@
1 = mean bit is set
2 = mean this bit can be 0 or 1
-opcode Name Desciptions
-
+opcode Name Desciptions
0010 0000 0000 0000 1000 0000 0100 1110 blr return from a functions
0222 2222 2222 2222 2222 2222 0011 1000 Li reg,#imm move a value to a register
+
+
+
+
+Here how the primary opcode work
+xxxx xxxx xxxx xxxx DDDS SSSS 3333 33DD
+
+3 = it is the primary opcode
+D = Destions register
+S = Source reigters
+ opcode
+ ------------------------
+ |bit order: 0123 45 67|
+ ------- ------- ----------- ----
+34: | 0c 00 | | e1 93 | stw r31,12(r1) 0000 1100 0000 0000 1110 0001 | 1001 00 | 00
+38: | 14 00 | | 01 90 | stw r0,20(r1) 0001 0100 0000 0000 0000 0001 | 1001 00 | 11
+ ------- ------- ---------
+ | |
+ | |--> Get source register R0-R31 (0xE1 & 0x1F) = 1
+ | |
+ | |--> Get Dest register R0-R31 ((0xE1 & 0xE0)>>5) | ((0x90 & 0x3)<<3) = 31 or 0
+ | | (The adding the two last bit on the end is maybe wrong need examine it)
+ | |
+ | --> Get the opcpde (0x90 & 0xFC)
+ \ /
+
+ The address offset 12 or 20
+
+
+ ---------------------------------------------------------
+|bit order: pos 1111 1111 1111 1111 0000 0000 0000 0000 |
+| 89AB CDEF 0123 4567 89AB CDEF 0123 4567 |
+|---------------------------------------------------------|
+| bits 0000 1100 0000 0000 1110 0001 1001 0000 |
+ ---------------------------------------------------------
+
Author: greatlrd
Date: Thu Jan 18 15:04:24 2007
New Revision: 25506
URL: http://svn.reactos.org/svn/reactos?rev=25506&view=rev
Log:
Adding a opcode list, which opcode we are supportin convert from
Added:
trunk/rosapps/devutils/cputointel/OpCodePPC.txt (with props)
Added: trunk/rosapps/devutils/cputointel/OpCodePPC.txt
URL: http://svn.reactos.org/svn/reactos/trunk/rosapps/devutils/cputointel/OpCode…
==============================================================================
--- trunk/rosapps/devutils/cputointel/OpCodePPC.txt (added)
+++ trunk/rosapps/devutils/cputointel/OpCodePPC.txt Thu Jan 18 15:04:24 2007
@@ -1,0 +1,17 @@
+
+PowerPC 32bits
+
+reg = R0-R31
+#imm = a value you set
+
+Bit expain
+0 = mean bit is zero
+1 = mean bit is set
+2 = mean this bit can be 0 or 1
+
+opcode Name Desciptions
+
+0010 0000 0000 0000 1000 0000 0100 1110 blr return from a functions
+
+0222 2222 2222 2222 2222 2222 0011 1000 Li reg,#imm move a value to a register
+
Propchange: trunk/rosapps/devutils/cputointel/OpCodePPC.txt
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