Ros-diffs February 2008

ros-diffs@reactos.org

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460 discussions

[ros-arm-bringup] 32314: The kernel entrypoint is called KiSystemStartup, not NtProcessStartup. On ARM, don't prepend underscore to the kernel entrypoint. We now correctly jump into the kernel entrypoint, instead of random code!

by ros-arm-bringup＠svn.reactos.org

Author: ros-arm-bringup Date: Tue Feb 12 09:15:35 2008 New Revision: 32314 URL: http://svn.reactos.org/svn/reactos?rev=32314&view=rev Log: The kernel entrypoint is called KiSystemStartup, not NtProcessStartup. On ARM, don't prepend underscore to the kernel entrypoint. We now correctly jump into the kernel entrypoint, instead of random code! Modified: trunk/reactos/tools/rbuild/backend/mingw/modulehandler.cpp trunk/reactos/tools/rbuild/module.cpp Modified: trunk/reactos/tools/rbuild/backend/mingw/modulehandler.cpp URL: http://svn.reactos.org/svn/reactos/trunk/reactos/tools/rbuild/backend/mingw… ============================================================================== --- trunk/reactos/tools/rbuild/backend/mingw/modulehandler.cpp (original) +++ trunk/reactos/tools/rbuild/backend/mingw/modulehandler.cpp Tue Feb 12 09:15:35 2008 @@ -2623,9 +2623,10 @@ string dependencies = linkDepsMacro + " " + objectsMacro; - string linkerParameters = ssprintf ( "-Wl,--subsystem,native -Wl,--entry,%s -Wl,--image-base,%s", - module.GetEntryPoint(true).c_str (), - module.baseaddress.c_str () ); + string linkerParameters = ssprintf ( "-Wl,--subsystem,native -Wl,--entry,%s -Wl,--image-base,%s", + module.GetEntryPoint(!(Environment::GetArch() == "arm")).c_str (), + module.baseaddress.c_str () ); + GenerateLinkerCommand ( dependencies, "${gcc}", linkerParameters + " $(NTOSKRNL_SHARED)", Modified: trunk/reactos/tools/rbuild/module.cpp URL: http://svn.reactos.org/svn/reactos/trunk/reactos/tools/rbuild/module.cpp?re… ============================================================================== --- trunk/reactos/tools/rbuild/module.cpp (original) +++ trunk/reactos/tools/rbuild/module.cpp Tue Feb 12 09:15:35 2008 @@ -1033,7 +1033,7 @@ switch ( type ) { case Kernel: - return "NtProcessStartup"; + return "KiSystemStartup"; case KernelModeDLL: case KernelModeDriver: return "DriverEntry@8";

16 years, 8 months

[ros-arm-bringup] 32313: Move the entrypoint and startup code in boot.s. Write ksarm.h and kxarm.h headers, defining the ARM Assembly ABI. Rewrite the ARM assembler files we currently have to match the ABI.

by ros-arm-bringup＠svn.reactos.org

Author: ros-arm-bringup Date: Tue Feb 12 08:55:12 2008 New Revision: 32313 URL: http://svn.reactos.org/svn/reactos?rev=32313&view=rev Log: Move the entrypoint and startup code in boot.s. Write ksarm.h and kxarm.h headers, defining the ARM Assembly ABI. Rewrite the ARM assembler files we currently have to match the ABI. Added: trunk/reactos/ntoskrnl/include/internal/arm/ksarm.h (with props) trunk/reactos/ntoskrnl/include/internal/arm/kxarm.h (with props) trunk/reactos/ntoskrnl/ke/arm/boot.s (with props) Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/boot.s trunk/reactos/ntoskrnl/ke/arm/stubs_asm.s trunk/reactos/ntoskrnl/ntoskrnl.rbuild Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/boot.s URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/arch/… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/arch/arm/boot.s (original) +++ trunk/reactos/boot/freeldr/freeldr/arch/arm/boot.s Tue Feb 12 08:55:12 2008 @@ -6,29 +6,14 @@ * PROGRAMMERS: ReactOS Portable Systems Group */ -/* INCLUDES *******************************************************************/ + .title "ARM FreeLDR Entry Point" + .include "ntoskrnl/include/internal/arm/kxarm.h" + .include "ntoskrnl/include/internal/arm/ksarm.h" -//#include <kxarm.h> - -#define CPSR_IRQ_DISABLE 0x80 -#define CPSR_FIQ_DISABLE 0x40 -#define CPSR_THUMB_ENABLE 0x20 - -#define C1_MMU_CONTROL 0x01 -#define C1_ALIGNMENT_CONTROL 0x02 -#define C1_DCACHE_CONTROL 0x04 -#define C1_ICACHE_CONTROL 0x1000 -#define C1_VECTOR_CONTROL 0x2000 - -/* GLOBALS ********************************************************************/ - -.global _start -.global ArmTranslationTable -.section startup - -/* BOOT CODE ******************************************************************/ - -_start: + .section startup + NESTED_ENTRY _start + PROLOG_END _start + // // C entrypoint // @@ -67,8 +52,7 @@ // r0 contains the ARM_BOARD_CONFIGURATION_DATA structure // bx lr - -/* BOOT STACK *****************************************************************/ + ENTRY_END _start L_BootStackEnd: .long BootStackEnd @@ -81,9 +65,8 @@ .space 0x4000 BootStackEnd: .long 0 - -/* INITIAL PAGE TABLE *********************************************************/ .section pagedata +.global ArmTranslationTable ArmTranslationTable: .space 0x4000 Added: trunk/reactos/ntoskrnl/include/internal/arm/ksarm.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/include/internal/… ============================================================================== --- trunk/reactos/ntoskrnl/include/internal/arm/ksarm.h (added) +++ trunk/reactos/ntoskrnl/include/internal/arm/ksarm.h Tue Feb 12 08:55:12 2008 @@ -1,0 +1,9 @@ +.equ CPSR_IRQ_DISABLE, 0x80 +.equ CPSR_FIQ_DISABLE, 0x40 +.equ CPSR_THUMB_ENABLE, 0x20 + +.equ C1_MMU_CONTROL, 0x01 +.equ C1_ALIGNMENT_CONTROL, 0x02 +.equ C1_DCACHE_CONTROL, 0x04 +.equ C1_ICACHE_CONTROL, 0x1000 +.equ C1_VECTOR_CONTROL, 0x2000 Propchange: trunk/reactos/ntoskrnl/include/internal/arm/ksarm.h ------------------------------------------------------------------------------ svn:eol-style = native Propchange: trunk/reactos/ntoskrnl/include/internal/arm/ksarm.h ------------------------------------------------------------------------------ svn:mime-type = text/plain Added: trunk/reactos/ntoskrnl/include/internal/arm/kxarm.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/include/internal/… ============================================================================== --- trunk/reactos/ntoskrnl/include/internal/arm/kxarm.h (added) +++ trunk/reactos/ntoskrnl/include/internal/arm/kxarm.h Tue Feb 12 08:55:12 2008 @@ -1,0 +1,21 @@ + +.macro TEXTAREA + .section text, "rx" + .align 2 +.endm + +.macro NESTED_ENTRY Name + .global &Name + .align 2 + .func &Name + &Name: +.endm + +.macro PROLOG_END Name + prolog_&Name: +.endm + +.macro ENTRY_END Name + end_&Name: + .endfunc +.endm Propchange: trunk/reactos/ntoskrnl/include/internal/arm/kxarm.h ------------------------------------------------------------------------------ svn:eol-style = native Propchange: trunk/reactos/ntoskrnl/include/internal/arm/kxarm.h ------------------------------------------------------------------------------ svn:mime-type = text/plain Added: trunk/reactos/ntoskrnl/ke/arm/boot.s URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ke/arm/boot.s?rev… ============================================================================== --- trunk/reactos/ntoskrnl/ke/arm/boot.s (added) +++ trunk/reactos/ntoskrnl/ke/arm/boot.s Tue Feb 12 08:55:12 2008 @@ -1,0 +1,22 @@ +/* + * PROJECT: ReactOS Kernel + * LICENSE: GPL - See COPYING in the top level directory + * FILE: ntoskrnl/ke/arm/boot.s + * PURPOSE: Implements the kernel entry point for ARM machines + * PROGRAMMERS: ReactOS Portable Systems Group + */ + + .title "ARM Kernel Entry Point" + .include "ntoskrnl/include/internal/arm/kxarm.h" + .include "ntoskrnl/include/internal/arm/ksarm.h" + + TEXTAREA + NESTED_ENTRY KiSystemStartup + PROLOG_END KiSystemStartup + + // + // Do stuff! + // + b . + + ENTRY_END KiSystemStartup Propchange: trunk/reactos/ntoskrnl/ke/arm/boot.s ------------------------------------------------------------------------------ svn:eol-style = native Propchange: trunk/reactos/ntoskrnl/ke/arm/boot.s ------------------------------------------------------------------------------ svn:mime-type = text/plain Modified: trunk/reactos/ntoskrnl/ke/arm/stubs_asm.s URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ke/arm/stubs_asm.… ============================================================================== --- trunk/reactos/ntoskrnl/ke/arm/stubs_asm.s (original) +++ trunk/reactos/ntoskrnl/ke/arm/stubs_asm.s Tue Feb 12 08:55:12 2008 @@ -111,7 +111,6 @@ GENERATE_ARM_STUB KeDisableInterrupts GENERATE_ARM_STUB KeContextToTrapFrame GENERATE_ARM_STUB KiDispatchException -GENERATE_ARM_STUB KiSystemStartup GENERATE_ARM_STUB NtSetLdtEntries GENERATE_ARM_STUB NtRaiseException GENERATE_ARM_STUB NtCallbackReturn Modified: trunk/reactos/ntoskrnl/ntoskrnl.rbuild URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ntoskrnl.rbuild?r… ============================================================================== --- trunk/reactos/ntoskrnl/ntoskrnl.rbuild (original) +++ trunk/reactos/ntoskrnl/ntoskrnl.rbuild Tue Feb 12 08:55:12 2008 @@ -59,7 +59,8 @@ </if> <if property="ARCH" value="arm"> <directory name="arm"> - <file>stubs_asm.s</file> + <file first="true">boot.s</file> + <file>stubs_asm.s</file> <file>stubs.c</file> </directory> </if>

16 years, 8 months

[ros-arm-bringup] 32312: fixed math

by ros-arm-bringup＠svn.reactos.org

Author: ros-arm-bringup Date: Tue Feb 12 08:07:08 2008 New Revision: 32312 URL: http://svn.reactos.org/svn/reactos?rev=32312&view=rev Log: fixed math Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/loader.c Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/loader.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/arch/… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/arch/arm/loader.c (original) +++ trunk/reactos/boot/freeldr/freeldr/arch/arm/loader.c Tue Feb 12 08:07:08 2008 @@ -72,7 +72,7 @@ Pte.L1.Section.Ignored = Pte.L1.Section.Ignored1 = 0; // - // Map KSEG0 (0x80000000 - 0xA0000000) to 0x00000000 - 0x80000000 + // Map KSEG0 (0x80000000 - 0xA0000000) to 0x00000000 - 0x20000000 // In this way, the KERNEL_PHYS_ADDR (0x800000) becomes 0x80800000 // which is the entrypoint, just like on x86. //

16 years, 8 months

[ros-arm-bringup] 32311: Better organize FreeLDR ARM files -- there are no more stubs now. We have the ReactOS kernel loader in loader.c, just like on x86, and the ARM FreeLDR HAL/Mach routines in macharm.c

by ros-arm-bringup＠svn.reactos.org

Author: ros-arm-bringup Date: Tue Feb 12 07:22:39 2008 New Revision: 32311 URL: http://svn.reactos.org/svn/reactos?rev=32311&view=rev Log: Better organize FreeLDR ARM files -- there are no more stubs now. We have the ReactOS kernel loader in loader.c, just like on x86, and the ARM FreeLDR HAL/Mach routines in macharm.c Added: trunk/reactos/boot/freeldr/freeldr/arch/arm/loader.c - copied, changed from r32310, trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c Removed: trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/macharm.c trunk/reactos/boot/freeldr/freeldr/freeldr_arch.rbuild Copied: trunk/reactos/boot/freeldr/freeldr/arch/arm/loader.c (from r32310, trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c) URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/arch/… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c (original) +++ trunk/reactos/boot/freeldr/freeldr/arch/arm/loader.c Tue Feb 12 07:22:39 2008 @@ -1,8 +1,8 @@ /* * PROJECT: ReactOS Boot Loader * LICENSE: GPL - See COPYING in the top level directory - * FILE: boot/freeldr/arch/arm/stubs.c - * PURPOSE: Non-completed ARM hardware-specific routines + * FILE: boot/freeldr/arch/arm/loader.c + * PURPOSE: ARM Kernel Loader * PROGRAMMERS: ReactOS Portable Systems Group */ @@ -22,31 +22,6 @@ extern ROS_KERNEL_ENTRY_POINT KernelEntryPoint; /* FUNCTIONS ******************************************************************/ - -BOOLEAN -ArmDiskGetDriveGeometry(IN ULONG DriveNumber, - OUT PGEOMETRY Geometry) -{ - ASSERT(gRamDiskBase == NULL); - return FALSE; -} - -BOOLEAN -ArmDiskReadLogicalSectors(IN ULONG DriveNumber, - IN ULONGLONG SectorNumber, - IN ULONG SectorCount, - IN PVOID Buffer) -{ - ASSERT(gRamDiskBase == NULL); - return FALSE; -} - -ULONG -ArmDiskGetCacheableBlockCount(IN ULONG DriveNumber) -{ - ASSERT(gRamDiskBase == NULL); - return FALSE; -} VOID ArmSetupPageDirectory(VOID) @@ -182,123 +157,6 @@ // } -PCONFIGURATION_COMPONENT_DATA -ArmHwDetect(VOID) -{ - PCONFIGURATION_COMPONENT_DATA RootNode; - - // - // Create the root node - // - FldrCreateSystemKey(&RootNode); - - // - // Write null component information - // - FldrSetComponentInformation(RootNode, - 0x0, - 0x0, - 0xFFFFFFFF); - - // - // TODO: - // There's no such thing as "PnP" on embedded hardware. - // The boot loader will send us a device tree, similar to ACPI - // or OpenFirmware device trees, and we will convert it to ARC. - // - - // - // Return the root node - // - return RootNode; -} - -ULONG -ArmMemGetMemoryMap(OUT PBIOS_MEMORY_MAP BiosMemoryMap, - IN ULONG MaxMemoryMapSize) -{ - // - // Return whatever the board returned to us (CS0 Base + Size and FLASH0) - // - RtlCopyMemory(BiosMemoryMap, - ArmBoardBlock->MemoryMap, - ArmBoardBlock->MemoryMapEntryCount * sizeof(BIOS_MEMORY_MAP)); - return ArmBoardBlock->MemoryMapEntryCount; -} - -VOID -MachInit(IN PCCH CommandLine) -{ - // - // Setup board-specific ARM routines - // - switch (ArmBoardBlock->BoardType) - { - // - // Check for Feroceon-base boards - // - case MACH_TYPE_FEROCEON: - - // - // These boards use a UART16550. Set us up for 115200 bps - // - ArmFeroSerialInit(115200); - MachVtbl.ConsPutChar = ArmFeroPutChar; - MachVtbl.ConsKbHit = ArmFeroKbHit; - MachVtbl.ConsGetCh = ArmFeroGetCh; - break; - - // - // Check for ARM Versatile PB boards - // - case MACH_TYPE_VERSATILE_PB: - - // - // These boards use a PrimeCell UART (PL011) - // - ArmVersaSerialInit(115200); - MachVtbl.ConsPutChar = ArmVersaPutChar; - MachVtbl.ConsKbHit = ArmVersaKbHit; - MachVtbl.ConsGetCh = ArmVersaGetCh; - break; - - default: - ASSERT(FALSE); - } - - // - // Setup generic ARM routines for all boards - // - MachVtbl.PrepareForReactOS = ArmPrepareForReactOS; - MachVtbl.GetMemoryMap = ArmMemGetMemoryMap; - MachVtbl.HwDetect = ArmHwDetect; - - // - // Setup disk I/O routines, switch to ramdisk ones for non-NAND boot - // - MachVtbl.DiskReadLogicalSectors = ArmDiskReadLogicalSectors; - MachVtbl.DiskGetDriveGeometry = ArmDiskGetDriveGeometry; - MachVtbl.DiskGetCacheableBlockCount = ArmDiskGetCacheableBlockCount; - RamDiskSwitchFromBios(); - - // - // Now set default disk handling routines -- we don't need to override - // - MachVtbl.DiskGetBootVolume = DiskGetBootVolume; - MachVtbl.DiskGetSystemVolume = DiskGetSystemVolume; - MachVtbl.DiskGetBootPath = DiskGetBootPath; - MachVtbl.DiskGetBootDevice = DiskGetBootDevice; - MachVtbl.DiskBootingFromFloppy = DiskBootingFromFloppy; - MachVtbl.DiskNormalizeSystemPath = DiskNormalizeSystemPath; - MachVtbl.DiskGetPartitionEntry = DiskGetPartitionEntry; - - // - // We can now print to the console - // - TuiPrintf("%s for ARM\n", GetFreeLoaderVersionString()); - TuiPrintf("Bootargs: %s\n", CommandLine); -} - VOID FrLdrStartup(IN ULONG Magic) { Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/macharm.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/arch/… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/arch/arm/macharm.c (original) +++ trunk/reactos/boot/freeldr/freeldr/arch/arm/macharm.c Tue Feb 12 07:22:39 2008 @@ -14,6 +14,7 @@ PARM_BOARD_CONFIGURATION_BLOCK ArmBoardBlock; ULONG BootDrive, BootPartition; +VOID ArmPrepareForReactOS(IN BOOLEAN Setup); /* FUNCTIONS ******************************************************************/ @@ -43,3 +44,144 @@ BootMain(ArmBoardBlock->CommandLine); } +BOOLEAN +ArmDiskGetDriveGeometry(IN ULONG DriveNumber, + OUT PGEOMETRY Geometry) +{ + ASSERT(gRamDiskBase == NULL); + return FALSE; +} + +BOOLEAN +ArmDiskReadLogicalSectors(IN ULONG DriveNumber, + IN ULONGLONG SectorNumber, + IN ULONG SectorCount, + IN PVOID Buffer) +{ + ASSERT(gRamDiskBase == NULL); + return FALSE; +} + +ULONG +ArmDiskGetCacheableBlockCount(IN ULONG DriveNumber) +{ + ASSERT(gRamDiskBase == NULL); + return FALSE; +} + +PCONFIGURATION_COMPONENT_DATA +ArmHwDetect(VOID) +{ + PCONFIGURATION_COMPONENT_DATA RootNode; + + // + // Create the root node + // + FldrCreateSystemKey(&RootNode); + + // + // Write null component information + // + FldrSetComponentInformation(RootNode, + 0x0, + 0x0, + 0xFFFFFFFF); + + // + // TODO: + // There's no such thing as "PnP" on embedded hardware. + // The boot loader will send us a device tree, similar to ACPI + // or OpenFirmware device trees, and we will convert it to ARC. + // + + // + // Return the root node + // + return RootNode; +} + +ULONG +ArmMemGetMemoryMap(OUT PBIOS_MEMORY_MAP BiosMemoryMap, + IN ULONG MaxMemoryMapSize) +{ + // + // Return whatever the board returned to us (CS0 Base + Size and FLASH0) + // + RtlCopyMemory(BiosMemoryMap, + ArmBoardBlock->MemoryMap, + ArmBoardBlock->MemoryMapEntryCount * sizeof(BIOS_MEMORY_MAP)); + return ArmBoardBlock->MemoryMapEntryCount; +} + +VOID +MachInit(IN PCCH CommandLine) +{ + // + // Setup board-specific ARM routines + // + switch (ArmBoardBlock->BoardType) + { + // + // Check for Feroceon-base boards + // + case MACH_TYPE_FEROCEON: + + // + // These boards use a UART16550. Set us up for 115200 bps + // + ArmFeroSerialInit(115200); + MachVtbl.ConsPutChar = ArmFeroPutChar; + MachVtbl.ConsKbHit = ArmFeroKbHit; + MachVtbl.ConsGetCh = ArmFeroGetCh; + break; + + // + // Check for ARM Versatile PB boards + // + case MACH_TYPE_VERSATILE_PB: + + // + // These boards use a PrimeCell UART (PL011) + // + ArmVersaSerialInit(115200); + MachVtbl.ConsPutChar = ArmVersaPutChar; + MachVtbl.ConsKbHit = ArmVersaKbHit; + MachVtbl.ConsGetCh = ArmVersaGetCh; + break; + + default: + ASSERT(FALSE); + } + + // + // Setup generic ARM routines for all boards + // + MachVtbl.PrepareForReactOS = ArmPrepareForReactOS; + MachVtbl.GetMemoryMap = ArmMemGetMemoryMap; + MachVtbl.HwDetect = ArmHwDetect; + + // + // Setup disk I/O routines, switch to ramdisk ones for non-NAND boot + // + MachVtbl.DiskReadLogicalSectors = ArmDiskReadLogicalSectors; + MachVtbl.DiskGetDriveGeometry = ArmDiskGetDriveGeometry; + MachVtbl.DiskGetCacheableBlockCount = ArmDiskGetCacheableBlockCount; + RamDiskSwitchFromBios(); + + // + // Now set default disk handling routines -- we don't need to override + // + MachVtbl.DiskGetBootVolume = DiskGetBootVolume; + MachVtbl.DiskGetSystemVolume = DiskGetSystemVolume; + MachVtbl.DiskGetBootPath = DiskGetBootPath; + MachVtbl.DiskGetBootDevice = DiskGetBootDevice; + MachVtbl.DiskBootingFromFloppy = DiskBootingFromFloppy; + MachVtbl.DiskNormalizeSystemPath = DiskNormalizeSystemPath; + MachVtbl.DiskGetPartitionEntry = DiskGetPartitionEntry; + + // + // We can now print to the console + // + TuiPrintf("%s for ARM\n", GetFreeLoaderVersionString()); + TuiPrintf("Bootargs: %s\n", CommandLine); +} Removed: trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/arch/… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c (original) +++ trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c (removed) @@ -1,322 +1,0 @@ -/* - * PROJECT: ReactOS Boot Loader - * LICENSE: GPL - See COPYING in the top level directory - * FILE: boot/freeldr/arch/arm/stubs.c - * PURPOSE: Non-completed ARM hardware-specific routines - * PROGRAMMERS: ReactOS Portable Systems Group - */ - -/* INCLUDES *******************************************************************/ - -#include <freeldr.h> -#include <internal/arm/ke.h> -#include <internal/arm/mm.h> -#include <internal/arm/intrin_i.h> - -/* GLOBALS ********************************************************************/ - -ULONG PageDirectoryStart, PageDirectoryEnd; -LOADER_PARAMETER_BLOCK ArmLoaderBlock; -LOADER_PARAMETER_EXTENSION ArmExtension; -extern ARM_TRANSLATION_TABLE ArmTranslationTable; -extern ROS_KERNEL_ENTRY_POINT KernelEntryPoint; - -/* FUNCTIONS ******************************************************************/ - -BOOLEAN -ArmDiskGetDriveGeometry(IN ULONG DriveNumber, - OUT PGEOMETRY Geometry) -{ - ASSERT(gRamDiskBase == NULL); - return FALSE; -} - -BOOLEAN -ArmDiskReadLogicalSectors(IN ULONG DriveNumber, - IN ULONGLONG SectorNumber, - IN ULONG SectorCount, - IN PVOID Buffer) -{ - ASSERT(gRamDiskBase == NULL); - return FALSE; -} - -ULONG -ArmDiskGetCacheableBlockCount(IN ULONG DriveNumber) -{ - ASSERT(gRamDiskBase == NULL); - return FALSE; -} - -VOID -ArmSetupPageDirectory(VOID) -{ - ARM_TTB_REGISTER TtbRegister; - ARM_DOMAIN_REGISTER DomainRegister; - ARM_PTE Pte; - ULONG i; - PARM_TRANSLATION_TABLE TranslationTable; - - // - // Allocate translation table buffer. - // During bootstrap, this will be a simple L1 (Master) Page Table with - // Section entries for KSEG0 and the first MB of RAM. - // - TranslationTable = &ArmTranslationTable; - if (!TranslationTable) return; - - // - // Set it as the TTB - // - TtbRegister.AsUlong = (ULONG)TranslationTable; - ASSERT(TtbRegister.Reserved == 0); - KeArmTranslationTableRegisterSet(TtbRegister); - - // - // Use Domain 0, enforce AP bits (client) - // - DomainRegister.AsUlong = 0; - DomainRegister.Domain0 = ClientDomain; - KeArmDomainRegisterSet(DomainRegister); - - // - // Set Fault PTEs everywhere - // - RtlZeroMemory(TranslationTable, 4096 * sizeof(ARM_PTE)); - - // - // Build the template PTE - // - Pte.L1.Section.Type = SectionPte; - Pte.L1.Section.Buffered = FALSE; - Pte.L1.Section.Cached = FALSE; - Pte.L1.Section.Reserved = 1; // ARM926EJ-S manual recommends setting to 1 - Pte.L1.Section.Domain = Domain0; - Pte.L1.Section.Access = SupervisorAccess; - Pte.L1.Section.BaseAddress = 0; - Pte.L1.Section.Ignored = Pte.L1.Section.Ignored1 = 0; - - // - // Map KSEG0 (0x80000000 - 0xA0000000) to 0x00000000 - 0x80000000 - // In this way, the KERNEL_PHYS_ADDR (0x800000) becomes 0x80800000 - // which is the entrypoint, just like on x86. - // - for (i = (KSEG0_BASE >> TTB_SHIFT); i < ((KSEG0_BASE + 0x20000000) >> TTB_SHIFT); i++) - { - // - // Write PTE and update the base address (next MB) for the next one - // - TranslationTable->Pte[i] = Pte; - Pte.L1.Section.BaseAddress++; - } - - // - // Identity map the first MB of memory as well - // - Pte.L1.Section.BaseAddress = 0; - TranslationTable->Pte[0] = Pte; -} - -VOID -ArmSetupPagingAndJump(IN ULONG Magic) -{ - ARM_CONTROL_REGISTER ControlRegister; - - // - // Enable MMU, DCache and ICache - // - ControlRegister = KeArmControlRegisterGet(); - ControlRegister.MmuEnabled = TRUE; - ControlRegister.ICacheEnabled = TRUE; - ControlRegister.DCacheEnabled = TRUE; - KeArmControlRegisterSet(ControlRegister); - - // - // Jump to Kernel - // - (*KernelEntryPoint)(Magic, (PVOID)&ArmLoaderBlock); -} - -VOID -ArmPrepareForReactOS(IN BOOLEAN Setup) -{ - // - // Initialize the loader block - // - InitializeListHead(&ArmLoaderBlock.BootDriverListHead); - InitializeListHead(&ArmLoaderBlock.LoadOrderListHead); - InitializeListHead(&ArmLoaderBlock.MemoryDescriptorListHead); - - // - // Setup the extension and setup block - // - ArmLoaderBlock.Extension = &ArmExtension; - ArmLoaderBlock.SetupLdrBlock = NULL; - - // - // TODO: Setup memory descriptors - // - - // - // TODO: Setup registry data - // - - // - // TODO: Setup ARC Hardware tree data - // - - // - // TODO: Setup NLS data - // - - // - // TODO: Setup boot-driver data - // - - // - // TODO: Setup extension parameters - // - - // - // TODO: Setup ARM-specific block - // -} - -PCONFIGURATION_COMPONENT_DATA -ArmHwDetect(VOID) -{ - PCONFIGURATION_COMPONENT_DATA RootNode; - - // - // Create the root node - // - FldrCreateSystemKey(&RootNode); - - // - // Write null component information - // - FldrSetComponentInformation(RootNode, - 0x0, - 0x0, - 0xFFFFFFFF); - - // - // TODO: - // There's no such thing as "PnP" on embedded hardware. - // The boot loader will send us a device tree, similar to ACPI - // or OpenFirmware device trees, and we will convert it to ARC. - // - - // - // Return the root node - // - return RootNode; -} - -ULONG -ArmMemGetMemoryMap(OUT PBIOS_MEMORY_MAP BiosMemoryMap, - IN ULONG MaxMemoryMapSize) -{ - // - // Return whatever the board returned to us (CS0 Base + Size and FLASH0) - // - RtlCopyMemory(BiosMemoryMap, - ArmBoardBlock->MemoryMap, - ArmBoardBlock->MemoryMapEntryCount * sizeof(BIOS_MEMORY_MAP)); - return ArmBoardBlock->MemoryMapEntryCount; -} - -VOID -MachInit(IN PCCH CommandLine) -{ - // - // Setup board-specific ARM routines - // - switch (ArmBoardBlock->BoardType) - { - // - // Check for Feroceon-base boards - // - case MACH_TYPE_FEROCEON: - - // - // These boards use a UART16550. Set us up for 115200 bps - // - ArmFeroSerialInit(115200); - MachVtbl.ConsPutChar = ArmFeroPutChar; - MachVtbl.ConsKbHit = ArmFeroKbHit; - MachVtbl.ConsGetCh = ArmFeroGetCh; - break; - - // - // Check for ARM Versatile PB boards - // - case MACH_TYPE_VERSATILE_PB: - - // - // These boards use a PrimeCell UART (PL011) - // - ArmVersaSerialInit(115200); - MachVtbl.ConsPutChar = ArmVersaPutChar; - MachVtbl.ConsKbHit = ArmVersaKbHit; - MachVtbl.ConsGetCh = ArmVersaGetCh; - break; - - default: - ASSERT(FALSE); - } - - // - // Setup generic ARM routines for all boards - // - MachVtbl.PrepareForReactOS = ArmPrepareForReactOS; - MachVtbl.GetMemoryMap = ArmMemGetMemoryMap; - MachVtbl.HwDetect = ArmHwDetect; - - // - // Setup disk I/O routines, switch to ramdisk ones for non-NAND boot - // - MachVtbl.DiskReadLogicalSectors = ArmDiskReadLogicalSectors; - MachVtbl.DiskGetDriveGeometry = ArmDiskGetDriveGeometry; - MachVtbl.DiskGetCacheableBlockCount = ArmDiskGetCacheableBlockCount; - RamDiskSwitchFromBios(); - - // - // Now set default disk handling routines -- we don't need to override - // - MachVtbl.DiskGetBootVolume = DiskGetBootVolume; - MachVtbl.DiskGetSystemVolume = DiskGetSystemVolume; - MachVtbl.DiskGetBootPath = DiskGetBootPath; - MachVtbl.DiskGetBootDevice = DiskGetBootDevice; - MachVtbl.DiskBootingFromFloppy = DiskBootingFromFloppy; - MachVtbl.DiskNormalizeSystemPath = DiskNormalizeSystemPath; - MachVtbl.DiskGetPartitionEntry = DiskGetPartitionEntry; - - // - // We can now print to the console - // - TuiPrintf("%s for ARM\n", GetFreeLoaderVersionString()); - TuiPrintf("Bootargs: %s\n", CommandLine); -} - -VOID -FrLdrStartup(IN ULONG Magic) -{ - // - // Disable interrupts (aleady done) - // - - // - // Set proper CPSR (already done) - // - - // - // Initialize the page directory - // - ArmSetupPageDirectory(); - - // - // Initialize paging and load NTOSKRNL - // - ArmSetupPagingAndJump(Magic); -} Modified: trunk/reactos/boot/freeldr/freeldr/freeldr_arch.rbuild URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/freel… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/freeldr_arch.rbuild (original) +++ trunk/reactos/boot/freeldr/freeldr/freeldr_arch.rbuild Tue Feb 12 07:22:39 2008 @@ -102,9 +102,9 @@ <define name="_NTHAL_" /> <file>boot.s</file> <file>ferouart.c</file> + <file>loader.c</file> + <file>macharm.c</file> <file>versuart.c</file> - <file>macharm.c</file> - <file>stubs.c</file> </module> </if> </directory>

16 years, 8 months

[ros-arm-bringup] 32310: We now have the ARM defines/structures in stubs.c in FreeLDR in more appropriate kernel headers. This is just cleanup work.

by ros-arm-bringup＠svn.reactos.org

Author: ros-arm-bringup Date: Tue Feb 12 07:15:53 2008 New Revision: 32310 URL: http://svn.reactos.org/svn/reactos?rev=32310&view=rev Log: We now have the ARM defines/structures in stubs.c in FreeLDR in more appropriate kernel headers. This is just cleanup work. Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c trunk/reactos/ntoskrnl/include/internal/arm/intrin_i.h trunk/reactos/ntoskrnl/include/internal/arm/ke.h trunk/reactos/ntoskrnl/include/internal/arm/mm.h trunk/reactos/ntoskrnl/include/internal/ntoskrnl.h Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/arch/… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c (original) +++ trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c Tue Feb 12 07:15:53 2008 @@ -9,183 +9,11 @@ /* INCLUDES *******************************************************************/ #include <freeldr.h> +#include <internal/arm/ke.h> +#include <internal/arm/mm.h> +#include <internal/arm/intrin_i.h> /* GLOBALS ********************************************************************/ - -typedef union _ARM_PTE -{ - union - { - struct - { - ULONG Type:2; - ULONG Unused:30; - } Fault; - struct - { - ULONG Type:2; - ULONG Reserved:3; - ULONG Domain:4; - ULONG Ignored:1; - ULONG BaseAddress:22; - } Coarse; - struct - { - ULONG Type:2; - ULONG Buffered:1; - ULONG Cached:1; - ULONG Reserved:1; - ULONG Domain:4; - ULONG Ignored:1; - ULONG Access:2; - ULONG Ignored1:8; - ULONG BaseAddress:12; - } Section; - struct - { - ULONG Type:2; - ULONG Reserved:3; - ULONG Domain:4; - ULONG Ignored:3; - ULONG BaseAddress:20; - } Fine; - } L1; - union - { - struct - { - ULONG Type:2; - ULONG Unused:30; - } Fault; - struct - { - ULONG Type:2; - ULONG Buffered:1; - ULONG Cached:1; - ULONG Access0:2; - ULONG Access1:2; - ULONG Access2:2; - ULONG Access3:2; - ULONG Ignored:4; - ULONG BaseAddress:16; - } Large; - struct - { - ULONG Type:2; - ULONG Buffered:1; - ULONG Cached:1; - ULONG Access0:2; - ULONG Access1:2; - ULONG Access2:2; - ULONG Access3:2; - ULONG BaseAddress:20; - } Small; - struct - { - ULONG Type:2; - ULONG Buffered:1; - ULONG Cached:1; - ULONG Access0:2; - ULONG Ignored:4; - ULONG BaseAddress:22; - } Tiny; - } L2; - ULONG AsUlong; -} ARM_PTE, *PARM_PTE; - -typedef struct _ARM_TRANSLATION_TABLE -{ - ARM_PTE Pte[4096]; -} ARM_TRANSLATION_TABLE, *PARM_TRANSLATION_TABLE; - -typedef union _ARM_TTB_REGISTER -{ - struct - { - ULONG Reserved:14; - ULONG BaseAddress:18; - }; - ULONG AsUlong; -} ARM_TTB_REGISTER; - -typedef enum _ARM_L1_PTE_TYPE -{ - FaultPte, - CoarsePte, - SectionPte, - FinePte -} ARM_L1_PTE_TYPE; - -typedef enum _ARM_PTE_ACCESS -{ - FaultAccess, - SupervisorAccess, - SharedAccess, - UserAccess -} ARM_PTE_ACCESS; - -typedef enum _ARM_DOMAIN -{ - FaultDomain, - ClientDomain, - InvalidDomain, - ManagerDomain -} ARM_DOMAIN; - -typedef union _ARM_DOMAIN_REGISTER -{ - struct - { - ULONG Domain0:2; - ULONG Domain1:2; - ULONG Domain2:2; - ULONG Domain3:2; - ULONG Domain4:2; - ULONG Domain5:2; - ULONG Domain6:2; - ULONG Domain7:2; - ULONG Domain8:2; - ULONG Domain9:2; - ULONG Domain10:2; - ULONG Domain11:2; - ULONG Domain12:2; - ULONG Domain13:2; - ULONG Domain14:2; - ULONG Domain15:2; - }; - ULONG AsUlong; -} ARM_DOMAIN_REGISTER; - -typedef union _ARM_CONTROL_REGISTER -{ - struct - { - ULONG MmuEnabled:1; - ULONG AlignmentFaultsEnabled:1; - ULONG DCacheEnabled:1; - ULONG Sbo:3; - ULONG BigEndianEnabled:1; - ULONG System:1; - ULONG Rom:1; - ULONG Sbz:2; - ULONG ICacheEnabled:1; - ULONG HighVectors:1; - ULONG RoundRobinReplacementEnabled:1; - ULONG Armv4Compat:1; - ULONG Sbo1:1; - ULONG Sbz1:1; - ULONG Sbo2:1; - ULONG Reserved:14; - }; - ULONG AsUlong; -} ARM_CONTROL_REGISTER, *PARM_CONTROL_REGISTER; - -typedef enum _ARM_DOMAINS -{ - Domain0 -} ARM_DOMAINS; - -#define TTB_SHIFT 20 ULONG PageDirectoryStart, PageDirectoryEnd; LOADER_PARAMETER_BLOCK ArmLoaderBlock; @@ -218,36 +46,6 @@ { ASSERT(gRamDiskBase == NULL); return FALSE; -} - -ARM_CONTROL_REGISTER -FORCEINLINE -ArmControlRegisterGet(VOID) -{ - ARM_CONTROL_REGISTER Value; - __asm__ __volatile__ ("mrc p15, 0, %0, c1, c0, 0" : "=r"(Value.AsUlong) : : "cc"); - return Value; -} - -VOID -FORCEINLINE -ArmControlRegisterSet(IN ARM_CONTROL_REGISTER ControlRegister) -{ - __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r"(ControlRegister.AsUlong) : "cc"); -} - -VOID -FORCEINLINE -ArmMmuTtbSet(IN ARM_TTB_REGISTER Ttb) -{ - __asm__ __volatile__ ("mcr p15, 0, %0, c2, c0, 0" : : "r"(Ttb.AsUlong) : "cc"); -} - -VOID -FORCEINLINE -ArmMmuDomainRegisterSet(IN ARM_DOMAIN_REGISTER DomainRegister) -{ - __asm__ __volatile__ ("mcr p15, 0, %0, c3, c0, 0" : : "r"(DomainRegister.AsUlong) : "cc"); } VOID @@ -272,14 +70,14 @@ // TtbRegister.AsUlong = (ULONG)TranslationTable; ASSERT(TtbRegister.Reserved == 0); - ArmMmuTtbSet(TtbRegister); + KeArmTranslationTableRegisterSet(TtbRegister); // // Use Domain 0, enforce AP bits (client) // DomainRegister.AsUlong = 0; DomainRegister.Domain0 = ClientDomain; - ArmMmuDomainRegisterSet(DomainRegister); + KeArmDomainRegisterSet(DomainRegister); // // Set Fault PTEs everywhere @@ -327,11 +125,11 @@ // // Enable MMU, DCache and ICache // - ControlRegister = ArmControlRegisterGet(); + ControlRegister = KeArmControlRegisterGet(); ControlRegister.MmuEnabled = TRUE; ControlRegister.ICacheEnabled = TRUE; ControlRegister.DCacheEnabled = TRUE; - ArmControlRegisterSet(ControlRegister); + KeArmControlRegisterSet(ControlRegister); // // Jump to Kernel Modified: trunk/reactos/ntoskrnl/include/internal/arm/intrin_i.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/include/internal/… ============================================================================== --- trunk/reactos/ntoskrnl/include/internal/arm/intrin_i.h (original) +++ trunk/reactos/ntoskrnl/include/internal/arm/intrin_i.h Tue Feb 12 07:15:53 2008 @@ -1,18 +1,45 @@ #ifndef _INTRIN_INTERNAL_ #define _INTRIN_INTERNAL_ -static __inline__ __attribute__((always_inline)) void KeArchHaltProcessor(void) +FORCEINLINE +VOID +KeArmHaltProcessor(void) { // // Enter Wait-For-Interrupt Mode // - __asm__ __volatile__ - ( - "mov r1, #0;" - "mcr p15, 0, r1, c7, c0, 4;" - ); + __asm__ __volatile__ ("mcr p15, 0, %0, c7, c0, 4" : : "r"(0) : "cc"); } +FORCEINLINE +ARM_CONTROL_REGISTER +KeArmControlRegisterGet(VOID) +{ + ARM_CONTROL_REGISTER Value; + __asm__ __volatile__ ("mrc p15, 0, %0, c1, c0, 0" : "=r"(Value.AsUlong) : : "cc"); + return Value; +} + +FORCEINLINE +VOID +KeArmControlRegisterSet(IN ARM_CONTROL_REGISTER ControlRegister) +{ + __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r"(ControlRegister.AsUlong) : "cc"); +} + +FORCEINLINE +VOID +KeArmTranslationTableRegisterSet(IN ARM_TTB_REGISTER Ttb) +{ + __asm__ __volatile__ ("mcr p15, 0, %0, c2, c0, 0" : : "r"(Ttb.AsUlong) : "cc"); +} + +FORCEINLINE +VOID +KeArmDomainRegisterSet(IN ARM_DOMAIN_REGISTER DomainRegister) +{ + __asm__ __volatile__ ("mcr p15, 0, %0, c3, c0, 0" : : "r"(DomainRegister.AsUlong) : "cc"); +} + +#define KeArchHaltProcessor KeArmHaltProcessor #endif - -/* EOF */ Modified: trunk/reactos/ntoskrnl/include/internal/arm/ke.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/include/internal/… ============================================================================== --- trunk/reactos/ntoskrnl/include/internal/arm/ke.h (original) +++ trunk/reactos/ntoskrnl/include/internal/arm/ke.h Tue Feb 12 07:15:53 2008 @@ -4,6 +4,84 @@ #if __GNUC__ >=3 #pragma GCC system_header #endif + +typedef union _ARM_TTB_REGISTER +{ + struct + { + ULONG Reserved:14; + ULONG BaseAddress:18; + }; + ULONG AsUlong; +} ARM_TTB_REGISTER; + +typedef union _ARM_DOMAIN_REGISTER +{ + struct + { + ULONG Domain0:2; + ULONG Domain1:2; + ULONG Domain2:2; + ULONG Domain3:2; + ULONG Domain4:2; + ULONG Domain5:2; + ULONG Domain6:2; + ULONG Domain7:2; + ULONG Domain8:2; + ULONG Domain9:2; + ULONG Domain10:2; + ULONG Domain11:2; + ULONG Domain12:2; + ULONG Domain13:2; + ULONG Domain14:2; + ULONG Domain15:2; + }; + ULONG AsUlong; +} ARM_DOMAIN_REGISTER; + +typedef union _ARM_CONTROL_REGISTER +{ + struct + { + ULONG MmuEnabled:1; + ULONG AlignmentFaultsEnabled:1; + ULONG DCacheEnabled:1; + ULONG Sbo:3; + ULONG BigEndianEnabled:1; + ULONG System:1; + ULONG Rom:1; + ULONG Sbz:2; + ULONG ICacheEnabled:1; + ULONG HighVectors:1; + ULONG RoundRobinReplacementEnabled:1; + ULONG Armv4Compat:1; + ULONG Sbo1:1; + ULONG Sbz1:1; + ULONG Sbo2:1; + ULONG Reserved:14; + }; + ULONG AsUlong; +} ARM_CONTROL_REGISTER, *PARM_CONTROL_REGISTER; + +typedef enum _ARM_DOMAINS +{ + Domain0, + Domain1, + Domain2, + Domain3, + Domain4, + Domain5, + Domain6, + Domain7, + Domain8, + Domain9, + Domain10, + Domain11, + Domain12, + Domain13, + Domain14, + Domain15 +} ARM_DOMAINS; VOID NTAPI @@ -17,4 +95,4 @@ #define KeArchInitThreadWithContext KeArmInitThreadWithContext -#endif +#endif Modified: trunk/reactos/ntoskrnl/include/internal/arm/mm.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/include/internal/… ============================================================================== --- trunk/reactos/ntoskrnl/include/internal/arm/mm.h (original) +++ trunk/reactos/ntoskrnl/include/internal/arm/mm.h Tue Feb 12 07:15:53 2008 @@ -1,1 +1,120 @@ +#ifndef __NTOSKRNL_INCLUDE_INTERNAL_ARM_MM_H +#define __NTOSKRNL_INCLUDE_INTERNAL_ARM_MM_H +#if __GNUC__ >=3 +#pragma GCC system_header +#endif + +#define TTB_SHIFT 20 + +typedef union _ARM_PTE +{ + union + { + struct + { + ULONG Type:2; + ULONG Unused:30; + } Fault; + struct + { + ULONG Type:2; + ULONG Reserved:3; + ULONG Domain:4; + ULONG Ignored:1; + ULONG BaseAddress:22; + } Coarse; + struct + { + ULONG Type:2; + ULONG Buffered:1; + ULONG Cached:1; + ULONG Reserved:1; + ULONG Domain:4; + ULONG Ignored:1; + ULONG Access:2; + ULONG Ignored1:8; + ULONG BaseAddress:12; + } Section; + struct + { + ULONG Type:2; + ULONG Reserved:3; + ULONG Domain:4; + ULONG Ignored:3; + ULONG BaseAddress:20; + } Fine; + } L1; + union + { + struct + { + ULONG Type:2; + ULONG Unused:30; + } Fault; + struct + { + ULONG Type:2; + ULONG Buffered:1; + ULONG Cached:1; + ULONG Access0:2; + ULONG Access1:2; + ULONG Access2:2; + ULONG Access3:2; + ULONG Ignored:4; + ULONG BaseAddress:16; + } Large; + struct + { + ULONG Type:2; + ULONG Buffered:1; + ULONG Cached:1; + ULONG Access0:2; + ULONG Access1:2; + ULONG Access2:2; + ULONG Access3:2; + ULONG BaseAddress:20; + } Small; + struct + { + ULONG Type:2; + ULONG Buffered:1; + ULONG Cached:1; + ULONG Access0:2; + ULONG Ignored:4; + ULONG BaseAddress:22; + } Tiny; + } L2; + ULONG AsUlong; +} ARM_PTE, *PARM_PTE; + +typedef struct _ARM_TRANSLATION_TABLE +{ + ARM_PTE Pte[4096]; +} ARM_TRANSLATION_TABLE, *PARM_TRANSLATION_TABLE; + +typedef enum _ARM_L1_PTE_TYPE +{ + FaultPte, + CoarsePte, + SectionPte, + FinePte +} ARM_L1_PTE_TYPE; + +typedef enum _ARM_PTE_ACCESS +{ + FaultAccess, + SupervisorAccess, + SharedAccess, + UserAccess +} ARM_PTE_ACCESS; + +typedef enum _ARM_DOMAIN +{ + FaultDomain, + ClientDomain, + InvalidDomain, + ManagerDomain +} ARM_DOMAIN; + +#endif Modified: trunk/reactos/ntoskrnl/include/internal/ntoskrnl.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/include/internal/… ============================================================================== --- trunk/reactos/ntoskrnl/include/internal/ntoskrnl.h (original) +++ trunk/reactos/ntoskrnl/include/internal/ntoskrnl.h Tue Feb 12 07:15:53 2008 @@ -22,7 +22,6 @@ #undef PsGetCurrentProcess #define PsGetCurrentProcess _PsGetCurrentProcess -#include "arch/intrin_i.h" #include "ke.h" #include "i386/mm.h" #include "i386/fpu.h" @@ -54,6 +53,7 @@ #include "inbv.h" #include "vdm.h" #include "hal.h" +#include "arch/intrin_i.h" // // We are very lazy on ARM -- we just import intrinsics

16 years, 8 months

[ros-arm-bringup] 32309: Fix the build. Your friendly ARM ninjas apologize.

by ros-arm-bringup＠svn.reactos.org

Author: ros-arm-bringup Date: Tue Feb 12 06:06:06 2008 New Revision: 32309 URL: http://svn.reactos.org/svn/reactos?rev=32309&view=rev Log: Fix the build. Your friendly ARM ninjas apologize. Modified: trunk/reactos/include/ddk/ntstrsafe.h trunk/reactos/ntoskrnl/mm/sysldr.c Modified: trunk/reactos/include/ddk/ntstrsafe.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/ddk/ntstrsafe.h?re… ============================================================================== --- trunk/reactos/include/ddk/ntstrsafe.h (original) +++ trunk/reactos/include/ddk/ntstrsafe.h Tue Feb 12 06:06:06 2008 @@ -203,7 +203,6 @@ /* PUBLIC FUNCTIONS **********************************************************/ -FORCEINLINE NTSTATUS NTAPI RtlStringCbPrintfA(OUT PCHAR Destination, @@ -233,7 +232,6 @@ return Status; } -FORCEINLINE NTSTATUS NTAPI RtlStringCbPrintfExA(OUT PCHAR Destination, Modified: trunk/reactos/ntoskrnl/mm/sysldr.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/mm/sysldr.c?rev=3… ============================================================================== --- trunk/reactos/ntoskrnl/mm/sysldr.c (original) +++ trunk/reactos/ntoskrnl/mm/sysldr.c Tue Feb 12 06:06:06 2008 @@ -13,7 +13,6 @@ #include <debug.h> /* GCC's incompetence strikes again */ -FORCEINLINE VOID sprintf_nt(IN PCHAR Buffer, IN PCHAR Format,

16 years, 8 months

[ros-arm-bringup] 32308: Fix a couple of MMU bugs (incrementing the base address before writing the PTE and using the wrong start base address). Virtual memory now works! FreeLDR now boots into the kernel, at 0x80801000, in KiSystemStartup!

by ros-arm-bringup＠svn.reactos.org

Author: ros-arm-bringup Date: Tue Feb 12 02:47:43 2008 New Revision: 32308 URL: http://svn.reactos.org/svn/reactos?rev=32308&view=rev Log: Fix a couple of MMU bugs (incrementing the base address before writing the PTE and using the wrong start base address). Virtual memory now works! FreeLDR now boots into the kernel, at 0x80801000, in KiSystemStartup! Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/arch/… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c (original) +++ trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c Tue Feb 12 02:47:43 2008 @@ -191,6 +191,7 @@ LOADER_PARAMETER_BLOCK ArmLoaderBlock; LOADER_PARAMETER_EXTENSION ArmExtension; extern ARM_TRANSLATION_TABLE ArmTranslationTable; +extern ROS_KERNEL_ENTRY_POINT KernelEntryPoint; /* FUNCTIONS ******************************************************************/ @@ -232,7 +233,7 @@ FORCEINLINE ArmControlRegisterSet(IN ARM_CONTROL_REGISTER ControlRegister) { - __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0; b ." : : "r"(ControlRegister.AsUlong) : "cc"); + __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r"(ControlRegister.AsUlong) : "cc"); } VOID @@ -271,7 +272,6 @@ // TtbRegister.AsUlong = (ULONG)TranslationTable; ASSERT(TtbRegister.Reserved == 0); - TuiPrintf("CP15 C2: %x\n", TtbRegister); ArmMmuTtbSet(TtbRegister); // @@ -279,7 +279,6 @@ // DomainRegister.AsUlong = 0; DomainRegister.Domain0 = ClientDomain; - TuiPrintf("CP15 C3: %x\n", DomainRegister); ArmMmuDomainRegisterSet(DomainRegister); // @@ -296,29 +295,26 @@ Pte.L1.Section.Reserved = 1; // ARM926EJ-S manual recommends setting to 1 Pte.L1.Section.Domain = Domain0; Pte.L1.Section.Access = SupervisorAccess; - Pte.L1.Section.BaseAddress = KSEG0_BASE >> TTB_SHIFT; + Pte.L1.Section.BaseAddress = 0; Pte.L1.Section.Ignored = Pte.L1.Section.Ignored1 = 0; - TuiPrintf("Template PTE: %x\n", Pte.AsUlong); - TuiPrintf("Base: %x %x\n", KSEG0_BASE, Pte.L1.Section.BaseAddress); - - // - // Map KSEG0 (0x80000000 - 0xA0000000) - // - TuiPrintf("First PTE Index: %x\n", KSEG0_BASE >> TTB_SHIFT); - TuiPrintf("Last PTE Index: %x\n", ((KSEG0_BASE + 0x20000000) >> TTB_SHIFT)); + + // + // Map KSEG0 (0x80000000 - 0xA0000000) to 0x00000000 - 0x80000000 + // In this way, the KERNEL_PHYS_ADDR (0x800000) becomes 0x80800000 + // which is the entrypoint, just like on x86. + // for (i = (KSEG0_BASE >> TTB_SHIFT); i < ((KSEG0_BASE + 0x20000000) >> TTB_SHIFT); i++) { // - // Update the PTE base address (next MB) + // Write PTE and update the base address (next MB) for the next one // + TranslationTable->Pte[i] = Pte; Pte.L1.Section.BaseAddress++; - TranslationTable->Pte[i] = Pte; } // - // Identity map the first MB of memory - // - TuiPrintf("Last KSEG0 PTE: %x %x\n", i, Pte.AsUlong); + // Identity map the first MB of memory as well + // Pte.L1.Section.BaseAddress = 0; TranslationTable->Pte[0] = Pte; } @@ -329,28 +325,18 @@ ARM_CONTROL_REGISTER ControlRegister; // - // This is it! Once we enable the MMU we're in a totally different universe. - // Cross our fingers: We mapped the bottom 1MB of memory, so FreeLDR and - // boot-data is still there. We also mapped the kernel, and made our - // allocations | KSEG0_BASE. If any of this isn't true, we're dead. - // - TuiPrintf("Crossing the Rubicon!\n"); - - // // Enable MMU, DCache and ICache // ControlRegister = ArmControlRegisterGet(); - TuiPrintf("CP15 C1: %x\n", ControlRegister); ControlRegister.MmuEnabled = TRUE; ControlRegister.ICacheEnabled = TRUE; ControlRegister.DCacheEnabled = TRUE; - TuiPrintf("CP15 C1: %x\n", ControlRegister); ArmControlRegisterSet(ControlRegister); // - // Are we still alive? - // - while (TRUE); + // Jump to Kernel + // + (*KernelEntryPoint)(Magic, (PVOID)&ArmLoaderBlock); } VOID

16 years, 8 months

[ros-arm-bringup] 32307: We define a region in FreeLDR where we store the initial TTB. We have to align it at a 16KB boundary, and ld loves to crash with such big alignment, so wee manually define it to load at 0x50000. Pray FreeLDR never gets that big (you'd think LD would warn if that section is overwriting others). Wrote a guideline for what ArmPrepareForReactOS should do and defined the initial ARM loader block and extension. Wrote the initial MMU code. It's totally busted but after 3 hours

by ros-arm-bringup＠svn.reactos.org

Author: ros-arm-bringup Date: Tue Feb 12 01:17:15 2008 New Revision: 32307 URL: http://svn.reactos.org/svn/reactos?rev=32307&view=rev Log: We define a region in FreeLDR where we store the initial TTB. We have to align it at a 16KB boundary, and ld loves to crash with such big alignment, so wee manually define it to load at 0x50000. Pray FreeLDR never gets that big (you'd think LD would warn if that section is overwriting others). Wrote a guideline for what ArmPrepareForReactOS should do and defined the initial ARM loader block and extension. Wrote the initial MMU code. It's totally busted but after 3 hours of debugging, it doesn't abort anymore! Cleanups TBD. Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/boot.s trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c trunk/reactos/boot/freeldr/freeldr/freeldr.rbuild Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/boot.s URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/arch/… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/arch/arm/boot.s (original) +++ trunk/reactos/boot/freeldr/freeldr/arch/arm/boot.s Tue Feb 12 01:17:15 2008 @@ -23,6 +23,7 @@ /* GLOBALS ********************************************************************/ .global _start +.global ArmTranslationTable .section startup /* BOOT CODE ******************************************************************/ @@ -42,11 +43,12 @@ msr cpsr, r1 // - // Turn off caches + // Turn off caches and the MMU // mrc p15, 0, r1, c1, c0, 0 bic r1, r1, #C1_DCACHE_CONTROL bic r1, r1, #C1_ICACHE_CONTROL + bic r1, r1, #C1_MMU_CONTROL mcr p15, 0, r1, c1, c0, 0 // @@ -65,6 +67,8 @@ // r0 contains the ARM_BOARD_CONFIGURATION_DATA structure // bx lr + +/* BOOT STACK *****************************************************************/ L_BootStackEnd: .long BootStackEnd @@ -77,3 +81,9 @@ .space 0x4000 BootStackEnd: .long 0 + +/* INITIAL PAGE TABLE *********************************************************/ + +.section pagedata +ArmTranslationTable: + .space 0x4000 Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/arch/… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c (original) +++ trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c Tue Feb 12 01:17:15 2008 @@ -12,7 +12,185 @@ /* GLOBALS ********************************************************************/ +typedef union _ARM_PTE +{ + union + { + struct + { + ULONG Type:2; + ULONG Unused:30; + } Fault; + struct + { + ULONG Type:2; + ULONG Reserved:3; + ULONG Domain:4; + ULONG Ignored:1; + ULONG BaseAddress:22; + } Coarse; + struct + { + ULONG Type:2; + ULONG Buffered:1; + ULONG Cached:1; + ULONG Reserved:1; + ULONG Domain:4; + ULONG Ignored:1; + ULONG Access:2; + ULONG Ignored1:8; + ULONG BaseAddress:12; + } Section; + struct + { + ULONG Type:2; + ULONG Reserved:3; + ULONG Domain:4; + ULONG Ignored:3; + ULONG BaseAddress:20; + } Fine; + } L1; + union + { + struct + { + ULONG Type:2; + ULONG Unused:30; + } Fault; + struct + { + ULONG Type:2; + ULONG Buffered:1; + ULONG Cached:1; + ULONG Access0:2; + ULONG Access1:2; + ULONG Access2:2; + ULONG Access3:2; + ULONG Ignored:4; + ULONG BaseAddress:16; + } Large; + struct + { + ULONG Type:2; + ULONG Buffered:1; + ULONG Cached:1; + ULONG Access0:2; + ULONG Access1:2; + ULONG Access2:2; + ULONG Access3:2; + ULONG BaseAddress:20; + } Small; + struct + { + ULONG Type:2; + ULONG Buffered:1; + ULONG Cached:1; + ULONG Access0:2; + ULONG Ignored:4; + ULONG BaseAddress:22; + } Tiny; + } L2; + ULONG AsUlong; +} ARM_PTE, *PARM_PTE; + +typedef struct _ARM_TRANSLATION_TABLE +{ + ARM_PTE Pte[4096]; +} ARM_TRANSLATION_TABLE, *PARM_TRANSLATION_TABLE; + +typedef union _ARM_TTB_REGISTER +{ + struct + { + ULONG Reserved:14; + ULONG BaseAddress:18; + }; + ULONG AsUlong; +} ARM_TTB_REGISTER; + +typedef enum _ARM_L1_PTE_TYPE +{ + FaultPte, + CoarsePte, + SectionPte, + FinePte +} ARM_L1_PTE_TYPE; + +typedef enum _ARM_PTE_ACCESS +{ + FaultAccess, + SupervisorAccess, + SharedAccess, + UserAccess +} ARM_PTE_ACCESS; + +typedef enum _ARM_DOMAIN +{ + FaultDomain, + ClientDomain, + InvalidDomain, + ManagerDomain +} ARM_DOMAIN; + +typedef union _ARM_DOMAIN_REGISTER +{ + struct + { + ULONG Domain0:2; + ULONG Domain1:2; + ULONG Domain2:2; + ULONG Domain3:2; + ULONG Domain4:2; + ULONG Domain5:2; + ULONG Domain6:2; + ULONG Domain7:2; + ULONG Domain8:2; + ULONG Domain9:2; + ULONG Domain10:2; + ULONG Domain11:2; + ULONG Domain12:2; + ULONG Domain13:2; + ULONG Domain14:2; + ULONG Domain15:2; + }; + ULONG AsUlong; +} ARM_DOMAIN_REGISTER; + +typedef union _ARM_CONTROL_REGISTER +{ + struct + { + ULONG MmuEnabled:1; + ULONG AlignmentFaultsEnabled:1; + ULONG DCacheEnabled:1; + ULONG Sbo:3; + ULONG BigEndianEnabled:1; + ULONG System:1; + ULONG Rom:1; + ULONG Sbz:2; + ULONG ICacheEnabled:1; + ULONG HighVectors:1; + ULONG RoundRobinReplacementEnabled:1; + ULONG Armv4Compat:1; + ULONG Sbo1:1; + ULONG Sbz1:1; + ULONG Sbo2:1; + ULONG Reserved:14; + }; + ULONG AsUlong; +} ARM_CONTROL_REGISTER, *PARM_CONTROL_REGISTER; + +typedef enum _ARM_DOMAINS +{ + Domain0 +} ARM_DOMAINS; + +#define TTB_SHIFT 20 + ULONG PageDirectoryStart, PageDirectoryEnd; +LOADER_PARAMETER_BLOCK ArmLoaderBlock; +LOADER_PARAMETER_EXTENSION ArmExtension; +extern ARM_TRANSLATION_TABLE ArmTranslationTable; /* FUNCTIONS ******************************************************************/ @@ -41,10 +219,183 @@ return FALSE; } +ARM_CONTROL_REGISTER +FORCEINLINE +ArmControlRegisterGet(VOID) +{ + ARM_CONTROL_REGISTER Value; + __asm__ __volatile__ ("mrc p15, 0, %0, c1, c0, 0" : "=r"(Value.AsUlong) : : "cc"); + return Value; +} + +VOID +FORCEINLINE +ArmControlRegisterSet(IN ARM_CONTROL_REGISTER ControlRegister) +{ + __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0; b ." : : "r"(ControlRegister.AsUlong) : "cc"); +} + +VOID +FORCEINLINE +ArmMmuTtbSet(IN ARM_TTB_REGISTER Ttb) +{ + __asm__ __volatile__ ("mcr p15, 0, %0, c2, c0, 0" : : "r"(Ttb.AsUlong) : "cc"); +} + +VOID +FORCEINLINE +ArmMmuDomainRegisterSet(IN ARM_DOMAIN_REGISTER DomainRegister) +{ + __asm__ __volatile__ ("mcr p15, 0, %0, c3, c0, 0" : : "r"(DomainRegister.AsUlong) : "cc"); +} + +VOID +ArmSetupPageDirectory(VOID) +{ + ARM_TTB_REGISTER TtbRegister; + ARM_DOMAIN_REGISTER DomainRegister; + ARM_PTE Pte; + ULONG i; + PARM_TRANSLATION_TABLE TranslationTable; + + // + // Allocate translation table buffer. + // During bootstrap, this will be a simple L1 (Master) Page Table with + // Section entries for KSEG0 and the first MB of RAM. + // + TranslationTable = &ArmTranslationTable; + if (!TranslationTable) return; + + // + // Set it as the TTB + // + TtbRegister.AsUlong = (ULONG)TranslationTable; + ASSERT(TtbRegister.Reserved == 0); + TuiPrintf("CP15 C2: %x\n", TtbRegister); + ArmMmuTtbSet(TtbRegister); + + // + // Use Domain 0, enforce AP bits (client) + // + DomainRegister.AsUlong = 0; + DomainRegister.Domain0 = ClientDomain; + TuiPrintf("CP15 C3: %x\n", DomainRegister); + ArmMmuDomainRegisterSet(DomainRegister); + + // + // Set Fault PTEs everywhere + // + RtlZeroMemory(TranslationTable, 4096 * sizeof(ARM_PTE)); + + // + // Build the template PTE + // + Pte.L1.Section.Type = SectionPte; + Pte.L1.Section.Buffered = FALSE; + Pte.L1.Section.Cached = FALSE; + Pte.L1.Section.Reserved = 1; // ARM926EJ-S manual recommends setting to 1 + Pte.L1.Section.Domain = Domain0; + Pte.L1.Section.Access = SupervisorAccess; + Pte.L1.Section.BaseAddress = KSEG0_BASE >> TTB_SHIFT; + Pte.L1.Section.Ignored = Pte.L1.Section.Ignored1 = 0; + TuiPrintf("Template PTE: %x\n", Pte.AsUlong); + TuiPrintf("Base: %x %x\n", KSEG0_BASE, Pte.L1.Section.BaseAddress); + + // + // Map KSEG0 (0x80000000 - 0xA0000000) + // + TuiPrintf("First PTE Index: %x\n", KSEG0_BASE >> TTB_SHIFT); + TuiPrintf("Last PTE Index: %x\n", ((KSEG0_BASE + 0x20000000) >> TTB_SHIFT)); + for (i = (KSEG0_BASE >> TTB_SHIFT); i < ((KSEG0_BASE + 0x20000000) >> TTB_SHIFT); i++) + { + // + // Update the PTE base address (next MB) + // + Pte.L1.Section.BaseAddress++; + TranslationTable->Pte[i] = Pte; + } + + // + // Identity map the first MB of memory + // + TuiPrintf("Last KSEG0 PTE: %x %x\n", i, Pte.AsUlong); + Pte.L1.Section.BaseAddress = 0; + TranslationTable->Pte[0] = Pte; +} + +VOID +ArmSetupPagingAndJump(IN ULONG Magic) +{ + ARM_CONTROL_REGISTER ControlRegister; + + // + // This is it! Once we enable the MMU we're in a totally different universe. + // Cross our fingers: We mapped the bottom 1MB of memory, so FreeLDR and + // boot-data is still there. We also mapped the kernel, and made our + // allocations | KSEG0_BASE. If any of this isn't true, we're dead. + // + TuiPrintf("Crossing the Rubicon!\n"); + + // + // Enable MMU, DCache and ICache + // + ControlRegister = ArmControlRegisterGet(); + TuiPrintf("CP15 C1: %x\n", ControlRegister); + ControlRegister.MmuEnabled = TRUE; + ControlRegister.ICacheEnabled = TRUE; + ControlRegister.DCacheEnabled = TRUE; + TuiPrintf("CP15 C1: %x\n", ControlRegister); + ArmControlRegisterSet(ControlRegister); + + // + // Are we still alive? + // + while (TRUE); +} + VOID ArmPrepareForReactOS(IN BOOLEAN Setup) -{ - while (TRUE); +{ + // + // Initialize the loader block + // + InitializeListHead(&ArmLoaderBlock.BootDriverListHead); + InitializeListHead(&ArmLoaderBlock.LoadOrderListHead); + InitializeListHead(&ArmLoaderBlock.MemoryDescriptorListHead); + + // + // Setup the extension and setup block + // + ArmLoaderBlock.Extension = &ArmExtension; + ArmLoaderBlock.SetupLdrBlock = NULL; + + // + // TODO: Setup memory descriptors + // + + // + // TODO: Setup registry data + // + + // + // TODO: Setup ARC Hardware tree data + // + + // + // TODO: Setup NLS data + // + + // + // TODO: Setup boot-driver data + // + + // + // TODO: Setup extension parameters + // + + // + // TODO: Setup ARM-specific block + // } PCONFIGURATION_COMPONENT_DATA @@ -167,5 +518,21 @@ VOID FrLdrStartup(IN ULONG Magic) { - while (TRUE); -} + // + // Disable interrupts (aleady done) + // + + // + // Set proper CPSR (already done) + // + + // + // Initialize the page directory + // + ArmSetupPageDirectory(); + + // + // Initialize paging and load NTOSKRNL + // + ArmSetupPagingAndJump(Magic); +} Modified: trunk/reactos/boot/freeldr/freeldr/freeldr.rbuild URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/freel… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/freeldr.rbuild (original) +++ trunk/reactos/boot/freeldr/freeldr/freeldr.rbuild Tue Feb 12 01:17:15 2008 @@ -31,6 +31,7 @@ <library>libcntpr</library> <linkerflag>-lgcc</linkerflag> <linkerflag>-static</linkerflag> + <linkerflag>-Wl,--section-start,pagedata=0x50000</linkerflag> </module> </if> <if property="ARCH" value="powerpc">

16 years, 8 months

[ros-arm-bringup] 32306: FORCEINLINE is a lot more...forcefull... now ; -). Previous version didn't always inline as requested.

by ros-arm-bringup＠svn.reactos.org

Author: ros-arm-bringup Date: Tue Feb 12 01:13:35 2008 New Revision: 32306 URL: http://svn.reactos.org/svn/reactos?rev=32306&view=rev Log: FORCEINLINE is a lot more...forcefull... now ;-). Previous version didn't always inline as requested. Modified: trunk/reactos/include/psdk/winnt.h Modified: trunk/reactos/include/psdk/winnt.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/psdk/winnt.h?rev=3… ============================================================================== --- trunk/reactos/include/psdk/winnt.h (original) +++ trunk/reactos/include/psdk/winnt.h Tue Feb 12 01:13:35 2008 @@ -84,7 +84,7 @@ #elif (_MSC_VER) #define FORCEINLINE __inline #else -#define FORCEINLINE static __inline +#define FORCEINLINE static __inline__ __attribute__((always_inline)) #endif #endif

16 years, 8 months

[ros-arm-bringup] 32305: We now support the ARM Versatile/PB platform, which means qemu-system-arm -M versatilepb is now able to emulate the ARM build of ReactOS. We now support the PL011 UART, required for console output on the Versatile. We now define the ARM_LOADER_BLOCK structure, to be used later when FreeLDR passes control to the kernel.

by ros-arm-bringup＠svn.reactos.org

Author: ros-arm-bringup Date: Mon Feb 11 23:15:16 2008 New Revision: 32305 URL: http://svn.reactos.org/svn/reactos?rev=32305&view=rev Log: We now support the ARM Versatile/PB platform, which means qemu-system-arm -M versatilepb is now able to emulate the ARM build of ReactOS. We now support the PL011 UART, required for console output on the Versatile. We now define the ARM_LOADER_BLOCK structure, to be used later when FreeLDR passes control to the kernel. Added: trunk/reactos/boot/freeldr/freeldr/arch/arm/versuart.c (with props) Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/macharm.c trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c trunk/reactos/boot/freeldr/freeldr/freeldr_arch.rbuild trunk/reactos/boot/freeldr/freeldr/include/arch/arm/hardware.h trunk/reactos/include/reactos/arc/arc.h Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/macharm.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/arch/… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/arch/arm/macharm.c (original) +++ trunk/reactos/boot/freeldr/freeldr/arch/arm/macharm.c Mon Feb 11 23:15:16 2008 @@ -34,7 +34,8 @@ // // This should probably go away once we support more boards // - ASSERT(ArmBoardBlock->BoardType == ARM_FEROCEON); + ASSERT((ArmBoardBlock->BoardType == MACH_TYPE_FEROCEON) || + (ArmBoardBlock->BoardType == MACH_TYPE_VERSATILE_PB)); // // Call FreeLDR's portable entrypoint with our command-line Modified: trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/arch/… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c (original) +++ trunk/reactos/boot/freeldr/freeldr/arch/arm/stubs.c Mon Feb 11 23:15:16 2008 @@ -15,14 +15,6 @@ ULONG PageDirectoryStart, PageDirectoryEnd; /* FUNCTIONS ******************************************************************/ - -VOID -FrLdrStartup(IN ULONG Magic) -{ - // - // Start the OS - // -} BOOLEAN ArmDiskGetDriveGeometry(IN ULONG DriveNumber, @@ -110,7 +102,7 @@ // // Check for Feroceon-base boards // - case ARM_FEROCEON: + case MACH_TYPE_FEROCEON: // // These boards use a UART16550. Set us up for 115200 bps @@ -119,6 +111,20 @@ MachVtbl.ConsPutChar = ArmFeroPutChar; MachVtbl.ConsKbHit = ArmFeroKbHit; MachVtbl.ConsGetCh = ArmFeroGetCh; + break; + + // + // Check for ARM Versatile PB boards + // + case MACH_TYPE_VERSATILE_PB: + + // + // These boards use a PrimeCell UART (PL011) + // + ArmVersaSerialInit(115200); + MachVtbl.ConsPutChar = ArmVersaPutChar; + MachVtbl.ConsKbHit = ArmVersaKbHit; + MachVtbl.ConsGetCh = ArmVersaGetCh; break; default: @@ -157,3 +163,9 @@ TuiPrintf("%s for ARM\n", GetFreeLoaderVersionString()); TuiPrintf("Bootargs: %s\n", CommandLine); } + +VOID +FrLdrStartup(IN ULONG Magic) +{ + while (TRUE); +} Added: trunk/reactos/boot/freeldr/freeldr/arch/arm/versuart.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/arch/… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/arch/arm/versuart.c (added) +++ trunk/reactos/boot/freeldr/freeldr/arch/arm/versuart.c Mon Feb 11 23:15:16 2008 @@ -1,0 +1,132 @@ +/* + * PROJECT: ReactOS Boot Loader + * LICENSE: GPL - See COPYING in the top level directory + * FILE: boot/freeldr/arch/arm/versuart.c + * PURPOSE: Implements code for Versatile boards using the PL011 UART + * PROGRAMMERS: ReactOS Portable Systems Group + */ + +/* INCLUDES *******************************************************************/ + +#include <freeldr.h> + +/* GLOBALS ********************************************************************/ + +// +// UART Registers +// +#define UART_PL01x_DR (ArmBoardBlock->UartRegisterBase + 0x00) +#define UART_PL01x_RSR (ArmBoardBlock->UartRegisterBase + 0x04) +#define UART_PL01x_ECR (ArmBoardBlock->UartRegisterBase + 0x04) +#define UART_PL01x_FR (ArmBoardBlock->UartRegisterBase + 0x18) +#define UART_PL011_IBRD (ArmBoardBlock->UartRegisterBase + 0x24) +#define UART_PL011_FBRD (ArmBoardBlock->UartRegisterBase + 0x28) +#define UART_PL011_LCRH (ArmBoardBlock->UartRegisterBase + 0x2C) +#define UART_PL011_CR (ArmBoardBlock->UartRegisterBase + 0x30) +#define UART_PL011_IMSC (ArmBoardBlock->UartRegisterBase + 0x38) + +// +// LCR Values +// +#define UART_PL011_LCRH_WLEN_8 0x60 +#define UART_PL011_LCRH_FEN 0x10 + +// +// FCR Values +// +#define UART_PL011_CR_UARTEN 0x01 +#define UART_PL011_CR_TXE 0x100 +#define UART_PL011_CR_RXE 0x200 + +// +// LSR Values +// +#define UART_PL01x_FR_RXFE 0x10 +#define UART_PL01x_FR_TXFF 0x20 + +/* FUNCTIONS ******************************************************************/ + +VOID +ArmVersaSerialInit(IN ULONG Baudrate) +{ + ULONG Divider, Remainder, Fraction; + + // + // Calculate baudrate clock divider and remainder + // + Divider = ArmBoardBlock->ClockRate / (16 * Baudrate); + Remainder = ArmBoardBlock->ClockRate % (16 * Baudrate); + + // + // Calculate the fractional part + // + Fraction = (8 * Remainder / Baudrate) >> 1; + Fraction += (8 * Remainder / Baudrate) & 1; + + // + // Disable interrupts + // + WRITE_REGISTER_ULONG(UART_PL011_CR, 0); + + // + // Set the baud rate to 115200 bps + // + WRITE_REGISTER_ULONG(UART_PL011_IBRD, Divider); + WRITE_REGISTER_ULONG(UART_PL011_FBRD, Fraction); + + // + // Set 8 bits for data, 1 stop bit, no parity, FIFO enabled + // + WRITE_REGISTER_ULONG(UART_PL011_LCRH, + UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN); + + // + // Clear and enable FIFO + // + WRITE_REGISTER_ULONG(UART_PL011_CR, + UART_PL011_CR_UARTEN | + UART_PL011_CR_TXE | + UART_PL011_CR_RXE); +} + +VOID +ArmVersaPutChar(IN INT Char) +{ + // + // Properly support new-lines + // + if (Char == '\n') ArmVersaPutChar('\r'); + + // + // Wait for ready + // + while ((READ_REGISTER_ULONG(UART_PL01x_FR) & UART_PL01x_FR_TXFF) != 0); + + // + // Send the character + // + WRITE_REGISTER_ULONG(UART_PL01x_DR, Char); +} + +INT +ArmVersaGetCh(VOID) +{ + // + // Wait for ready + // + while ((READ_REGISTER_ULONG(UART_PL01x_FR) & UART_PL01x_FR_RXFE) != 0); + + // + // Read the character + // + return READ_REGISTER_ULONG(UART_PL01x_DR); +} + +BOOLEAN +ArmVersaKbHit(VOID) +{ + // + // Return if something is ready + // + return ((READ_REGISTER_ULONG(UART_PL01x_FR) & UART_PL01x_FR_RXFE) == 0); +} Propchange: trunk/reactos/boot/freeldr/freeldr/arch/arm/versuart.c ------------------------------------------------------------------------------ svn:eol-style = native Propchange: trunk/reactos/boot/freeldr/freeldr/arch/arm/versuart.c ------------------------------------------------------------------------------ svn:mime-type = text/plain Modified: trunk/reactos/boot/freeldr/freeldr/freeldr_arch.rbuild URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/freel… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/freeldr_arch.rbuild (original) +++ trunk/reactos/boot/freeldr/freeldr/freeldr_arch.rbuild Mon Feb 11 23:15:16 2008 @@ -102,6 +102,7 @@ <define name="_NTHAL_" /> <file>boot.s</file> <file>ferouart.c</file> + <file>versuart.c</file> <file>macharm.c</file> <file>stubs.c</file> </module> Modified: trunk/reactos/boot/freeldr/freeldr/include/arch/arm/hardware.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/inclu… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/include/arch/arm/hardware.h (original) +++ trunk/reactos/boot/freeldr/freeldr/include/arch/arm/hardware.h Mon Feb 11 23:15:16 2008 @@ -14,16 +14,16 @@ #endif // -// The only things we support +// Marvell Feroceon-based SoC: +// Buffalo Linkstation, KuroBox Pro, D-Link DS323 and others // -typedef enum _ARM_BOARD_TYPE -{ - // - // Marvell Feroceon-based SoC: - // Buffalo Linkstation, KuroBox Pro, D-Link DS323 and others - // - ARM_FEROCEON = 1, -} ARM_BOARD_TYPE; +#define MACH_TYPE_FEROCEON 526 + +// +// ARM Versatile PB: +// qemu-system-arm -M versatilepb, RealView Development Boards and others +// +#define MACH_TYPE_VERSATILE_PB 387 // // Compatible boot-loaders should return us this information @@ -34,7 +34,7 @@ { ULONG MajorVersion; ULONG MinorVersion; - ARM_BOARD_TYPE BoardType; + ULONG BoardType; ULONG ClockRate; ULONG TimerRegisterBase; ULONG UartRegisterBase; @@ -105,6 +105,18 @@ BOOLEAN ArmFeroKbHit(VOID); +VOID +ArmVersaSerialInit(IN ULONG Baudrate); + +VOID +ArmVersaPutChar(IN INT Char); + +INT +ArmVersaGetCh(VOID); + +BOOLEAN +ArmVersaKbHit(VOID); + extern PARM_BOARD_CONFIGURATION_BLOCK ArmBoardBlock; #endif Modified: trunk/reactos/include/reactos/arc/arc.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/reactos/arc/arc.h?… ============================================================================== --- trunk/reactos/include/reactos/arc/arc.h (original) +++ trunk/reactos/include/reactos/arc/arc.h Mon Feb 11 23:15:16 2008 @@ -351,6 +351,28 @@ ULONG MachineType; } PPC_LOADER_BLOCK, *PPPC_LOADER_BLOCK; +typedef struct _ARM_LOADER_BLOCK +{ +#ifdef _ARM_ + ULONG InterruptStack; + ULONG FirstLevelDcacheSize; + ULONG FirstLevelDcacheFillSize; + ULONG FirstLevelIcacheSize; + ULONG FirstLevelIcacheFillSize; + ULONG GpBase; + ULONG PanicStack; + ULONG PcrPage; + ULONG PdrPage; + ULONG SecondLevelDcacheSize; + ULONG SecondLevelDcacheFillSize; + ULONG SecondLevelIcacheSize; + ULONG SecondLevelIcacheFillSize; + ULONG PcrPage2; +#else + ULONG PlaceHolder; +#endif +} ARM_LOADER_BLOCK, *PARM_LOADER_BLOCK; + // // Firmware information block (NT6+) // @@ -426,7 +448,8 @@ I386_LOADER_BLOCK I386; ALPHA_LOADER_BLOCK Alpha; IA64_LOADER_BLOCK Ia64; - PPC_LOADER_BLOCK PowerPC; + PPC_LOADER_BLOCK PowerPC; + ARM_LOADER_BLOCK Arm; } u; FIRMWARE_INFORMATION_LOADER_BLOCK FirmwareInformation; } LOADER_PARAMETER_BLOCK, *PLOADER_PARAMETER_BLOCK;

16 years, 8 months

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