Author: sginsberg
Date: Thu Nov 12 22:46:52 2009
New Revision: 44121
URL: http://svn.reactos.org/svn/reactos?rev=44121&view=rev
Log:
- Documentative amendment to 44115: It incorrectly stated that the commit added "init(i)al support for PCI and ISA interrupts". What was added is (disabled) initial support for ISA, EISA and PCI configurations that require level-triggered interrupts (we only support edge-triggered interrupts right now) and PCI IRQ routing, along with proper handling of IRQ13.
Modified:
trunk/reactos/hal/halx86/generic/irq.S
Modified: trunk/reactos/hal/halx86/generic/irq.S
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/generic/irq.S?r…
==============================================================================
--- trunk/reactos/hal/halx86/generic/irq.S [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/generic/irq.S [iso-8859-1] Thu Nov 12 22:46:52 2009
@@ -20,7 +20,7 @@
/* Master PIC */
.short 0x20 /* Port */
- .byte 0x11 /* Edge,, cascade, CAI 8, ICW4 */
+ .byte 0x11 /* Edge, cascade, CAI 8, ICW4 */
.byte PRIMARY_VECTOR_BASE /* Base */
.byte 4 /* IRQ 4 connected to slave */
.byte 1 /* Non buffered, not nested, 8086 */
@@ -798,7 +798,7 @@
mov dword ptr PCR[KPCR_IRQL], DISPATCH_LEVEL
#if DBG
- /* Make sure we were not higher then dispatch */
+ /* Make sure we were not higher then synch */
cmp eax, DISPATCH_LEVEL
ja InvalidRaise
#endif