Ros-diffs June 2010

ros-diffs@reactos.org

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[jmorlan] 47562: [KERNEL32], [WIN32CSR] - Make Get/SetConsoleTitle more compatible with windows; in particular, transfer title via capture buffer to allow for longer titles. - Tighten up capture buffer validation in win32csr.

by jmorlan＠svn.reactos.org

Author: jmorlan Date: Fri Jun 4 08:36:12 2010 New Revision: 47562 URL: http://svn.reactos.org/svn/reactos?rev=47562&view=rev Log: [KERNEL32], [WIN32CSR] - Make Get/SetConsoleTitle more compatible with windows; in particular, transfer title via capture buffer to allow for longer titles. - Tighten up capture buffer validation in win32csr. Modified: trunk/reactos/dll/win32/kernel32/misc/console.c trunk/reactos/include/reactos/subsys/csrss/csrss.h trunk/reactos/subsystems/win32/csrss/win32csr/alias.c trunk/reactos/subsystems/win32/csrss/win32csr/coninput.c trunk/reactos/subsystems/win32/csrss/win32csr/conoutput.c trunk/reactos/subsystems/win32/csrss/win32csr/console.c trunk/reactos/subsystems/win32/csrss/win32csr/dllmain.c trunk/reactos/subsystems/win32/csrss/win32csr/win32csr.h Modified: trunk/reactos/dll/win32/kernel32/misc/console.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/dll/win32/kernel32/misc/co… ============================================================================== --- trunk/reactos/dll/win32/kernel32/misc/console.c [iso-8859-1] (original) +++ trunk/reactos/dll/win32/kernel32/misc/console.c [iso-8859-1] Fri Jun 4 08:36:12 2010 @@ -3418,6 +3418,64 @@ } +static DWORD +IntGetConsoleTitle(LPVOID lpConsoleTitle, DWORD nSize, BOOL bUnicode) +{ + CSR_API_MESSAGE Request; + PCSR_CAPTURE_BUFFER CaptureBuffer; + ULONG CsrRequest = MAKE_CSR_API(GET_TITLE, CSR_CONSOLE); + NTSTATUS Status; + + if (nSize == 0) + return 0; + + Request.Data.GetTitleRequest.Length = nSize * (bUnicode ? 1 : sizeof(WCHAR)); + CaptureBuffer = CsrAllocateCaptureBuffer(1, Request.Data.GetTitleRequest.Length); + if (CaptureBuffer == NULL) + { + SetLastError(ERROR_NOT_ENOUGH_MEMORY); + return 0; + } + + CsrAllocateMessagePointer(CaptureBuffer, + Request.Data.GetTitleRequest.Length, + (PVOID*)&Request.Data.GetTitleRequest.Title); + + Status = CsrClientCallServer(&Request, CaptureBuffer, CsrRequest, sizeof(CSR_API_MESSAGE)); + if (!NT_SUCCESS(Status) || !(NT_SUCCESS(Status = Request.Status))) + { + CsrFreeCaptureBuffer(CaptureBuffer); + SetLastErrorByStatus(Status); + return 0; + } + + if (bUnicode) + { + if (nSize >= sizeof(WCHAR)) + wcscpy((LPWSTR)lpConsoleTitle, Request.Data.GetTitleRequest.Title); + } + else + { + if (nSize < Request.Data.GetTitleRequest.Length / sizeof(WCHAR) || + !WideCharToMultiByte(CP_ACP, // ANSI code page + 0, // performance and mapping flags + Request.Data.GetTitleRequest.Title, // address of wide-character string + -1, // number of characters in string + (LPSTR)lpConsoleTitle, // address of buffer for new string + nSize, // size of buffer + NULL, // FAST + NULL)) + { + /* Yes, if the buffer isn't big enough, it returns 0... Bad API */ + *(LPSTR)lpConsoleTitle = '\0'; + Request.Data.GetTitleRequest.Length = 0; + } + } + CsrFreeCaptureBuffer(CaptureBuffer); + + return Request.Data.GetTitleRequest.Length / sizeof(WCHAR); +} + /*-------------------------------------------------------------- * GetConsoleTitleW * @@ -3428,48 +3486,8 @@ GetConsoleTitleW(LPWSTR lpConsoleTitle, DWORD nSize) { - PCSR_API_MESSAGE Request; - ULONG CsrRequest; - NTSTATUS Status; - - Request = RtlAllocateHeap(RtlGetProcessHeap(), - 0, - CSR_API_MESSAGE_HEADER_SIZE(CSRSS_GET_TITLE) + CSRSS_MAX_TITLE_LENGTH * sizeof(WCHAR)); - if (Request == NULL) - { - SetLastError(ERROR_NOT_ENOUGH_MEMORY); - return FALSE; - } - - CsrRequest = MAKE_CSR_API(GET_TITLE, CSR_CONSOLE); - - Status = CsrClientCallServer(Request, - NULL, - CsrRequest, - CSR_API_MESSAGE_HEADER_SIZE(CSRSS_GET_TITLE) + CSRSS_MAX_TITLE_LENGTH * sizeof(WCHAR)); - if (!NT_SUCCESS(Status) || !(NT_SUCCESS(Status = Request->Status))) - { - RtlFreeHeap(RtlGetProcessHeap(), 0, Request); - SetLastErrorByStatus(Status); - return 0; - } - - if (nSize * sizeof(WCHAR) <= Request->Data.GetTitleRequest.Length) - { - nSize--; - } - else - { - nSize = Request->Data.GetTitleRequest.Length / sizeof (WCHAR); - } - memcpy(lpConsoleTitle, Request->Data.GetTitleRequest.Title, nSize * sizeof(WCHAR)); - lpConsoleTitle[nSize] = L'\0'; - - RtlFreeHeap(RtlGetProcessHeap(), 0, Request); - - return nSize; -} - + return IntGetConsoleTitle(lpConsoleTitle, nSize, TRUE); +} /*-------------------------------------------------------------- * GetConsoleTitleA @@ -3483,28 +3501,7 @@ GetConsoleTitleA(LPSTR lpConsoleTitle, DWORD nSize) { - WCHAR WideTitle [CSRSS_MAX_TITLE_LENGTH + 1]; - DWORD nWideTitle = CSRSS_MAX_TITLE_LENGTH + 1; - DWORD nWritten; - - if (!lpConsoleTitle || !nSize) return 0; - nWideTitle = GetConsoleTitleW((LPWSTR) WideTitle, nWideTitle); - if (!nWideTitle) return 0; - - if ((nWritten = WideCharToMultiByte(CP_ACP, // ANSI code page - 0, // performance and mapping flags - (LPWSTR) WideTitle, // address of wide-character string - nWideTitle, // number of characters in string - lpConsoleTitle, // address of buffer for new string - nSize - 1, // size of buffer - NULL, // FAST - NULL))) // FAST - { - lpConsoleTitle[nWritten] = '\0'; - return nWritten; - } - - return 0; + return IntGetConsoleTitle(lpConsoleTitle, nSize, FALSE); } @@ -3517,40 +3514,32 @@ WINAPI SetConsoleTitleW(LPCWSTR lpConsoleTitle) { - PCSR_API_MESSAGE Request; - ULONG CsrRequest; - NTSTATUS Status; - unsigned int c; - - Request = RtlAllocateHeap(RtlGetProcessHeap(), 0, - max(sizeof(CSR_API_MESSAGE), - CSR_API_MESSAGE_HEADER_SIZE(CSRSS_SET_TITLE) + - min(wcslen(lpConsoleTitle), CSRSS_MAX_TITLE_LENGTH) * sizeof(WCHAR))); - if (Request == NULL) + CSR_API_MESSAGE Request; + PCSR_CAPTURE_BUFFER CaptureBuffer; + ULONG CsrRequest = MAKE_CSR_API(SET_TITLE, CSR_CONSOLE); + NTSTATUS Status; + + Request.Data.SetTitleRequest.Length = wcslen(lpConsoleTitle) * sizeof(WCHAR); + + CaptureBuffer = CsrAllocateCaptureBuffer(1, Request.Data.SetTitleRequest.Length); + if (CaptureBuffer == NULL) { SetLastError(ERROR_NOT_ENOUGH_MEMORY); return FALSE; } - CsrRequest = MAKE_CSR_API(SET_TITLE, CSR_CONSOLE); - - for (c = 0; lpConsoleTitle[c] && c < CSRSS_MAX_TITLE_LENGTH; c++) - Request->Data.SetTitleRequest.Title[c] = lpConsoleTitle[c]; - - Request->Data.SetTitleRequest.Length = c * sizeof(WCHAR); - Status = CsrClientCallServer(Request, - NULL, - CsrRequest, - max(sizeof(CSR_API_MESSAGE), - CSR_API_MESSAGE_HEADER_SIZE(CSRSS_SET_TITLE) + c * sizeof(WCHAR))); - if (!NT_SUCCESS(Status) || !NT_SUCCESS(Status = Request->Status)) - { - RtlFreeHeap(RtlGetProcessHeap(), 0, Request); + CsrCaptureMessageBuffer(CaptureBuffer, + (PVOID)lpConsoleTitle, + Request.Data.SetTitleRequest.Length, + (PVOID*)&Request.Data.SetTitleRequest.Title); + + Status = CsrClientCallServer(&Request, CaptureBuffer, CsrRequest, sizeof(CSR_API_MESSAGE)); + CsrFreeCaptureBuffer(CaptureBuffer); + if (!NT_SUCCESS(Status) || !NT_SUCCESS(Status = Request.Status)) + { SetLastErrorByStatus(Status); - return(FALSE); - } - - RtlFreeHeap(RtlGetProcessHeap(), 0, Request); + return FALSE; + } return TRUE; } @@ -3567,43 +3556,18 @@ WINAPI SetConsoleTitleA(LPCSTR lpConsoleTitle) { - PCSR_API_MESSAGE Request; - ULONG CsrRequest; - NTSTATUS Status; - unsigned int c; - - Request = RtlAllocateHeap(RtlGetProcessHeap(), - 0, - max(sizeof(CSR_API_MESSAGE), - CSR_API_MESSAGE_HEADER_SIZE(CSRSS_SET_TITLE) + - min(strlen(lpConsoleTitle), CSRSS_MAX_TITLE_LENGTH) * sizeof(WCHAR))); - if (Request == NULL) + ULONG Length = strlen(lpConsoleTitle) + 1; + LPWSTR WideTitle = HeapAlloc(GetProcessHeap(), 0, Length * sizeof(WCHAR)); + BOOL Ret; + if (!WideTitle) { SetLastError(ERROR_NOT_ENOUGH_MEMORY); return FALSE; } - - CsrRequest = MAKE_CSR_API(SET_TITLE, CSR_CONSOLE); - - for (c = 0; lpConsoleTitle[c] && c < CSRSS_MAX_TITLE_LENGTH; c++) - Request->Data.SetTitleRequest.Title[c] = lpConsoleTitle[c]; - - Request->Data.SetTitleRequest.Length = c * sizeof(WCHAR); - Status = CsrClientCallServer(Request, - NULL, - CsrRequest, - max(sizeof(CSR_API_MESSAGE), - CSR_API_MESSAGE_HEADER_SIZE(CSRSS_SET_TITLE) + c * sizeof(WCHAR))); - if (!NT_SUCCESS(Status) || !NT_SUCCESS(Status = Request->Status)) - { - RtlFreeHeap(RtlGetProcessHeap(), 0, Request); - SetLastErrorByStatus(Status); - return(FALSE); - } - - RtlFreeHeap(RtlGetProcessHeap(), 0, Request); - - return TRUE; + MultiByteToWideChar(CP_ACP, 0, lpConsoleTitle, -1, WideTitle, Length); + Ret = SetConsoleTitleW(WideTitle); + HeapFree(GetProcessHeap(), 0, WideTitle); + return Ret; } Modified: trunk/reactos/include/reactos/subsys/csrss/csrss.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/reactos/subsys/csr… ============================================================================== --- trunk/reactos/include/reactos/subsys/csrss/csrss.h [iso-8859-1] (original) +++ trunk/reactos/include/reactos/subsys/csrss/csrss.h [iso-8859-1] Fri Jun 4 08:36:12 2010 @@ -207,13 +207,13 @@ typedef struct { DWORD Length; - WCHAR Title[0]; + PWCHAR Title; } CSRSS_SET_TITLE, *PCSRSS_SET_TITLE; typedef struct { DWORD Length; - WCHAR Title[0]; + PWCHAR Title; } CSRSS_GET_TITLE, *PCSRSS_GET_TITLE; typedef struct @@ -487,11 +487,6 @@ #define CSRSS_MAX_READ_CONSOLE (LPC_MAX_DATA_LENGTH - CSR_API_MESSAGE_HEADER_SIZE(CSRSS_READ_CONSOLE)) #define CSRSS_MAX_READ_CONSOLE_OUTPUT_CHAR (LPC_MAX_DATA_LENGTH - CSR_API_MESSAGE_HEADER_SIZE(CSRSS_READ_CONSOLE_OUTPUT_CHAR)) #define CSRSS_MAX_READ_CONSOLE_OUTPUT_ATTRIB (LPC_MAX_DATA_LENGTH - CSR_API_MESSAGE_HEADER_SIZE(CSRSS_READ_CONSOLE_OUTPUT_ATTRIB)) -#define CSRSS_MAX_GET_PROCESS_LIST (LPC_MAX_DATA_LENGTH - CSR_API_MESSAGE_HEADER_SIZE(CSRSS_GET_PROCESS_LIST)) - -/* WCHARs, not bytes! */ -#define CSRSS_MAX_TITLE_LENGTH 80 -#define CSRSS_MAX_ALIAS_TARGET_LENGTH 80 #define CREATE_PROCESS (0x0) #define TERMINATE_PROCESS (0x1) Modified: trunk/reactos/subsystems/win32/csrss/win32csr/alias.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/subsystems/win32/csrss/win… ============================================================================== --- trunk/reactos/subsystems/win32/csrss/win32csr/alias.c [iso-8859-1] (original) +++ trunk/reactos/subsystems/win32/csrss/win32csr/alias.c [iso-8859-1] Fri Jun 4 08:36:12 2010 @@ -31,21 +31,6 @@ } ALIAS_HEADER, *PALIAS_HEADER; -/* Ensure that a buffer is contained within the process's shared memory section. */ -static BOOL -ValidateBuffer(PCSRSS_PROCESS_DATA ProcessData, PVOID Buffer, ULONG Size) -{ - ULONG Offset = (BYTE *)Buffer - (BYTE *)ProcessData->CsrSectionViewBase; - if (Offset >= ProcessData->CsrSectionViewSize - || Size > (ProcessData->CsrSectionViewSize - Offset)) - { - DPRINT1("Invalid buffer %p %d; not within %p %d\n", - Buffer, Size, ProcessData->CsrSectionViewBase, ProcessData->CsrSectionViewSize); - return FALSE; - } - return TRUE; -} - static PALIAS_HEADER IntFindAliasHeader(PALIAS_HEADER RootHeader, LPCWSTR lpExeName) @@ -415,7 +400,8 @@ return STATUS_BUFFER_TOO_SMALL; } - if (!ValidateBuffer(ProcessData, lpTarget, Request->Data.GetConsoleAlias.TargetBufferLength)) + if (!Win32CsrValidateBuffer(ProcessData, lpTarget, + Request->Data.GetConsoleAlias.TargetBufferLength, 1)) { ConioUnlockConsole(Console); return STATUS_ACCESS_VIOLATION; @@ -457,9 +443,10 @@ return STATUS_BUFFER_OVERFLOW; } - if (!ValidateBuffer(ProcessData, - Request->Data.GetAllConsoleAlias.AliasBuffer, - Request->Data.GetAllConsoleAlias.AliasBufferLength)) + if (!Win32CsrValidateBuffer(ProcessData, + Request->Data.GetAllConsoleAlias.AliasBuffer, + Request->Data.GetAllConsoleAlias.AliasBufferLength, + 1)) { ConioUnlockConsole(Console); return STATUS_ACCESS_VIOLATION; @@ -532,9 +519,10 @@ return STATUS_INVALID_PARAMETER; } - if (!ValidateBuffer(ProcessData, - Request->Data.GetConsoleAliasesExes.ExeNames, - Request->Data.GetConsoleAliasesExes.Length)) + if (!Win32CsrValidateBuffer(ProcessData, + Request->Data.GetConsoleAliasesExes.ExeNames, + Request->Data.GetConsoleAliasesExes.Length, + 1)) { ConioUnlockConsole(Console); return STATUS_ACCESS_VIOLATION; Modified: trunk/reactos/subsystems/win32/csrss/win32csr/coninput.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/subsystems/win32/csrss/win… ============================================================================== --- trunk/reactos/subsystems/win32/csrss/win32csr/coninput.c [iso-8859-1] (original) +++ trunk/reactos/subsystems/win32/csrss/win32csr/coninput.c [iso-8859-1] Fri Jun 4 08:36:12 2010 @@ -678,7 +678,6 @@ { NTSTATUS Status; PCSRSS_CONSOLE Console; - DWORD Size; DWORD Length; PLIST_ENTRY CurrentItem; PINPUT_RECORD InputRecord; @@ -698,10 +697,8 @@ InputRecord = Request->Data.PeekConsoleInputRequest.InputRecord; Length = Request->Data.PeekConsoleInputRequest.Length; - Size = Length * sizeof(INPUT_RECORD); - - if (((PVOID)InputRecord < ProcessData->CsrSectionViewBase) - || (((ULONG_PTR)InputRecord + Size) > ((ULONG_PTR)ProcessData->CsrSectionViewBase + ProcessData->CsrSectionViewSize))) + + if (!Win32CsrValidateBuffer(ProcessData, InputRecord, Length, sizeof(INPUT_RECORD))) { ConioUnlockConsole(Console); return STATUS_ACCESS_VIOLATION; @@ -749,7 +746,6 @@ PCSRSS_CONSOLE Console; NTSTATUS Status; DWORD Length; - DWORD Size; DWORD i; ConsoleInput* Record; @@ -766,10 +762,8 @@ InputRecord = Request->Data.WriteConsoleInputRequest.InputRecord; Length = Request->Data.WriteConsoleInputRequest.Length; - Size = Length * sizeof(INPUT_RECORD); - - if (((PVOID)InputRecord < ProcessData->CsrSectionViewBase) - || (((ULONG_PTR)InputRecord + Size) > ((ULONG_PTR)ProcessData->CsrSectionViewBase + ProcessData->CsrSectionViewSize))) + + if (!Win32CsrValidateBuffer(ProcessData, InputRecord, Length, sizeof(INPUT_RECORD))) { ConioUnlockConsole(Console); return STATUS_ACCESS_VIOLATION; Modified: trunk/reactos/subsystems/win32/csrss/win32csr/conoutput.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/subsystems/win32/csrss/win… ============================================================================== --- trunk/reactos/subsystems/win32/csrss/win32csr/conoutput.c [iso-8859-1] (original) +++ trunk/reactos/subsystems/win32/csrss/win32csr/conoutput.c [iso-8859-1] Fri Jun 4 08:36:12 2010 @@ -1084,7 +1084,6 @@ COORD BufferSize; NTSTATUS Status; PBYTE Ptr; - DWORD PSize; DPRINT("CsrWriteConsoleOutput\n"); @@ -1101,12 +1100,10 @@ Console = Buff->Header.Console; BufferSize = Request->Data.WriteConsoleOutputRequest.BufferSize; - PSize = BufferSize.X * BufferSize.Y * sizeof(CHAR_INFO); BufferCoord = Request->Data.WriteConsoleOutputRequest.BufferCoord; CharInfo = Request->Data.WriteConsoleOutputRequest.CharInfo; - if (((PVOID)CharInfo < ProcessData->CsrSectionViewBase) || - (((ULONG_PTR)CharInfo + PSize) > - ((ULONG_PTR)ProcessData->CsrSectionViewBase + ProcessData->CsrSectionViewSize))) + if (!Win32CsrValidateBuffer(ProcessData, CharInfo, + BufferSize.X * BufferSize.Y, sizeof(CHAR_INFO))) { ConioUnlockScreenBuffer(Buff); return STATUS_ACCESS_VIOLATION; @@ -1395,8 +1392,6 @@ PCHAR_INFO CharInfo; PCHAR_INFO CurCharInfo; PCSRSS_SCREEN_BUFFER Buff; - DWORD Size; - DWORD Length; DWORD SizeX, SizeY; NTSTATUS Status; COORD BufferSize; @@ -1423,14 +1418,12 @@ ReadRegion = Request->Data.ReadConsoleOutputRequest.ReadRegion; BufferSize = Request->Data.ReadConsoleOutputRequest.BufferSize; BufferCoord = Request->Data.ReadConsoleOutputRequest.BufferCoord; - Length = BufferSize.X * BufferSize.Y; - Size = Length * sizeof(CHAR_INFO); /* FIXME: Is this correct? */ CodePage = ProcessData->Console->OutputCodePage; - if (((PVOID)CharInfo < ProcessData->CsrSectionViewBase) - || (((ULONG_PTR)CharInfo + Size) > ((ULONG_PTR)ProcessData->CsrSectionViewBase + ProcessData->CsrSectionViewSize))) + if (!Win32CsrValidateBuffer(ProcessData, CharInfo, + BufferSize.X * BufferSize.Y, sizeof(CHAR_INFO))) { ConioUnlockScreenBuffer(Buff); return STATUS_ACCESS_VIOLATION; Modified: trunk/reactos/subsystems/win32/csrss/win32csr/console.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/subsystems/win32/csrss/win… ============================================================================== --- trunk/reactos/subsystems/win32/csrss/win32csr/console.c [iso-8859-1] (original) +++ trunk/reactos/subsystems/win32/csrss/win32csr/console.c [iso-8859-1] Fri Jun 4 08:36:12 2010 @@ -455,19 +455,15 @@ DPRINT("CsrSetTitle\n"); - if (Request->Header.u1.s1.TotalLength - < CSR_API_MESSAGE_HEADER_SIZE(CSRSS_SET_TITLE) - + Request->Data.SetTitleRequest.Length) - { - DPRINT1("Invalid request size\n"); - Request->Header.u1.s1.TotalLength = sizeof(CSR_API_MESSAGE); - Request->Header.u1.s1.DataLength = sizeof(CSR_API_MESSAGE) - sizeof(PORT_MESSAGE); - return STATUS_INVALID_PARAMETER; - } - - Status = ConioConsoleFromProcessData(ProcessData, &Console); - Request->Header.u1.s1.TotalLength = sizeof(CSR_API_MESSAGE); - Request->Header.u1.s1.DataLength = sizeof(CSR_API_MESSAGE) - sizeof(PORT_MESSAGE); + Request->Header.u1.s1.TotalLength = sizeof(CSR_API_MESSAGE); + Request->Header.u1.s1.DataLength = sizeof(CSR_API_MESSAGE) - sizeof(PORT_MESSAGE); + if (!Win32CsrValidateBuffer(ProcessData, Request->Data.SetTitleRequest.Title, + Request->Data.SetTitleRequest.Length, 1)) + { + return STATUS_ACCESS_VIOLATION; + } + + Status = ConioConsoleFromProcessData(ProcessData, &Console); if(NT_SUCCESS(Status)) { Buffer = RtlAllocateHeap(RtlGetProcessHeap(), 0, Request->Data.SetTitleRequest.Length); @@ -507,6 +503,13 @@ Request->Header.u1.s1.TotalLength = sizeof(CSR_API_MESSAGE); Request->Header.u1.s1.DataLength = sizeof(CSR_API_MESSAGE) - sizeof(PORT_MESSAGE); + + if (!Win32CsrValidateBuffer(ProcessData, Request->Data.GetTitleRequest.Title, + Request->Data.GetTitleRequest.Length, 1)) + { + return STATUS_ACCESS_VIOLATION; + } + Status = ConioConsoleFromProcessData(ProcessData, &Console); if (! NT_SUCCESS(Status)) { @@ -515,19 +518,16 @@ } /* Copy title of the console to the user title buffer */ - RtlZeroMemory(&Request->Data.GetTitleRequest, sizeof(CSRSS_GET_TITLE)); + if (Request->Data.GetTitleRequest.Length >= sizeof(WCHAR)) + { + Length = min(Request->Data.GetTitleRequest.Length - sizeof(WCHAR), Console->Title.Length); + memcpy(Request->Data.GetTitleRequest.Title, Console->Title.Buffer, Length); + Request->Data.GetTitleRequest.Title[Length / sizeof(WCHAR)] = L'\0'; + } + Request->Data.GetTitleRequest.Length = Console->Title.Length; - memcpy (Request->Data.GetTitleRequest.Title, Console->Title.Buffer, - Console->Title.Length); - Length = CSR_API_MESSAGE_HEADER_SIZE(CSRSS_SET_TITLE) + Console->Title.Length; - - ConioUnlockConsole(Console); - - if (Length > sizeof(CSR_API_MESSAGE)) - { - Request->Header.u1.s1.TotalLength = Length; - Request->Header.u1.s1.DataLength = Length - sizeof(PORT_MESSAGE); - } + + ConioUnlockConsole(Console); return STATUS_SUCCESS; } @@ -754,7 +754,6 @@ PLIST_ENTRY current_entry; ULONG nItems = 0; NTSTATUS Status; - ULONG_PTR Offset; DPRINT("CsrGetProcessList\n"); @@ -762,13 +761,8 @@ Request->Header.u1.s1.DataLength = sizeof(CSR_API_MESSAGE) - sizeof(PORT_MESSAGE); Buffer = Request->Data.GetProcessListRequest.ProcessId; - Offset = (PBYTE)Buffer - (PBYTE)ProcessData->CsrSectionViewBase; - if (Offset >= ProcessData->CsrSectionViewSize - || (Request->Data.GetProcessListRequest.nMaxIds * sizeof(DWORD)) > (ProcessData->CsrSectionViewSize - Offset) - || Offset & (sizeof(DWORD) - 1)) - { + if (!Win32CsrValidateBuffer(ProcessData, Buffer, Request->Data.GetProcessListRequest.nMaxIds, sizeof(DWORD))) return STATUS_ACCESS_VIOLATION; - } Status = ConioConsoleFromProcessData(ProcessData, &Console); if (! NT_SUCCESS(Status)) Modified: trunk/reactos/subsystems/win32/csrss/win32csr/dllmain.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/subsystems/win32/csrss/win… ============================================================================== --- trunk/reactos/subsystems/win32/csrss/win32csr/dllmain.c [iso-8859-1] (original) +++ trunk/reactos/subsystems/win32/csrss/win32csr/dllmain.c [iso-8859-1] Fri Jun 4 08:36:12 2010 @@ -100,6 +100,32 @@ return TRUE; } +/* Ensure that a captured buffer is safe to access */ +BOOL FASTCALL +Win32CsrValidateBuffer(PCSRSS_PROCESS_DATA ProcessData, PVOID Buffer, + SIZE_T NumElements, SIZE_T ElementSize) +{ + /* Check that the following conditions are true: + * 1. The start of the buffer is somewhere within the process's + * shared memory section view. + * 2. The remaining space in the view is at least as large as the buffer. + * (NB: Please don't try to "optimize" this by using multiplication + * instead of division; remember that 2147483648 * 2 = 0.) + * 3. The buffer is DWORD-aligned. + */ + ULONG_PTR Offset = (BYTE *)Buffer - (BYTE *)ProcessData->CsrSectionViewBase; + if (Offset >= ProcessData->CsrSectionViewSize + || NumElements > (ProcessData->CsrSectionViewSize - Offset) / ElementSize + || (Offset & (sizeof(DWORD) - 1)) != 0) + { + DPRINT1("Invalid buffer %p(%u*%u); section view is %p(%u)\n", + Buffer, NumElements, ElementSize, + ProcessData->CsrSectionViewBase, ProcessData->CsrSectionViewSize); + return FALSE; + } + return TRUE; +} + NTSTATUS FASTCALL Win32CsrEnumProcesses(CSRSS_ENUM_PROCESS_PROC EnumProc, PVOID Context) Modified: trunk/reactos/subsystems/win32/csrss/win32csr/win32csr.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/subsystems/win32/csrss/win… ============================================================================== --- trunk/reactos/subsystems/win32/csrss/win32csr/win32csr.h [iso-8859-1] (original) +++ trunk/reactos/subsystems/win32/csrss/win32csr/win32csr.h [iso-8859-1] Fri Jun 4 08:36:12 2010 @@ -63,6 +63,10 @@ CSR_API(CsrDuplicateHandle); CSR_API(CsrGetInputWaitHandle); +BOOL FASTCALL Win32CsrValidateBuffer(PCSRSS_PROCESS_DATA ProcessData, + PVOID Buffer, + SIZE_T NumElements, + SIZE_T ElementSize); NTSTATUS FASTCALL Win32CsrEnumProcesses(CSRSS_ENUM_PROCESS_PROC EnumProc, PVOID Context);

14 years, 5 months

[tkreuzer] 47561: revert 47559 and 47560 (once again... sigh)

by tkreuzer＠svn.reactos.org

Author: tkreuzer Date: Fri Jun 4 02:49:33 2010 New Revision: 47561 URL: http://svn.reactos.org/svn/reactos?rev=47561&view=rev Log: revert 47559 and 47560 (once again... sigh) Modified: trunk/reactos/include/ddk/ntddk.h [This mail would be too long, it was shortened to contain the URLs only.] Modified: trunk/reactos/include/ddk/ntddk.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/ddk/ntddk.h?rev=47…

14 years, 5 months

[tkreuzer] 47560: try to fix build

by tkreuzer＠svn.reactos.org

Author: tkreuzer Date: Fri Jun 4 02:26:49 2010 New Revision: 47560 URL: http://svn.reactos.org/svn/reactos?rev=47560&view=rev Log: try to fix build Modified: trunk/reactos/include/ddk/ntddk.h Modified: trunk/reactos/include/ddk/ntddk.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/ddk/ntddk.h?rev=47… ============================================================================== --- trunk/reactos/include/ddk/ntddk.h [iso-8859-1] (original) +++ trunk/reactos/include/ddk/ntddk.h [iso-8859-1] Fri Jun 4 02:26:49 2010 @@ -1043,6 +1043,8 @@ PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR Descriptors[ANYSIZE_ARRAY]; } PHYSICAL_COUNTER_RESOURCE_LIST, *PPHYSICAL_COUNTER_RESOURCE_LIST; +#endif // 0 + typedef VOID (NTAPI *PciPin2Line)( IN struct _BUS_HANDLER *BusHandler, @@ -1079,6 +1081,8 @@ PCI_SLOT_NUMBER ParentSlot; PVOID Reserved[4]; } PCIBUSDATA, *PPCIBUSDATA; + +#if 0 // Someone (testbot? RosBE for linux?) doesn't like too many types it seems... #ifndef _PCIINTRF_X_ #define _PCIINTRF_X_

14 years, 5 months

[tkreuzer] 47559: [DDK] Merge the rest of the old header-branch version of ntddk.h, but with a large number of additional types #if 0'ed out

by tkreuzer＠svn.reactos.org

Author: tkreuzer Date: Fri Jun 4 02:19:39 2010 New Revision: 47559 URL: http://svn.reactos.org/svn/reactos?rev=47559&view=rev Log: [DDK] Merge the rest of the old header-branch version of ntddk.h, but with a large number of additional types #if 0'ed out Modified: trunk/reactos/include/ddk/ntddk.h [This mail would be too long, it was shortened to contain the URLs only.] Modified: trunk/reactos/include/ddk/ntddk.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/ddk/ntddk.h?rev=47…

14 years, 5 months

[tkreuzer] 47558: [DDK] try to work around the testbot brokenness with an #if 0"

by tkreuzer＠svn.reactos.org

Author: tkreuzer Date: Fri Jun 4 01:40:33 2010 New Revision: 47558 URL: http://svn.reactos.org/svn/reactos?rev=47558&view=rev Log: [DDK] try to work around the testbot brokenness with an #if 0" Modified: trunk/reactos/include/ddk/ntddk.h Modified: trunk/reactos/include/ddk/ntddk.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/ddk/ntddk.h?rev=47… ============================================================================== --- trunk/reactos/include/ddk/ntddk.h [iso-8859-1] (original) +++ trunk/reactos/include/ddk/ntddk.h [iso-8859-1] Fri Jun 4 01:40:33 2010 @@ -703,6 +703,7 @@ USHORT AsUSHORT; } PCI_EXPRESS_SLOT_CONTROL_REGISTER, *PPCI_EXPRESS_SLOT_CONTROL_REGISTER; +#if 0 // Someone (testbot? RosBE for linux?) doesn't like too many types it seems... typedef union _PCI_EXPRESS_SLOT_STATUS_REGISTER { struct { USHORT AttentionButtonPressed:1; @@ -963,6 +964,8 @@ #define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_EX FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK #endif /* (NTDDI_VERSION >= NTDDI_WIN7) */ + +#endif // 0 typedef enum _HAL_QUERY_INFORMATION_CLASS { HalInstalledBusInformation,

14 years, 5 months

[tkreuzer] 47557: [HAL] Include the correct headers for amd64 vs i386

by tkreuzer＠svn.reactos.org

Author: tkreuzer Date: Fri Jun 4 01:18:20 2010 New Revision: 47557 URL: http://svn.reactos.org/svn/reactos?rev=47557&view=rev Log: [HAL] Include the correct headers for amd64 vs i386 Modified: trunk/reactos/hal/halx86/include/hal.h Modified: trunk/reactos/hal/halx86/include/hal.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/include/hal.h?r… ============================================================================== --- trunk/reactos/hal/halx86/include/hal.h [iso-8859-1] (original) +++ trunk/reactos/hal/halx86/include/hal.h [iso-8859-1] Fri Jun 4 01:18:20 2010 @@ -32,11 +32,13 @@ /* Internal kernel headers */ #include "internal/pci.h" #define KeGetCurrentThread _KeGetCurrentThread +#ifdef _M_AMD64 +#include <internal/amd64/ke.h> +#include <internal/amd64/mm.h> +#include "internal/amd64/intrin_i.h" +#else #include <internal/i386/ke.h> #include <internal/i386/mm.h> -#ifdef _M_AMD64 -#include "internal/amd64/intrin_i.h" -#else #include "internal/i386/intrin_i.h" #endif

14 years, 5 months

[tkreuzer] 47556: [DDK] In an incredibly daring move, add even more types to ntddk.h

by tkreuzer＠svn.reactos.org

Author: tkreuzer Date: Fri Jun 4 01:08:40 2010 New Revision: 47556 URL: http://svn.reactos.org/svn/reactos?rev=47556&view=rev Log: [DDK] In an incredibly daring move, add even more types to ntddk.h Modified: trunk/reactos/include/ddk/ntddk.h Modified: trunk/reactos/include/ddk/ntddk.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/ddk/ntddk.h?rev=47… ============================================================================== --- trunk/reactos/include/ddk/ntddk.h [iso-8859-1] (original) +++ trunk/reactos/include/ddk/ntddk.h [iso-8859-1] Fri Jun 4 01:08:40 2010 @@ -702,6 +702,267 @@ } DUMMYSTRUCTNAME; USHORT AsUSHORT; } PCI_EXPRESS_SLOT_CONTROL_REGISTER, *PPCI_EXPRESS_SLOT_CONTROL_REGISTER; + +typedef union _PCI_EXPRESS_SLOT_STATUS_REGISTER { + struct { + USHORT AttentionButtonPressed:1; + USHORT PowerFaultDetected:1; + USHORT MRLSensorChanged:1; + USHORT PresenceDetectChanged:1; + USHORT CommandCompleted:1; + USHORT MRLSensorState:1; + USHORT PresenceDetectState:1; + USHORT ElectromechanicalLockEngaged:1; + USHORT DataLinkStateChanged:1; + USHORT Rsvd:7; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_SLOT_STATUS_REGISTER, *PPCI_EXPRESS_SLOT_STATUS_REGISTER; + +typedef union _PCI_EXPRESS_ROOT_CONTROL_REGISTER { + struct { + USHORT CorrectableSerrEnable:1; + USHORT NonFatalSerrEnable:1; + USHORT FatalSerrEnable:1; + USHORT PMEInterruptEnable:1; + USHORT CRSSoftwareVisibilityEnable:1; + USHORT Rsvd:11; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_ROOT_CONTROL_REGISTER, *PPCI_EXPRESS_ROOT_CONTROL_REGISTER; + +typedef union _PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER { + struct { + USHORT CRSSoftwareVisibility:1; + USHORT Rsvd:15; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER, *PPCI_EXPRESS_ROOT_CAPABILITIES_REGISTER; + +typedef union _PCI_EXPRESS_ROOT_STATUS_REGISTER { + struct { + ULONG PMERequestorId:16; + ULONG PMEStatus:1; + ULONG PMEPending:1; + ULONG Rsvd:14; + } DUMMYSTRUCTNAME; + ULONG AsULONG; +} PCI_EXPRESS_ROOT_STATUS_REGISTER, *PPCI_EXPRESS_ROOT_STATUS_REGISTER; + +typedef struct _PCI_EXPRESS_CAPABILITY { + PCI_CAPABILITIES_HEADER Header; + PCI_EXPRESS_CAPABILITIES_REGISTER ExpressCapabilities; + PCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER DeviceCapabilities; + PCI_EXPRESS_DEVICE_CONTROL_REGISTER DeviceControl; + PCI_EXPRESS_DEVICE_STATUS_REGISTER DeviceStatus; + PCI_EXPRESS_LINK_CAPABILITIES_REGISTER LinkCapabilities; + PCI_EXPRESS_LINK_CONTROL_REGISTER LinkControl; + PCI_EXPRESS_LINK_STATUS_REGISTER LinkStatus; + PCI_EXPRESS_SLOT_CAPABILITIES_REGISTER SlotCapabilities; + PCI_EXPRESS_SLOT_CONTROL_REGISTER SlotControl; + PCI_EXPRESS_SLOT_STATUS_REGISTER SlotStatus; + PCI_EXPRESS_ROOT_CONTROL_REGISTER RootControl; + PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER RootCapabilities; + PCI_EXPRESS_ROOT_STATUS_REGISTER RootStatus; +} PCI_EXPRESS_CAPABILITY, *PPCI_EXPRESS_CAPABILITY; + +typedef enum { + MRLClosed = 0, + MRLOpen +} PCI_EXPRESS_MRL_STATE; + +typedef enum { + SlotEmpty = 0, + CardPresent +} PCI_EXPRESS_CARD_PRESENCE; + +typedef enum { + IndicatorOn = 1, + IndicatorBlink, + IndicatorOff +} PCI_EXPRESS_INDICATOR_STATE; + +typedef enum { + PowerOn = 0, + PowerOff +} PCI_EXPRESS_POWER_STATE; + +typedef enum { + L0sEntrySupport = 1, + L0sAndL1EntrySupport = 3 +} PCI_EXPRESS_ASPM_SUPPORT; + +typedef enum { + L0sAndL1EntryDisabled, + L0sEntryEnabled, + L1EntryEnabled, + L0sAndL1EntryEnabled +} PCI_EXPRESS_ASPM_CONTROL; + +typedef enum { + L0s_Below64ns = 0, + L0s_64ns_128ns, + L0s_128ns_256ns, + L0s_256ns_512ns, + L0s_512ns_1us, + L0s_1us_2us, + L0s_2us_4us, + L0s_Above4us +} PCI_EXPRESS_L0s_EXIT_LATENCY; + +typedef enum { + L1_Below1us = 0, + L1_1us_2us, + L1_2us_4us, + L1_4us_8us, + L1_8us_16us, + L1_16us_32us, + L1_32us_64us, + L1_Above64us +} PCI_EXPRESS_L1_EXIT_LATENCY; + +typedef enum { + PciExpressEndpoint = 0, + PciExpressLegacyEndpoint, + PciExpressRootPort = 4, + PciExpressUpstreamSwitchPort, + PciExpressDownstreamSwitchPort, + PciExpressToPciXBridge, + PciXToExpressBridge, + PciExpressRootComplexIntegratedEndpoint, + PciExpressRootComplexEventCollector +} PCI_EXPRESS_DEVICE_TYPE; + +typedef enum { + MaxPayload128Bytes = 0, + MaxPayload256Bytes, + MaxPayload512Bytes, + MaxPayload1024Bytes, + MaxPayload2048Bytes, + MaxPayload4096Bytes +} PCI_EXPRESS_MAX_PAYLOAD_SIZE; + +typedef union _PCI_EXPRESS_PME_REQUESTOR_ID { + struct { + USHORT FunctionNumber:3; + USHORT DeviceNumber:5; + USHORT BusNumber:8; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_PME_REQUESTOR_ID, *PPCI_EXPRESS_PME_REQUESTOR_ID; + +#if defined(_WIN64) + +#ifndef USE_DMA_MACROS +#define USE_DMA_MACROS +#endif + +#ifndef NO_LEGACY_DRIVERS +#define NO_LEGACY_DRIVERS +#endif + +#endif /* defined(_WIN64) */ + +typedef enum _PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE { + ResourceTypeSingle = 0, + ResourceTypeRange, + ResourceTypeExtendedCounterConfiguration, + ResourceTypeOverflow, + ResourceTypeMax +} PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE; + +typedef struct _PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR { + PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE Type; + ULONG Flags; + union { + ULONG CounterIndex; + ULONG ExtendedRegisterAddress; + struct { + ULONG Begin; + ULONG End; + } Range; + } u; +} PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR, *PPHYSICAL_COUNTER_RESOURCE_DESCRIPTOR; + +typedef struct _PHYSICAL_COUNTER_RESOURCE_LIST { + ULONG Count; + PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR Descriptors[ANYSIZE_ARRAY]; +} PHYSICAL_COUNTER_RESOURCE_LIST, *PPHYSICAL_COUNTER_RESOURCE_LIST; + +#ifndef _PCIINTRF_X_ +#define _PCIINTRF_X_ + +typedef ULONG +(NTAPI *PCI_READ_WRITE_CONFIG)( + IN PVOID Context, + IN ULONG BusOffset, + IN ULONG Slot, + IN PVOID Buffer, + IN ULONG Offset, + IN ULONG Length); + +typedef VOID +(NTAPI *PCI_PIN_TO_LINE)( + IN PVOID Context, + IN PPCI_COMMON_CONFIG PciData); + +typedef VOID +(NTAPI *PCI_LINE_TO_PIN)( + IN PVOID Context, + IN PPCI_COMMON_CONFIG PciNewData, + IN PPCI_COMMON_CONFIG PciOldData); + +typedef VOID +(NTAPI *PCI_ROOT_BUS_CAPABILITY)( + IN PVOID Context, + OUT PPCI_ROOT_BUS_HARDWARE_CAPABILITY HardwareCapability); + +typedef VOID +(NTAPI *PCI_EXPRESS_WAKE_CONTROL)( + IN PVOID Context, + IN BOOLEAN EnableWake); + +typedef struct _PCI_BUS_INTERFACE_STANDARD { + USHORT Size; + USHORT Version; + PVOID Context; + PINTERFACE_REFERENCE InterfaceReference; + PINTERFACE_DEREFERENCE InterfaceDereference; + PCI_READ_WRITE_CONFIG ReadConfig; + PCI_READ_WRITE_CONFIG WriteConfig; + PCI_PIN_TO_LINE PinToLine; + PCI_LINE_TO_PIN LineToPin; + PCI_ROOT_BUS_CAPABILITY RootBusCapability; + PCI_EXPRESS_WAKE_CONTROL ExpressWakeControl; +} PCI_BUS_INTERFACE_STANDARD, *PPCI_BUS_INTERFACE_STANDARD; + +#define PCI_BUS_INTERFACE_STANDARD_VERSION 1 + +#endif /* _PCIINTRF_X_ */ + +#if (NTDDI_VERSION >= NTDDI_WIN7) + +#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX 0x00004000 +#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX 0x00008000 +#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_EX \ + (FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX | \ + FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX) + +#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_DEPRECATED 0x00000200 +#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_DEPRECATED 0x00000300 +#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_DEPRECATED 0x00000300 + +#else + +#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL 0x00000200 +#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL 0x00000300 +#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK 0x00000300 + +#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL +#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL +#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_EX FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK + +#endif /* (NTDDI_VERSION >= NTDDI_WIN7) */ typedef enum _HAL_QUERY_INFORMATION_CLASS { HalInstalledBusInformation,

14 years, 5 months

[tkreuzer] 47555: [DDK] 2nd try, this time adding half of the structures.

by tkreuzer＠svn.reactos.org

Author: tkreuzer Date: Fri Jun 4 00:25:25 2010 New Revision: 47555 URL: http://svn.reactos.org/svn/reactos?rev=47555&view=rev Log: [DDK] 2nd try, this time adding half of the structures. Modified: trunk/reactos/include/ddk/ntddk.h Modified: trunk/reactos/include/ddk/ntddk.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/ddk/ntddk.h?rev=47… ============================================================================== --- trunk/reactos/include/ddk/ntddk.h [iso-8859-1] (original) +++ trunk/reactos/include/ddk/ntddk.h [iso-8859-1] Fri Jun 4 00:25:25 2010 @@ -321,6 +321,387 @@ PARBITER_HANDLER ArbiterHandler; ULONG Flags; } ARBITER_INTERFACE, *PARBITER_INTERFACE; + +typedef struct _PCI_AGP_CAPABILITY { + PCI_CAPABILITIES_HEADER Header; + USHORT Minor:4; + USHORT Major:4; + USHORT Rsvd1:8; + struct _PCI_AGP_STATUS { + ULONG Rate:3; + ULONG Agp3Mode:1; + ULONG FastWrite:1; + ULONG FourGB:1; + ULONG HostTransDisable:1; + ULONG Gart64:1; + ULONG ITA_Coherent:1; + ULONG SideBandAddressing:1; + ULONG CalibrationCycle:3; + ULONG AsyncRequestSize:3; + ULONG Rsvd1:1; + ULONG Isoch:1; + ULONG Rsvd2:6; + ULONG RequestQueueDepthMaximum:8; + } AGPStatus; + struct _PCI_AGP_COMMAND { + ULONG Rate:3; + ULONG Rsvd1:1; + ULONG FastWriteEnable:1; + ULONG FourGBEnable:1; + ULONG Rsvd2:1; + ULONG Gart64:1; + ULONG AGPEnable:1; + ULONG SBAEnable:1; + ULONG CalibrationCycle:3; + ULONG AsyncReqSize:3; + ULONG Rsvd3:8; + ULONG RequestQueueDepth:8; + } AGPCommand; +} PCI_AGP_CAPABILITY, *PPCI_AGP_CAPABILITY; + +typedef enum _EXTENDED_AGP_REGISTER { + IsochStatus, + AgpControl, + ApertureSize, + AperturePageSize, + GartLow, + GartHigh, + IsochCommand +} EXTENDED_AGP_REGISTER, *PEXTENDED_AGP_REGISTER; + +typedef struct _PCI_AGP_ISOCH_STATUS { + ULONG ErrorCode:2; + ULONG Rsvd1:1; + ULONG Isoch_L:3; + ULONG Isoch_Y:2; + ULONG Isoch_N:8; + ULONG Rsvd2:16; +} PCI_AGP_ISOCH_STATUS, *PPCI_AGP_ISOCH_STATUS; + +typedef struct _PCI_AGP_CONTROL { + ULONG Rsvd1:7; + ULONG GTLB_Enable:1; + ULONG AP_Enable:1; + ULONG CAL_Disable:1; + ULONG Rsvd2:22; +} PCI_AGP_CONTROL, *PPCI_AGP_CONTROL; + +typedef struct _PCI_AGP_APERTURE_PAGE_SIZE { + USHORT PageSizeMask:11; + USHORT Rsvd1:1; + USHORT PageSizeSelect:4; +} PCI_AGP_APERTURE_PAGE_SIZE, *PPCI_AGP_APERTURE_PAGE_SIZE; + +typedef struct _PCI_AGP_ISOCH_COMMAND { + USHORT Rsvd1:6; + USHORT Isoch_Y:2; + USHORT Isoch_N:8; +} PCI_AGP_ISOCH_COMMAND, *PPCI_AGP_ISOCH_COMMAND; + +typedef struct PCI_AGP_EXTENDED_CAPABILITY { + PCI_AGP_ISOCH_STATUS IsochStatus; + PCI_AGP_CONTROL AgpControl; + USHORT ApertureSize; + PCI_AGP_APERTURE_PAGE_SIZE AperturePageSize; + ULONG GartLow; + ULONG GartHigh; + PCI_AGP_ISOCH_COMMAND IsochCommand; +} PCI_AGP_EXTENDED_CAPABILITY, *PPCI_AGP_EXTENDED_CAPABILITY; + +#define PCI_AGP_RATE_1X 0x1 +#define PCI_AGP_RATE_2X 0x2 +#define PCI_AGP_RATE_4X 0x4 + +#define PCIX_MODE_CONVENTIONAL_PCI 0x0 +#define PCIX_MODE1_66MHZ 0x1 +#define PCIX_MODE1_100MHZ 0x2 +#define PCIX_MODE1_133MHZ 0x3 +#define PCIX_MODE2_266_66MHZ 0x9 +#define PCIX_MODE2_266_100MHZ 0xA +#define PCIX_MODE2_266_133MHZ 0xB +#define PCIX_MODE2_533_66MHZ 0xD +#define PCIX_MODE2_533_100MHZ 0xE +#define PCIX_MODE2_533_133MHZ 0xF + +#define PCIX_VERSION_MODE1_ONLY 0x0 +#define PCIX_VERSION_MODE2_ECC 0x1 +#define PCIX_VERSION_DUAL_MODE_ECC 0x2 + +typedef struct _PCIX_BRIDGE_CAPABILITY { + PCI_CAPABILITIES_HEADER Header; + union { + struct { + USHORT Bus64Bit:1; + USHORT Bus133MHzCapable:1; + USHORT SplitCompletionDiscarded:1; + USHORT UnexpectedSplitCompletion:1; + USHORT SplitCompletionOverrun:1; + USHORT SplitRequestDelayed:1; + USHORT BusModeFrequency:4; + USHORT Rsvd:2; + USHORT Version:2; + USHORT Bus266MHzCapable:1; + USHORT Bus533MHzCapable:1; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; + } SecondaryStatus; + union { + struct { + ULONG FunctionNumber:3; + ULONG DeviceNumber:5; + ULONG BusNumber:8; + ULONG Device64Bit:1; + ULONG Device133MHzCapable:1; + ULONG SplitCompletionDiscarded:1; + ULONG UnexpectedSplitCompletion:1; + ULONG SplitCompletionOverrun:1; + ULONG SplitRequestDelayed:1; + ULONG Rsvd:7; + ULONG DIMCapable:1; + ULONG Device266MHzCapable:1; + ULONG Device533MHzCapable:1; + } DUMMYSTRUCTNAME; + ULONG AsULONG; + } BridgeStatus; + USHORT UpstreamSplitTransactionCapacity; + USHORT UpstreamSplitTransactionLimit; + USHORT DownstreamSplitTransactionCapacity; + USHORT DownstreamSplitTransactionLimit; + union { + struct { + ULONG SelectSecondaryRegisters:1; + ULONG ErrorPresentInOtherBank:1; + ULONG AdditionalCorrectableError:1; + ULONG AdditionalUncorrectableError:1; + ULONG ErrorPhase:3; + ULONG ErrorCorrected:1; + ULONG Syndrome:8; + ULONG ErrorFirstCommand:4; + ULONG ErrorSecondCommand:4; + ULONG ErrorUpperAttributes:4; + ULONG ControlUpdateEnable:1; + ULONG Rsvd:1; + ULONG DisableSingleBitCorrection:1; + ULONG EccMode:1; + } DUMMYSTRUCTNAME; + ULONG AsULONG; + } EccControlStatus; + ULONG EccFirstAddress; + ULONG EccSecondAddress; + ULONG EccAttribute; +} PCIX_BRIDGE_CAPABILITY, *PPCIX_BRIDGE_CAPABILITY; + +typedef struct _PCI_SUBSYSTEM_IDS_CAPABILITY { + PCI_CAPABILITIES_HEADER Header; + USHORT Reserved; + USHORT SubVendorID; + USHORT SubSystemID; +} PCI_SUBSYSTEM_IDS_CAPABILITY, *PPCI_SUBSYSTEM_IDS_CAPABILITY; + +#define OSC_FIRMWARE_FAILURE 0x02 +#define OSC_UNRECOGNIZED_UUID 0x04 +#define OSC_UNRECOGNIZED_REVISION 0x08 +#define OSC_CAPABILITIES_MASKED 0x10 + +#define PCI_ROOT_BUS_OSC_METHOD_CAPABILITY_REVISION 0x01 + +typedef struct _PCI_ROOT_BUS_OSC_SUPPORT_FIELD { + union { + struct { + ULONG ExtendedConfigOpRegions:1; + ULONG ActiveStatePowerManagement:1; + ULONG ClockPowerManagement:1; + ULONG SegmentGroups:1; + ULONG MessageSignaledInterrupts:1; + ULONG WindowsHardwareErrorArchitecture:1; + ULONG Reserved:26; + } DUMMYSTRUCTNAME; + ULONG AsULONG; + } u; +} PCI_ROOT_BUS_OSC_SUPPORT_FIELD, *PPCI_ROOT_BUS_OSC_SUPPORT_FIELD; + +typedef struct _PCI_ROOT_BUS_OSC_CONTROL_FIELD { + union { + struct { + ULONG ExpressNativeHotPlug:1; + ULONG ShpcNativeHotPlug:1; + ULONG ExpressNativePME:1; + ULONG ExpressAdvancedErrorReporting:1; + ULONG ExpressCapabilityStructure:1; + ULONG Reserved:27; + } DUMMYSTRUCTNAME; + ULONG AsULONG; + } u; +} PCI_ROOT_BUS_OSC_CONTROL_FIELD, *PPCI_ROOT_BUS_OSC_CONTROL_FIELD; + +typedef enum _PCI_HARDWARE_INTERFACE { + PciConventional, + PciXMode1, + PciXMode2, + PciExpress +} PCI_HARDWARE_INTERFACE, *PPCI_HARDWARE_INTERFACE; + +typedef enum { + BusWidth32Bits, + BusWidth64Bits +} PCI_BUS_WIDTH; + +typedef struct _PCI_ROOT_BUS_HARDWARE_CAPABILITY { + PCI_HARDWARE_INTERFACE SecondaryInterface; + struct { + BOOLEAN BusCapabilitiesFound; + ULONG CurrentSpeedAndMode; + ULONG SupportedSpeedsAndModes; + BOOLEAN DeviceIDMessagingCapable; + PCI_BUS_WIDTH SecondaryBusWidth; + } DUMMYSTRUCTNAME; + PCI_ROOT_BUS_OSC_SUPPORT_FIELD OscFeatureSupport; + PCI_ROOT_BUS_OSC_CONTROL_FIELD OscControlRequest; + PCI_ROOT_BUS_OSC_CONTROL_FIELD OscControlGranted; +} PCI_ROOT_BUS_HARDWARE_CAPABILITY, *PPCI_ROOT_BUS_HARDWARE_CAPABILITY; + +typedef union _PCI_EXPRESS_CAPABILITIES_REGISTER { + struct { + USHORT CapabilityVersion:4; + USHORT DeviceType:4; + USHORT SlotImplemented:1; + USHORT InterruptMessageNumber:5; + USHORT Rsvd:2; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_CAPABILITIES_REGISTER, *PPCI_EXPRESS_CAPABILITIES_REGISTER; + +typedef union _PCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER { + struct { + ULONG MaxPayloadSizeSupported:3; + ULONG PhantomFunctionsSupported:2; + ULONG ExtendedTagSupported:1; + ULONG L0sAcceptableLatency:3; + ULONG L1AcceptableLatency:3; + ULONG Undefined:3; + ULONG RoleBasedErrorReporting:1; + ULONG Rsvd1:2; + ULONG CapturedSlotPowerLimit:8; + ULONG CapturedSlotPowerLimitScale:2; + ULONG Rsvd2:4; + } DUMMYSTRUCTNAME; + ULONG AsULONG; +} PCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER, *PPCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER; + +#define PCI_EXPRESS_AER_DEVICE_CONTROL_MASK 0x07; + +typedef union _PCI_EXPRESS_DEVICE_CONTROL_REGISTER { + struct { + USHORT CorrectableErrorEnable:1; + USHORT NonFatalErrorEnable:1; + USHORT FatalErrorEnable:1; + USHORT UnsupportedRequestErrorEnable:1; + USHORT EnableRelaxedOrder:1; + USHORT MaxPayloadSize:3; + USHORT ExtendedTagEnable:1; + USHORT PhantomFunctionsEnable:1; + USHORT AuxPowerEnable:1; + USHORT NoSnoopEnable:1; + USHORT MaxReadRequestSize:3; + USHORT BridgeConfigRetryEnable:1; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_DEVICE_CONTROL_REGISTER, *PPCI_EXPRESS_DEVICE_CONTROL_REGISTER; + +#define PCI_EXPRESS_AER_DEVICE_STATUS_MASK 0x0F; + +typedef union _PCI_EXPRESS_DEVICE_STATUS_REGISTER { + struct { + USHORT CorrectableErrorDetected:1; + USHORT NonFatalErrorDetected:1; + USHORT FatalErrorDetected:1; + USHORT UnsupportedRequestDetected:1; + USHORT AuxPowerDetected:1; + USHORT TransactionsPending:1; + USHORT Rsvd:10; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_DEVICE_STATUS_REGISTER, *PPCI_EXPRESS_DEVICE_STATUS_REGISTER; + +typedef union _PCI_EXPRESS_LINK_CAPABILITIES_REGISTER { + struct { + ULONG MaximumLinkSpeed:4; + ULONG MaximumLinkWidth:6; + ULONG ActiveStatePMSupport:2; + ULONG L0sExitLatency:3; + ULONG L1ExitLatency:3; + ULONG ClockPowerManagement:1; + ULONG SurpriseDownErrorReportingCapable:1; + ULONG DataLinkLayerActiveReportingCapable:1; + ULONG Rsvd:3; + ULONG PortNumber:8; + } DUMMYSTRUCTNAME; + ULONG AsULONG; +} PCI_EXPRESS_LINK_CAPABILITIES_REGISTER, *PPCI_EXPRESS_LINK_CAPABILITIES_REGISTER; + +typedef union _PCI_EXPRESS_LINK_CONTROL_REGISTER { + struct { + USHORT ActiveStatePMControl:2; + USHORT Rsvd1:1; + USHORT ReadCompletionBoundary:1; + USHORT LinkDisable:1; + USHORT RetrainLink:1; + USHORT CommonClockConfig:1; + USHORT ExtendedSynch:1; + USHORT EnableClockPowerManagement:1; + USHORT Rsvd2:7; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_LINK_CONTROL_REGISTER, *PPCI_EXPRESS_LINK_CONTROL_REGISTER; + +typedef union _PCI_EXPRESS_LINK_STATUS_REGISTER { + struct { + USHORT LinkSpeed:4; + USHORT LinkWidth:6; + USHORT Undefined:1; + USHORT LinkTraining:1; + USHORT SlotClockConfig:1; + USHORT DataLinkLayerActive:1; + USHORT Rsvd:2; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_LINK_STATUS_REGISTER, *PPCI_EXPRESS_LINK_STATUS_REGISTER; + +typedef union _PCI_EXPRESS_SLOT_CAPABILITIES_REGISTER { + struct { + ULONG AttentionButtonPresent:1; + ULONG PowerControllerPresent:1; + ULONG MRLSensorPresent:1; + ULONG AttentionIndicatorPresent:1; + ULONG PowerIndicatorPresent:1; + ULONG HotPlugSurprise:1; + ULONG HotPlugCapable:1; + ULONG SlotPowerLimit:8; + ULONG SlotPowerLimitScale:2; + ULONG ElectromechanicalLockPresent:1; + ULONG NoCommandCompletedSupport:1; + ULONG PhysicalSlotNumber:13; + } DUMMYSTRUCTNAME; + ULONG AsULONG; +} PCI_EXPRESS_SLOT_CAPABILITIES_REGISTER, *PPCI_EXPRESS_SLOT_CAPABILITIES_REGISTER; + +typedef union _PCI_EXPRESS_SLOT_CONTROL_REGISTER { + struct { + USHORT AttentionButtonEnable:1; + USHORT PowerFaultDetectEnable:1; + USHORT MRLSensorEnable:1; + USHORT PresenceDetectEnable:1; + USHORT CommandCompletedEnable:1; + USHORT HotPlugInterruptEnable:1; + USHORT AttentionIndicatorControl:2; + USHORT PowerIndicatorControl:2; + USHORT PowerControllerControl:1; + USHORT ElectromechanicalLockControl:1; + USHORT DataLinkStateChangeEnable:1; + USHORT Rsvd:3; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_SLOT_CONTROL_REGISTER, *PPCI_EXPRESS_SLOT_CONTROL_REGISTER; typedef enum _HAL_QUERY_INFORMATION_CLASS { HalInstalledBusInformation,

14 years, 5 months

[tkreuzer] 47554: Revert r47553 because testbot doesn't like it

by tkreuzer＠svn.reactos.org

Author: tkreuzer Date: Fri Jun 4 00:15:54 2010 New Revision: 47554 URL: http://svn.reactos.org/svn/reactos?rev=47554&view=rev Log: Revert r47553 because testbot doesn't like it Modified: trunk/reactos/include/ddk/ntddk.h Modified: trunk/reactos/include/ddk/ntddk.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/ddk/ntddk.h?rev=47… ============================================================================== --- trunk/reactos/include/ddk/ntddk.h [iso-8859-1] (original) +++ trunk/reactos/include/ddk/ntddk.h [iso-8859-1] Fri Jun 4 00:15:54 2010 @@ -322,718 +322,6 @@ ULONG Flags; } ARBITER_INTERFACE, *PARBITER_INTERFACE; -typedef enum _RESOURCE_TRANSLATION_DIRECTION { - TranslateChildToParent, - TranslateParentToChild -} RESOURCE_TRANSLATION_DIRECTION; - -typedef NTSTATUS -(NTAPI *PTRANSLATE_RESOURCE_HANDLER)( - IN OUT PVOID Context OPTIONAL, - IN PCM_PARTIAL_RESOURCE_DESCRIPTOR Source, - IN RESOURCE_TRANSLATION_DIRECTION Direction, - IN ULONG AlternativesCount OPTIONAL, - IN IO_RESOURCE_DESCRIPTOR Alternatives[], - IN PDEVICE_OBJECT PhysicalDeviceObject, - OUT PCM_PARTIAL_RESOURCE_DESCRIPTOR Target); - -typedef NTSTATUS -(NTAPI *PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER)( - IN OUT PVOID Context OPTIONAL, - IN PIO_RESOURCE_DESCRIPTOR Source, - IN PDEVICE_OBJECT PhysicalDeviceObject, - OUT PULONG TargetCount, - OUT PIO_RESOURCE_DESCRIPTOR *Target); - -typedef struct _TRANSLATOR_INTERFACE { - USHORT Size; - USHORT Version; - PVOID Context; - PINTERFACE_REFERENCE InterfaceReference; - PINTERFACE_DEREFERENCE InterfaceDereference; - PTRANSLATE_RESOURCE_HANDLER TranslateResources; - PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER TranslateResourceRequirements; -} TRANSLATOR_INTERFACE, *PTRANSLATOR_INTERFACE; - -typedef struct _PCI_AGP_CAPABILITY { - PCI_CAPABILITIES_HEADER Header; - USHORT Minor:4; - USHORT Major:4; - USHORT Rsvd1:8; - struct _PCI_AGP_STATUS { - ULONG Rate:3; - ULONG Agp3Mode:1; - ULONG FastWrite:1; - ULONG FourGB:1; - ULONG HostTransDisable:1; - ULONG Gart64:1; - ULONG ITA_Coherent:1; - ULONG SideBandAddressing:1; - ULONG CalibrationCycle:3; - ULONG AsyncRequestSize:3; - ULONG Rsvd1:1; - ULONG Isoch:1; - ULONG Rsvd2:6; - ULONG RequestQueueDepthMaximum:8; - } AGPStatus; - struct _PCI_AGP_COMMAND { - ULONG Rate:3; - ULONG Rsvd1:1; - ULONG FastWriteEnable:1; - ULONG FourGBEnable:1; - ULONG Rsvd2:1; - ULONG Gart64:1; - ULONG AGPEnable:1; - ULONG SBAEnable:1; - ULONG CalibrationCycle:3; - ULONG AsyncReqSize:3; - ULONG Rsvd3:8; - ULONG RequestQueueDepth:8; - } AGPCommand; -} PCI_AGP_CAPABILITY, *PPCI_AGP_CAPABILITY; - -typedef enum _EXTENDED_AGP_REGISTER { - IsochStatus, - AgpControl, - ApertureSize, - AperturePageSize, - GartLow, - GartHigh, - IsochCommand -} EXTENDED_AGP_REGISTER, *PEXTENDED_AGP_REGISTER; - -typedef struct _PCI_AGP_ISOCH_STATUS { - ULONG ErrorCode:2; - ULONG Rsvd1:1; - ULONG Isoch_L:3; - ULONG Isoch_Y:2; - ULONG Isoch_N:8; - ULONG Rsvd2:16; -} PCI_AGP_ISOCH_STATUS, *PPCI_AGP_ISOCH_STATUS; - -typedef struct _PCI_AGP_CONTROL { - ULONG Rsvd1:7; - ULONG GTLB_Enable:1; - ULONG AP_Enable:1; - ULONG CAL_Disable:1; - ULONG Rsvd2:22; -} PCI_AGP_CONTROL, *PPCI_AGP_CONTROL; - -typedef struct _PCI_AGP_APERTURE_PAGE_SIZE { - USHORT PageSizeMask:11; - USHORT Rsvd1:1; - USHORT PageSizeSelect:4; -} PCI_AGP_APERTURE_PAGE_SIZE, *PPCI_AGP_APERTURE_PAGE_SIZE; - -typedef struct _PCI_AGP_ISOCH_COMMAND { - USHORT Rsvd1:6; - USHORT Isoch_Y:2; - USHORT Isoch_N:8; -} PCI_AGP_ISOCH_COMMAND, *PPCI_AGP_ISOCH_COMMAND; - -typedef struct PCI_AGP_EXTENDED_CAPABILITY { - PCI_AGP_ISOCH_STATUS IsochStatus; - PCI_AGP_CONTROL AgpControl; - USHORT ApertureSize; - PCI_AGP_APERTURE_PAGE_SIZE AperturePageSize; - ULONG GartLow; - ULONG GartHigh; - PCI_AGP_ISOCH_COMMAND IsochCommand; -} PCI_AGP_EXTENDED_CAPABILITY, *PPCI_AGP_EXTENDED_CAPABILITY; - -#define PCI_AGP_RATE_1X 0x1 -#define PCI_AGP_RATE_2X 0x2 -#define PCI_AGP_RATE_4X 0x4 - -#define PCIX_MODE_CONVENTIONAL_PCI 0x0 -#define PCIX_MODE1_66MHZ 0x1 -#define PCIX_MODE1_100MHZ 0x2 -#define PCIX_MODE1_133MHZ 0x3 -#define PCIX_MODE2_266_66MHZ 0x9 -#define PCIX_MODE2_266_100MHZ 0xA -#define PCIX_MODE2_266_133MHZ 0xB -#define PCIX_MODE2_533_66MHZ 0xD -#define PCIX_MODE2_533_100MHZ 0xE -#define PCIX_MODE2_533_133MHZ 0xF - -#define PCIX_VERSION_MODE1_ONLY 0x0 -#define PCIX_VERSION_MODE2_ECC 0x1 -#define PCIX_VERSION_DUAL_MODE_ECC 0x2 - -typedef struct _PCIX_BRIDGE_CAPABILITY { - PCI_CAPABILITIES_HEADER Header; - union { - struct { - USHORT Bus64Bit:1; - USHORT Bus133MHzCapable:1; - USHORT SplitCompletionDiscarded:1; - USHORT UnexpectedSplitCompletion:1; - USHORT SplitCompletionOverrun:1; - USHORT SplitRequestDelayed:1; - USHORT BusModeFrequency:4; - USHORT Rsvd:2; - USHORT Version:2; - USHORT Bus266MHzCapable:1; - USHORT Bus533MHzCapable:1; - } DUMMYSTRUCTNAME; - USHORT AsUSHORT; - } SecondaryStatus; - union { - struct { - ULONG FunctionNumber:3; - ULONG DeviceNumber:5; - ULONG BusNumber:8; - ULONG Device64Bit:1; - ULONG Device133MHzCapable:1; - ULONG SplitCompletionDiscarded:1; - ULONG UnexpectedSplitCompletion:1; - ULONG SplitCompletionOverrun:1; - ULONG SplitRequestDelayed:1; - ULONG Rsvd:7; - ULONG DIMCapable:1; - ULONG Device266MHzCapable:1; - ULONG Device533MHzCapable:1; - } DUMMYSTRUCTNAME; - ULONG AsULONG; - } BridgeStatus; - USHORT UpstreamSplitTransactionCapacity; - USHORT UpstreamSplitTransactionLimit; - USHORT DownstreamSplitTransactionCapacity; - USHORT DownstreamSplitTransactionLimit; - union { - struct { - ULONG SelectSecondaryRegisters:1; - ULONG ErrorPresentInOtherBank:1; - ULONG AdditionalCorrectableError:1; - ULONG AdditionalUncorrectableError:1; - ULONG ErrorPhase:3; - ULONG ErrorCorrected:1; - ULONG Syndrome:8; - ULONG ErrorFirstCommand:4; - ULONG ErrorSecondCommand:4; - ULONG ErrorUpperAttributes:4; - ULONG ControlUpdateEnable:1; - ULONG Rsvd:1; - ULONG DisableSingleBitCorrection:1; - ULONG EccMode:1; - } DUMMYSTRUCTNAME; - ULONG AsULONG; - } EccControlStatus; - ULONG EccFirstAddress; - ULONG EccSecondAddress; - ULONG EccAttribute; -} PCIX_BRIDGE_CAPABILITY, *PPCIX_BRIDGE_CAPABILITY; - -typedef struct _PCI_SUBSYSTEM_IDS_CAPABILITY { - PCI_CAPABILITIES_HEADER Header; - USHORT Reserved; - USHORT SubVendorID; - USHORT SubSystemID; -} PCI_SUBSYSTEM_IDS_CAPABILITY, *PPCI_SUBSYSTEM_IDS_CAPABILITY; - -#define OSC_FIRMWARE_FAILURE 0x02 -#define OSC_UNRECOGNIZED_UUID 0x04 -#define OSC_UNRECOGNIZED_REVISION 0x08 -#define OSC_CAPABILITIES_MASKED 0x10 - -#define PCI_ROOT_BUS_OSC_METHOD_CAPABILITY_REVISION 0x01 - -typedef struct _PCI_ROOT_BUS_OSC_SUPPORT_FIELD { - union { - struct { - ULONG ExtendedConfigOpRegions:1; - ULONG ActiveStatePowerManagement:1; - ULONG ClockPowerManagement:1; - ULONG SegmentGroups:1; - ULONG MessageSignaledInterrupts:1; - ULONG WindowsHardwareErrorArchitecture:1; - ULONG Reserved:26; - } DUMMYSTRUCTNAME; - ULONG AsULONG; - } u; -} PCI_ROOT_BUS_OSC_SUPPORT_FIELD, *PPCI_ROOT_BUS_OSC_SUPPORT_FIELD; - -typedef struct _PCI_ROOT_BUS_OSC_CONTROL_FIELD { - union { - struct { - ULONG ExpressNativeHotPlug:1; - ULONG ShpcNativeHotPlug:1; - ULONG ExpressNativePME:1; - ULONG ExpressAdvancedErrorReporting:1; - ULONG ExpressCapabilityStructure:1; - ULONG Reserved:27; - } DUMMYSTRUCTNAME; - ULONG AsULONG; - } u; -} PCI_ROOT_BUS_OSC_CONTROL_FIELD, *PPCI_ROOT_BUS_OSC_CONTROL_FIELD; - -typedef enum _PCI_HARDWARE_INTERFACE { - PciConventional, - PciXMode1, - PciXMode2, - PciExpress -} PCI_HARDWARE_INTERFACE, *PPCI_HARDWARE_INTERFACE; - -typedef enum { - BusWidth32Bits, - BusWidth64Bits -} PCI_BUS_WIDTH; - -typedef struct _PCI_ROOT_BUS_HARDWARE_CAPABILITY { - PCI_HARDWARE_INTERFACE SecondaryInterface; - struct { - BOOLEAN BusCapabilitiesFound; - ULONG CurrentSpeedAndMode; - ULONG SupportedSpeedsAndModes; - BOOLEAN DeviceIDMessagingCapable; - PCI_BUS_WIDTH SecondaryBusWidth; - } DUMMYSTRUCTNAME; - PCI_ROOT_BUS_OSC_SUPPORT_FIELD OscFeatureSupport; - PCI_ROOT_BUS_OSC_CONTROL_FIELD OscControlRequest; - PCI_ROOT_BUS_OSC_CONTROL_FIELD OscControlGranted; -} PCI_ROOT_BUS_HARDWARE_CAPABILITY, *PPCI_ROOT_BUS_HARDWARE_CAPABILITY; - -typedef union _PCI_EXPRESS_CAPABILITIES_REGISTER { - struct { - USHORT CapabilityVersion:4; - USHORT DeviceType:4; - USHORT SlotImplemented:1; - USHORT InterruptMessageNumber:5; - USHORT Rsvd:2; - } DUMMYSTRUCTNAME; - USHORT AsUSHORT; -} PCI_EXPRESS_CAPABILITIES_REGISTER, *PPCI_EXPRESS_CAPABILITIES_REGISTER; - -typedef union _PCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER { - struct { - ULONG MaxPayloadSizeSupported:3; - ULONG PhantomFunctionsSupported:2; - ULONG ExtendedTagSupported:1; - ULONG L0sAcceptableLatency:3; - ULONG L1AcceptableLatency:3; - ULONG Undefined:3; - ULONG RoleBasedErrorReporting:1; - ULONG Rsvd1:2; - ULONG CapturedSlotPowerLimit:8; - ULONG CapturedSlotPowerLimitScale:2; - ULONG Rsvd2:4; - } DUMMYSTRUCTNAME; - ULONG AsULONG; -} PCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER, *PPCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER; - -#define PCI_EXPRESS_AER_DEVICE_CONTROL_MASK 0x07; - -typedef union _PCI_EXPRESS_DEVICE_CONTROL_REGISTER { - struct { - USHORT CorrectableErrorEnable:1; - USHORT NonFatalErrorEnable:1; - USHORT FatalErrorEnable:1; - USHORT UnsupportedRequestErrorEnable:1; - USHORT EnableRelaxedOrder:1; - USHORT MaxPayloadSize:3; - USHORT ExtendedTagEnable:1; - USHORT PhantomFunctionsEnable:1; - USHORT AuxPowerEnable:1; - USHORT NoSnoopEnable:1; - USHORT MaxReadRequestSize:3; - USHORT BridgeConfigRetryEnable:1; - } DUMMYSTRUCTNAME; - USHORT AsUSHORT; -} PCI_EXPRESS_DEVICE_CONTROL_REGISTER, *PPCI_EXPRESS_DEVICE_CONTROL_REGISTER; - -#define PCI_EXPRESS_AER_DEVICE_STATUS_MASK 0x0F; - -typedef union _PCI_EXPRESS_DEVICE_STATUS_REGISTER { - struct { - USHORT CorrectableErrorDetected:1; - USHORT NonFatalErrorDetected:1; - USHORT FatalErrorDetected:1; - USHORT UnsupportedRequestDetected:1; - USHORT AuxPowerDetected:1; - USHORT TransactionsPending:1; - USHORT Rsvd:10; - } DUMMYSTRUCTNAME; - USHORT AsUSHORT; -} PCI_EXPRESS_DEVICE_STATUS_REGISTER, *PPCI_EXPRESS_DEVICE_STATUS_REGISTER; - -typedef union _PCI_EXPRESS_LINK_CAPABILITIES_REGISTER { - struct { - ULONG MaximumLinkSpeed:4; - ULONG MaximumLinkWidth:6; - ULONG ActiveStatePMSupport:2; - ULONG L0sExitLatency:3; - ULONG L1ExitLatency:3; - ULONG ClockPowerManagement:1; - ULONG SurpriseDownErrorReportingCapable:1; - ULONG DataLinkLayerActiveReportingCapable:1; - ULONG Rsvd:3; - ULONG PortNumber:8; - } DUMMYSTRUCTNAME; - ULONG AsULONG; -} PCI_EXPRESS_LINK_CAPABILITIES_REGISTER, *PPCI_EXPRESS_LINK_CAPABILITIES_REGISTER; - -typedef union _PCI_EXPRESS_LINK_CONTROL_REGISTER { - struct { - USHORT ActiveStatePMControl:2; - USHORT Rsvd1:1; - USHORT ReadCompletionBoundary:1; - USHORT LinkDisable:1; - USHORT RetrainLink:1; - USHORT CommonClockConfig:1; - USHORT ExtendedSynch:1; - USHORT EnableClockPowerManagement:1; - USHORT Rsvd2:7; - } DUMMYSTRUCTNAME; - USHORT AsUSHORT; -} PCI_EXPRESS_LINK_CONTROL_REGISTER, *PPCI_EXPRESS_LINK_CONTROL_REGISTER; - -typedef union _PCI_EXPRESS_LINK_STATUS_REGISTER { - struct { - USHORT LinkSpeed:4; - USHORT LinkWidth:6; - USHORT Undefined:1; - USHORT LinkTraining:1; - USHORT SlotClockConfig:1; - USHORT DataLinkLayerActive:1; - USHORT Rsvd:2; - } DUMMYSTRUCTNAME; - USHORT AsUSHORT; -} PCI_EXPRESS_LINK_STATUS_REGISTER, *PPCI_EXPRESS_LINK_STATUS_REGISTER; - -typedef union _PCI_EXPRESS_SLOT_CAPABILITIES_REGISTER { - struct { - ULONG AttentionButtonPresent:1; - ULONG PowerControllerPresent:1; - ULONG MRLSensorPresent:1; - ULONG AttentionIndicatorPresent:1; - ULONG PowerIndicatorPresent:1; - ULONG HotPlugSurprise:1; - ULONG HotPlugCapable:1; - ULONG SlotPowerLimit:8; - ULONG SlotPowerLimitScale:2; - ULONG ElectromechanicalLockPresent:1; - ULONG NoCommandCompletedSupport:1; - ULONG PhysicalSlotNumber:13; - } DUMMYSTRUCTNAME; - ULONG AsULONG; -} PCI_EXPRESS_SLOT_CAPABILITIES_REGISTER, *PPCI_EXPRESS_SLOT_CAPABILITIES_REGISTER; - -typedef union _PCI_EXPRESS_SLOT_CONTROL_REGISTER { - struct { - USHORT AttentionButtonEnable:1; - USHORT PowerFaultDetectEnable:1; - USHORT MRLSensorEnable:1; - USHORT PresenceDetectEnable:1; - USHORT CommandCompletedEnable:1; - USHORT HotPlugInterruptEnable:1; - USHORT AttentionIndicatorControl:2; - USHORT PowerIndicatorControl:2; - USHORT PowerControllerControl:1; - USHORT ElectromechanicalLockControl:1; - USHORT DataLinkStateChangeEnable:1; - USHORT Rsvd:3; - } DUMMYSTRUCTNAME; - USHORT AsUSHORT; -} PCI_EXPRESS_SLOT_CONTROL_REGISTER, *PPCI_EXPRESS_SLOT_CONTROL_REGISTER; - -typedef union _PCI_EXPRESS_SLOT_STATUS_REGISTER { - struct { - USHORT AttentionButtonPressed:1; - USHORT PowerFaultDetected:1; - USHORT MRLSensorChanged:1; - USHORT PresenceDetectChanged:1; - USHORT CommandCompleted:1; - USHORT MRLSensorState:1; - USHORT PresenceDetectState:1; - USHORT ElectromechanicalLockEngaged:1; - USHORT DataLinkStateChanged:1; - USHORT Rsvd:7; - } DUMMYSTRUCTNAME; - USHORT AsUSHORT; -} PCI_EXPRESS_SLOT_STATUS_REGISTER, *PPCI_EXPRESS_SLOT_STATUS_REGISTER; - -typedef union _PCI_EXPRESS_ROOT_CONTROL_REGISTER { - struct { - USHORT CorrectableSerrEnable:1; - USHORT NonFatalSerrEnable:1; - USHORT FatalSerrEnable:1; - USHORT PMEInterruptEnable:1; - USHORT CRSSoftwareVisibilityEnable:1; - USHORT Rsvd:11; - } DUMMYSTRUCTNAME; - USHORT AsUSHORT; -} PCI_EXPRESS_ROOT_CONTROL_REGISTER, *PPCI_EXPRESS_ROOT_CONTROL_REGISTER; - -typedef union _PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER { - struct { - USHORT CRSSoftwareVisibility:1; - USHORT Rsvd:15; - } DUMMYSTRUCTNAME; - USHORT AsUSHORT; -} PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER, *PPCI_EXPRESS_ROOT_CAPABILITIES_REGISTER; - -typedef union _PCI_EXPRESS_ROOT_STATUS_REGISTER { - struct { - ULONG PMERequestorId:16; - ULONG PMEStatus:1; - ULONG PMEPending:1; - ULONG Rsvd:14; - } DUMMYSTRUCTNAME; - ULONG AsULONG; -} PCI_EXPRESS_ROOT_STATUS_REGISTER, *PPCI_EXPRESS_ROOT_STATUS_REGISTER; - -typedef struct _PCI_EXPRESS_CAPABILITY { - PCI_CAPABILITIES_HEADER Header; - PCI_EXPRESS_CAPABILITIES_REGISTER ExpressCapabilities; - PCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER DeviceCapabilities; - PCI_EXPRESS_DEVICE_CONTROL_REGISTER DeviceControl; - PCI_EXPRESS_DEVICE_STATUS_REGISTER DeviceStatus; - PCI_EXPRESS_LINK_CAPABILITIES_REGISTER LinkCapabilities; - PCI_EXPRESS_LINK_CONTROL_REGISTER LinkControl; - PCI_EXPRESS_LINK_STATUS_REGISTER LinkStatus; - PCI_EXPRESS_SLOT_CAPABILITIES_REGISTER SlotCapabilities; - PCI_EXPRESS_SLOT_CONTROL_REGISTER SlotControl; - PCI_EXPRESS_SLOT_STATUS_REGISTER SlotStatus; - PCI_EXPRESS_ROOT_CONTROL_REGISTER RootControl; - PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER RootCapabilities; - PCI_EXPRESS_ROOT_STATUS_REGISTER RootStatus; -} PCI_EXPRESS_CAPABILITY, *PPCI_EXPRESS_CAPABILITY; - -typedef enum { - MRLClosed = 0, - MRLOpen -} PCI_EXPRESS_MRL_STATE; - -typedef enum { - SlotEmpty = 0, - CardPresent -} PCI_EXPRESS_CARD_PRESENCE; - -typedef enum { - IndicatorOn = 1, - IndicatorBlink, - IndicatorOff -} PCI_EXPRESS_INDICATOR_STATE; - -typedef enum { - PowerOn = 0, - PowerOff -} PCI_EXPRESS_POWER_STATE; - -typedef enum { - L0sEntrySupport = 1, - L0sAndL1EntrySupport = 3 -} PCI_EXPRESS_ASPM_SUPPORT; - -typedef enum { - L0sAndL1EntryDisabled, - L0sEntryEnabled, - L1EntryEnabled, - L0sAndL1EntryEnabled -} PCI_EXPRESS_ASPM_CONTROL; - -typedef enum { - L0s_Below64ns = 0, - L0s_64ns_128ns, - L0s_128ns_256ns, - L0s_256ns_512ns, - L0s_512ns_1us, - L0s_1us_2us, - L0s_2us_4us, - L0s_Above4us -} PCI_EXPRESS_L0s_EXIT_LATENCY; - -typedef enum { - L1_Below1us = 0, - L1_1us_2us, - L1_2us_4us, - L1_4us_8us, - L1_8us_16us, - L1_16us_32us, - L1_32us_64us, - L1_Above64us -} PCI_EXPRESS_L1_EXIT_LATENCY; - -typedef enum { - PciExpressEndpoint = 0, - PciExpressLegacyEndpoint, - PciExpressRootPort = 4, - PciExpressUpstreamSwitchPort, - PciExpressDownstreamSwitchPort, - PciExpressToPciXBridge, - PciXToExpressBridge, - PciExpressRootComplexIntegratedEndpoint, - PciExpressRootComplexEventCollector -} PCI_EXPRESS_DEVICE_TYPE; - -typedef enum { - MaxPayload128Bytes = 0, - MaxPayload256Bytes, - MaxPayload512Bytes, - MaxPayload1024Bytes, - MaxPayload2048Bytes, - MaxPayload4096Bytes -} PCI_EXPRESS_MAX_PAYLOAD_SIZE; - -typedef union _PCI_EXPRESS_PME_REQUESTOR_ID { - struct { - USHORT FunctionNumber:3; - USHORT DeviceNumber:5; - USHORT BusNumber:8; - } DUMMYSTRUCTNAME; - USHORT AsUSHORT; -} PCI_EXPRESS_PME_REQUESTOR_ID, *PPCI_EXPRESS_PME_REQUESTOR_ID; - -#if defined(_WIN64) - -#ifndef USE_DMA_MACROS -#define USE_DMA_MACROS -#endif - -#ifndef NO_LEGACY_DRIVERS -#define NO_LEGACY_DRIVERS -#endif - -#endif /* defined(_WIN64) */ - -typedef enum _PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE { - ResourceTypeSingle = 0, - ResourceTypeRange, - ResourceTypeExtendedCounterConfiguration, - ResourceTypeOverflow, - ResourceTypeMax -} PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE; - -typedef struct _PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR { - PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE Type; - ULONG Flags; - union { - ULONG CounterIndex; - ULONG ExtendedRegisterAddress; - struct { - ULONG Begin; - ULONG End; - } Range; - } u; -} PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR, *PPHYSICAL_COUNTER_RESOURCE_DESCRIPTOR; - -typedef struct _PHYSICAL_COUNTER_RESOURCE_LIST { - ULONG Count; - PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR Descriptors[ANYSIZE_ARRAY]; -} PHYSICAL_COUNTER_RESOURCE_LIST, *PPHYSICAL_COUNTER_RESOURCE_LIST; - -typedef VOID -(NTAPI *PciPin2Line)( - IN struct _BUS_HANDLER *BusHandler, - IN struct _BUS_HANDLER *RootHandler, - IN PCI_SLOT_NUMBER SlotNumber, - IN PPCI_COMMON_CONFIG PciData); - -typedef VOID -(NTAPI *PciLine2Pin)( - IN struct _BUS_HANDLER *BusHandler, - IN struct _BUS_HANDLER *RootHandler, - IN PCI_SLOT_NUMBER SlotNumber, - IN PPCI_COMMON_CONFIG PciNewData, - IN PPCI_COMMON_CONFIG PciOldData); - -typedef VOID -(NTAPI *PciReadWriteConfig)( - IN struct _BUS_HANDLER *BusHandler, - IN PCI_SLOT_NUMBER Slot, - IN PVOID Buffer, - IN ULONG Offset, - IN ULONG Length); - -#define PCI_DATA_TAG ' ICP' -#define PCI_DATA_VERSION 1 - -typedef struct _PCIBUSDATA { - ULONG Tag; - ULONG Version; - PciReadWriteConfig ReadConfig; - PciReadWriteConfig WriteConfig; - PciPin2Line Pin2Line; - PciLine2Pin Line2Pin; - PCI_SLOT_NUMBER ParentSlot; - PVOID Reserved[4]; -} PCIBUSDATA, *PPCIBUSDATA; - -#ifndef _PCIINTRF_X_ -#define _PCIINTRF_X_ - -typedef ULONG -(NTAPI *PCI_READ_WRITE_CONFIG)( - IN PVOID Context, - IN ULONG BusOffset, - IN ULONG Slot, - IN PVOID Buffer, - IN ULONG Offset, - IN ULONG Length); - -typedef VOID -(NTAPI *PCI_PIN_TO_LINE)( - IN PVOID Context, - IN PPCI_COMMON_CONFIG PciData); - -typedef VOID -(NTAPI *PCI_LINE_TO_PIN)( - IN PVOID Context, - IN PPCI_COMMON_CONFIG PciNewData, - IN PPCI_COMMON_CONFIG PciOldData); - -typedef VOID -(NTAPI *PCI_ROOT_BUS_CAPABILITY)( - IN PVOID Context, - OUT PPCI_ROOT_BUS_HARDWARE_CAPABILITY HardwareCapability); - -typedef VOID -(NTAPI *PCI_EXPRESS_WAKE_CONTROL)( - IN PVOID Context, - IN BOOLEAN EnableWake); - -typedef struct _PCI_BUS_INTERFACE_STANDARD { - USHORT Size; - USHORT Version; - PVOID Context; - PINTERFACE_REFERENCE InterfaceReference; - PINTERFACE_DEREFERENCE InterfaceDereference; - PCI_READ_WRITE_CONFIG ReadConfig; - PCI_READ_WRITE_CONFIG WriteConfig; - PCI_PIN_TO_LINE PinToLine; - PCI_LINE_TO_PIN LineToPin; - PCI_ROOT_BUS_CAPABILITY RootBusCapability; - PCI_EXPRESS_WAKE_CONTROL ExpressWakeControl; -} PCI_BUS_INTERFACE_STANDARD, *PPCI_BUS_INTERFACE_STANDARD; - -#define PCI_BUS_INTERFACE_STANDARD_VERSION 1 - -#endif /* _PCIINTRF_X_ */ - -#if (NTDDI_VERSION >= NTDDI_WIN7) - -#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX 0x00004000 -#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX 0x00008000 -#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_EX \ - (FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX | \ - FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX) - -#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_DEPRECATED 0x00000200 -#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_DEPRECATED 0x00000300 -#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_DEPRECATED 0x00000300 - -#else - -#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL 0x00000200 -#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL 0x00000300 -#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK 0x00000300 - -#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL -#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL -#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_EX FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK - -#endif /* (NTDDI_VERSION >= NTDDI_WIN7) */ - typedef enum _HAL_QUERY_INFORMATION_CLASS { HalInstalledBusInformation, HalProfileSourceInformation, @@ -1133,6 +421,39 @@ ULONG Version; PVOID Function[1]; } PM_DISPATCH_TABLE, *PPM_DISPATCH_TABLE; + +typedef enum _RESOURCE_TRANSLATION_DIRECTION { + TranslateChildToParent, + TranslateParentToChild +} RESOURCE_TRANSLATION_DIRECTION; + +typedef NTSTATUS +(NTAPI *PTRANSLATE_RESOURCE_HANDLER)( + IN OUT PVOID Context, + IN PCM_PARTIAL_RESOURCE_DESCRIPTOR Source, + IN RESOURCE_TRANSLATION_DIRECTION Direction, + IN ULONG AlternativesCount OPTIONAL, + IN IO_RESOURCE_DESCRIPTOR Alternatives[], + IN PDEVICE_OBJECT PhysicalDeviceObject, + OUT PCM_PARTIAL_RESOURCE_DESCRIPTOR Target); + +typedef NTSTATUS +(NTAPI *PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER)( + IN PVOID Context OPTIONAL, + IN PIO_RESOURCE_DESCRIPTOR Source, + IN PDEVICE_OBJECT PhysicalDeviceObject, + OUT PULONG TargetCount, + OUT PIO_RESOURCE_DESCRIPTOR *Target); + +typedef struct _TRANSLATOR_INTERFACE { + USHORT Size; + USHORT Version; + PVOID Context; + PINTERFACE_REFERENCE InterfaceReference; + PINTERFACE_DEREFERENCE InterfaceDereference; + PTRANSLATE_RESOURCE_HANDLER TranslateResources; + PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER TranslateResourceRequirements; +} TRANSLATOR_INTERFACE, *PTRANSLATOR_INTERFACE; typedef VOID (FASTCALL *pHalExamineMBR)( @@ -2546,10 +1867,42 @@ /* Hardware Abstraction Layer Types */ - - - - +typedef VOID +(NTAPI *PciPin2Line)( + IN struct _BUS_HANDLER *BusHandler, + IN struct _BUS_HANDLER *RootHandler, + IN PCI_SLOT_NUMBER SlotNumber, + IN PPCI_COMMON_CONFIG PciData); + +typedef VOID +(NTAPI *PciLine2Pin)( + IN struct _BUS_HANDLER *BusHandler, + IN struct _BUS_HANDLER *RootHandler, + IN PCI_SLOT_NUMBER SlotNumber, + IN PPCI_COMMON_CONFIG PciNewData, + IN PPCI_COMMON_CONFIG PciOldData); + +typedef VOID +(NTAPI *PciReadWriteConfig)( + IN struct _BUS_HANDLER *BusHandler, + IN PCI_SLOT_NUMBER Slot, + IN PVOID Buffer, + IN ULONG Offset, + IN ULONG Length); + +#define PCI_DATA_TAG ' ICP' +#define PCI_DATA_VERSION 1 + +typedef struct _PCIBUSDATA { + ULONG Tag; + ULONG Version; + PciReadWriteConfig ReadConfig; + PciReadWriteConfig WriteConfig; + PciPin2Line Pin2Line; + PciLine2Pin Line2Pin; + PCI_SLOT_NUMBER ParentSlot; + PVOID Reserved[4]; +} PCIBUSDATA, *PPCIBUSDATA; /* Hardware Abstraction Layer Functions */

14 years, 5 months

[tkreuzer] 47553: [DDK} Add a number of PCI related types to ntddk.h

by tkreuzer＠svn.reactos.org

Author: tkreuzer Date: Thu Jun 3 23:55:57 2010 New Revision: 47553 URL: http://svn.reactos.org/svn/reactos?rev=47553&view=rev Log: [DDK} Add a number of PCI related types to ntddk.h Modified: trunk/reactos/include/ddk/ntddk.h Modified: trunk/reactos/include/ddk/ntddk.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/ddk/ntddk.h?rev=47… ============================================================================== --- trunk/reactos/include/ddk/ntddk.h [iso-8859-1] (original) +++ trunk/reactos/include/ddk/ntddk.h [iso-8859-1] Thu Jun 3 23:55:57 2010 @@ -322,6 +322,718 @@ ULONG Flags; } ARBITER_INTERFACE, *PARBITER_INTERFACE; +typedef enum _RESOURCE_TRANSLATION_DIRECTION { + TranslateChildToParent, + TranslateParentToChild +} RESOURCE_TRANSLATION_DIRECTION; + +typedef NTSTATUS +(NTAPI *PTRANSLATE_RESOURCE_HANDLER)( + IN OUT PVOID Context OPTIONAL, + IN PCM_PARTIAL_RESOURCE_DESCRIPTOR Source, + IN RESOURCE_TRANSLATION_DIRECTION Direction, + IN ULONG AlternativesCount OPTIONAL, + IN IO_RESOURCE_DESCRIPTOR Alternatives[], + IN PDEVICE_OBJECT PhysicalDeviceObject, + OUT PCM_PARTIAL_RESOURCE_DESCRIPTOR Target); + +typedef NTSTATUS +(NTAPI *PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER)( + IN OUT PVOID Context OPTIONAL, + IN PIO_RESOURCE_DESCRIPTOR Source, + IN PDEVICE_OBJECT PhysicalDeviceObject, + OUT PULONG TargetCount, + OUT PIO_RESOURCE_DESCRIPTOR *Target); + +typedef struct _TRANSLATOR_INTERFACE { + USHORT Size; + USHORT Version; + PVOID Context; + PINTERFACE_REFERENCE InterfaceReference; + PINTERFACE_DEREFERENCE InterfaceDereference; + PTRANSLATE_RESOURCE_HANDLER TranslateResources; + PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER TranslateResourceRequirements; +} TRANSLATOR_INTERFACE, *PTRANSLATOR_INTERFACE; + +typedef struct _PCI_AGP_CAPABILITY { + PCI_CAPABILITIES_HEADER Header; + USHORT Minor:4; + USHORT Major:4; + USHORT Rsvd1:8; + struct _PCI_AGP_STATUS { + ULONG Rate:3; + ULONG Agp3Mode:1; + ULONG FastWrite:1; + ULONG FourGB:1; + ULONG HostTransDisable:1; + ULONG Gart64:1; + ULONG ITA_Coherent:1; + ULONG SideBandAddressing:1; + ULONG CalibrationCycle:3; + ULONG AsyncRequestSize:3; + ULONG Rsvd1:1; + ULONG Isoch:1; + ULONG Rsvd2:6; + ULONG RequestQueueDepthMaximum:8; + } AGPStatus; + struct _PCI_AGP_COMMAND { + ULONG Rate:3; + ULONG Rsvd1:1; + ULONG FastWriteEnable:1; + ULONG FourGBEnable:1; + ULONG Rsvd2:1; + ULONG Gart64:1; + ULONG AGPEnable:1; + ULONG SBAEnable:1; + ULONG CalibrationCycle:3; + ULONG AsyncReqSize:3; + ULONG Rsvd3:8; + ULONG RequestQueueDepth:8; + } AGPCommand; +} PCI_AGP_CAPABILITY, *PPCI_AGP_CAPABILITY; + +typedef enum _EXTENDED_AGP_REGISTER { + IsochStatus, + AgpControl, + ApertureSize, + AperturePageSize, + GartLow, + GartHigh, + IsochCommand +} EXTENDED_AGP_REGISTER, *PEXTENDED_AGP_REGISTER; + +typedef struct _PCI_AGP_ISOCH_STATUS { + ULONG ErrorCode:2; + ULONG Rsvd1:1; + ULONG Isoch_L:3; + ULONG Isoch_Y:2; + ULONG Isoch_N:8; + ULONG Rsvd2:16; +} PCI_AGP_ISOCH_STATUS, *PPCI_AGP_ISOCH_STATUS; + +typedef struct _PCI_AGP_CONTROL { + ULONG Rsvd1:7; + ULONG GTLB_Enable:1; + ULONG AP_Enable:1; + ULONG CAL_Disable:1; + ULONG Rsvd2:22; +} PCI_AGP_CONTROL, *PPCI_AGP_CONTROL; + +typedef struct _PCI_AGP_APERTURE_PAGE_SIZE { + USHORT PageSizeMask:11; + USHORT Rsvd1:1; + USHORT PageSizeSelect:4; +} PCI_AGP_APERTURE_PAGE_SIZE, *PPCI_AGP_APERTURE_PAGE_SIZE; + +typedef struct _PCI_AGP_ISOCH_COMMAND { + USHORT Rsvd1:6; + USHORT Isoch_Y:2; + USHORT Isoch_N:8; +} PCI_AGP_ISOCH_COMMAND, *PPCI_AGP_ISOCH_COMMAND; + +typedef struct PCI_AGP_EXTENDED_CAPABILITY { + PCI_AGP_ISOCH_STATUS IsochStatus; + PCI_AGP_CONTROL AgpControl; + USHORT ApertureSize; + PCI_AGP_APERTURE_PAGE_SIZE AperturePageSize; + ULONG GartLow; + ULONG GartHigh; + PCI_AGP_ISOCH_COMMAND IsochCommand; +} PCI_AGP_EXTENDED_CAPABILITY, *PPCI_AGP_EXTENDED_CAPABILITY; + +#define PCI_AGP_RATE_1X 0x1 +#define PCI_AGP_RATE_2X 0x2 +#define PCI_AGP_RATE_4X 0x4 + +#define PCIX_MODE_CONVENTIONAL_PCI 0x0 +#define PCIX_MODE1_66MHZ 0x1 +#define PCIX_MODE1_100MHZ 0x2 +#define PCIX_MODE1_133MHZ 0x3 +#define PCIX_MODE2_266_66MHZ 0x9 +#define PCIX_MODE2_266_100MHZ 0xA +#define PCIX_MODE2_266_133MHZ 0xB +#define PCIX_MODE2_533_66MHZ 0xD +#define PCIX_MODE2_533_100MHZ 0xE +#define PCIX_MODE2_533_133MHZ 0xF + +#define PCIX_VERSION_MODE1_ONLY 0x0 +#define PCIX_VERSION_MODE2_ECC 0x1 +#define PCIX_VERSION_DUAL_MODE_ECC 0x2 + +typedef struct _PCIX_BRIDGE_CAPABILITY { + PCI_CAPABILITIES_HEADER Header; + union { + struct { + USHORT Bus64Bit:1; + USHORT Bus133MHzCapable:1; + USHORT SplitCompletionDiscarded:1; + USHORT UnexpectedSplitCompletion:1; + USHORT SplitCompletionOverrun:1; + USHORT SplitRequestDelayed:1; + USHORT BusModeFrequency:4; + USHORT Rsvd:2; + USHORT Version:2; + USHORT Bus266MHzCapable:1; + USHORT Bus533MHzCapable:1; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; + } SecondaryStatus; + union { + struct { + ULONG FunctionNumber:3; + ULONG DeviceNumber:5; + ULONG BusNumber:8; + ULONG Device64Bit:1; + ULONG Device133MHzCapable:1; + ULONG SplitCompletionDiscarded:1; + ULONG UnexpectedSplitCompletion:1; + ULONG SplitCompletionOverrun:1; + ULONG SplitRequestDelayed:1; + ULONG Rsvd:7; + ULONG DIMCapable:1; + ULONG Device266MHzCapable:1; + ULONG Device533MHzCapable:1; + } DUMMYSTRUCTNAME; + ULONG AsULONG; + } BridgeStatus; + USHORT UpstreamSplitTransactionCapacity; + USHORT UpstreamSplitTransactionLimit; + USHORT DownstreamSplitTransactionCapacity; + USHORT DownstreamSplitTransactionLimit; + union { + struct { + ULONG SelectSecondaryRegisters:1; + ULONG ErrorPresentInOtherBank:1; + ULONG AdditionalCorrectableError:1; + ULONG AdditionalUncorrectableError:1; + ULONG ErrorPhase:3; + ULONG ErrorCorrected:1; + ULONG Syndrome:8; + ULONG ErrorFirstCommand:4; + ULONG ErrorSecondCommand:4; + ULONG ErrorUpperAttributes:4; + ULONG ControlUpdateEnable:1; + ULONG Rsvd:1; + ULONG DisableSingleBitCorrection:1; + ULONG EccMode:1; + } DUMMYSTRUCTNAME; + ULONG AsULONG; + } EccControlStatus; + ULONG EccFirstAddress; + ULONG EccSecondAddress; + ULONG EccAttribute; +} PCIX_BRIDGE_CAPABILITY, *PPCIX_BRIDGE_CAPABILITY; + +typedef struct _PCI_SUBSYSTEM_IDS_CAPABILITY { + PCI_CAPABILITIES_HEADER Header; + USHORT Reserved; + USHORT SubVendorID; + USHORT SubSystemID; +} PCI_SUBSYSTEM_IDS_CAPABILITY, *PPCI_SUBSYSTEM_IDS_CAPABILITY; + +#define OSC_FIRMWARE_FAILURE 0x02 +#define OSC_UNRECOGNIZED_UUID 0x04 +#define OSC_UNRECOGNIZED_REVISION 0x08 +#define OSC_CAPABILITIES_MASKED 0x10 + +#define PCI_ROOT_BUS_OSC_METHOD_CAPABILITY_REVISION 0x01 + +typedef struct _PCI_ROOT_BUS_OSC_SUPPORT_FIELD { + union { + struct { + ULONG ExtendedConfigOpRegions:1; + ULONG ActiveStatePowerManagement:1; + ULONG ClockPowerManagement:1; + ULONG SegmentGroups:1; + ULONG MessageSignaledInterrupts:1; + ULONG WindowsHardwareErrorArchitecture:1; + ULONG Reserved:26; + } DUMMYSTRUCTNAME; + ULONG AsULONG; + } u; +} PCI_ROOT_BUS_OSC_SUPPORT_FIELD, *PPCI_ROOT_BUS_OSC_SUPPORT_FIELD; + +typedef struct _PCI_ROOT_BUS_OSC_CONTROL_FIELD { + union { + struct { + ULONG ExpressNativeHotPlug:1; + ULONG ShpcNativeHotPlug:1; + ULONG ExpressNativePME:1; + ULONG ExpressAdvancedErrorReporting:1; + ULONG ExpressCapabilityStructure:1; + ULONG Reserved:27; + } DUMMYSTRUCTNAME; + ULONG AsULONG; + } u; +} PCI_ROOT_BUS_OSC_CONTROL_FIELD, *PPCI_ROOT_BUS_OSC_CONTROL_FIELD; + +typedef enum _PCI_HARDWARE_INTERFACE { + PciConventional, + PciXMode1, + PciXMode2, + PciExpress +} PCI_HARDWARE_INTERFACE, *PPCI_HARDWARE_INTERFACE; + +typedef enum { + BusWidth32Bits, + BusWidth64Bits +} PCI_BUS_WIDTH; + +typedef struct _PCI_ROOT_BUS_HARDWARE_CAPABILITY { + PCI_HARDWARE_INTERFACE SecondaryInterface; + struct { + BOOLEAN BusCapabilitiesFound; + ULONG CurrentSpeedAndMode; + ULONG SupportedSpeedsAndModes; + BOOLEAN DeviceIDMessagingCapable; + PCI_BUS_WIDTH SecondaryBusWidth; + } DUMMYSTRUCTNAME; + PCI_ROOT_BUS_OSC_SUPPORT_FIELD OscFeatureSupport; + PCI_ROOT_BUS_OSC_CONTROL_FIELD OscControlRequest; + PCI_ROOT_BUS_OSC_CONTROL_FIELD OscControlGranted; +} PCI_ROOT_BUS_HARDWARE_CAPABILITY, *PPCI_ROOT_BUS_HARDWARE_CAPABILITY; + +typedef union _PCI_EXPRESS_CAPABILITIES_REGISTER { + struct { + USHORT CapabilityVersion:4; + USHORT DeviceType:4; + USHORT SlotImplemented:1; + USHORT InterruptMessageNumber:5; + USHORT Rsvd:2; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_CAPABILITIES_REGISTER, *PPCI_EXPRESS_CAPABILITIES_REGISTER; + +typedef union _PCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER { + struct { + ULONG MaxPayloadSizeSupported:3; + ULONG PhantomFunctionsSupported:2; + ULONG ExtendedTagSupported:1; + ULONG L0sAcceptableLatency:3; + ULONG L1AcceptableLatency:3; + ULONG Undefined:3; + ULONG RoleBasedErrorReporting:1; + ULONG Rsvd1:2; + ULONG CapturedSlotPowerLimit:8; + ULONG CapturedSlotPowerLimitScale:2; + ULONG Rsvd2:4; + } DUMMYSTRUCTNAME; + ULONG AsULONG; +} PCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER, *PPCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER; + +#define PCI_EXPRESS_AER_DEVICE_CONTROL_MASK 0x07; + +typedef union _PCI_EXPRESS_DEVICE_CONTROL_REGISTER { + struct { + USHORT CorrectableErrorEnable:1; + USHORT NonFatalErrorEnable:1; + USHORT FatalErrorEnable:1; + USHORT UnsupportedRequestErrorEnable:1; + USHORT EnableRelaxedOrder:1; + USHORT MaxPayloadSize:3; + USHORT ExtendedTagEnable:1; + USHORT PhantomFunctionsEnable:1; + USHORT AuxPowerEnable:1; + USHORT NoSnoopEnable:1; + USHORT MaxReadRequestSize:3; + USHORT BridgeConfigRetryEnable:1; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_DEVICE_CONTROL_REGISTER, *PPCI_EXPRESS_DEVICE_CONTROL_REGISTER; + +#define PCI_EXPRESS_AER_DEVICE_STATUS_MASK 0x0F; + +typedef union _PCI_EXPRESS_DEVICE_STATUS_REGISTER { + struct { + USHORT CorrectableErrorDetected:1; + USHORT NonFatalErrorDetected:1; + USHORT FatalErrorDetected:1; + USHORT UnsupportedRequestDetected:1; + USHORT AuxPowerDetected:1; + USHORT TransactionsPending:1; + USHORT Rsvd:10; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_DEVICE_STATUS_REGISTER, *PPCI_EXPRESS_DEVICE_STATUS_REGISTER; + +typedef union _PCI_EXPRESS_LINK_CAPABILITIES_REGISTER { + struct { + ULONG MaximumLinkSpeed:4; + ULONG MaximumLinkWidth:6; + ULONG ActiveStatePMSupport:2; + ULONG L0sExitLatency:3; + ULONG L1ExitLatency:3; + ULONG ClockPowerManagement:1; + ULONG SurpriseDownErrorReportingCapable:1; + ULONG DataLinkLayerActiveReportingCapable:1; + ULONG Rsvd:3; + ULONG PortNumber:8; + } DUMMYSTRUCTNAME; + ULONG AsULONG; +} PCI_EXPRESS_LINK_CAPABILITIES_REGISTER, *PPCI_EXPRESS_LINK_CAPABILITIES_REGISTER; + +typedef union _PCI_EXPRESS_LINK_CONTROL_REGISTER { + struct { + USHORT ActiveStatePMControl:2; + USHORT Rsvd1:1; + USHORT ReadCompletionBoundary:1; + USHORT LinkDisable:1; + USHORT RetrainLink:1; + USHORT CommonClockConfig:1; + USHORT ExtendedSynch:1; + USHORT EnableClockPowerManagement:1; + USHORT Rsvd2:7; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_LINK_CONTROL_REGISTER, *PPCI_EXPRESS_LINK_CONTROL_REGISTER; + +typedef union _PCI_EXPRESS_LINK_STATUS_REGISTER { + struct { + USHORT LinkSpeed:4; + USHORT LinkWidth:6; + USHORT Undefined:1; + USHORT LinkTraining:1; + USHORT SlotClockConfig:1; + USHORT DataLinkLayerActive:1; + USHORT Rsvd:2; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_LINK_STATUS_REGISTER, *PPCI_EXPRESS_LINK_STATUS_REGISTER; + +typedef union _PCI_EXPRESS_SLOT_CAPABILITIES_REGISTER { + struct { + ULONG AttentionButtonPresent:1; + ULONG PowerControllerPresent:1; + ULONG MRLSensorPresent:1; + ULONG AttentionIndicatorPresent:1; + ULONG PowerIndicatorPresent:1; + ULONG HotPlugSurprise:1; + ULONG HotPlugCapable:1; + ULONG SlotPowerLimit:8; + ULONG SlotPowerLimitScale:2; + ULONG ElectromechanicalLockPresent:1; + ULONG NoCommandCompletedSupport:1; + ULONG PhysicalSlotNumber:13; + } DUMMYSTRUCTNAME; + ULONG AsULONG; +} PCI_EXPRESS_SLOT_CAPABILITIES_REGISTER, *PPCI_EXPRESS_SLOT_CAPABILITIES_REGISTER; + +typedef union _PCI_EXPRESS_SLOT_CONTROL_REGISTER { + struct { + USHORT AttentionButtonEnable:1; + USHORT PowerFaultDetectEnable:1; + USHORT MRLSensorEnable:1; + USHORT PresenceDetectEnable:1; + USHORT CommandCompletedEnable:1; + USHORT HotPlugInterruptEnable:1; + USHORT AttentionIndicatorControl:2; + USHORT PowerIndicatorControl:2; + USHORT PowerControllerControl:1; + USHORT ElectromechanicalLockControl:1; + USHORT DataLinkStateChangeEnable:1; + USHORT Rsvd:3; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_SLOT_CONTROL_REGISTER, *PPCI_EXPRESS_SLOT_CONTROL_REGISTER; + +typedef union _PCI_EXPRESS_SLOT_STATUS_REGISTER { + struct { + USHORT AttentionButtonPressed:1; + USHORT PowerFaultDetected:1; + USHORT MRLSensorChanged:1; + USHORT PresenceDetectChanged:1; + USHORT CommandCompleted:1; + USHORT MRLSensorState:1; + USHORT PresenceDetectState:1; + USHORT ElectromechanicalLockEngaged:1; + USHORT DataLinkStateChanged:1; + USHORT Rsvd:7; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_SLOT_STATUS_REGISTER, *PPCI_EXPRESS_SLOT_STATUS_REGISTER; + +typedef union _PCI_EXPRESS_ROOT_CONTROL_REGISTER { + struct { + USHORT CorrectableSerrEnable:1; + USHORT NonFatalSerrEnable:1; + USHORT FatalSerrEnable:1; + USHORT PMEInterruptEnable:1; + USHORT CRSSoftwareVisibilityEnable:1; + USHORT Rsvd:11; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_ROOT_CONTROL_REGISTER, *PPCI_EXPRESS_ROOT_CONTROL_REGISTER; + +typedef union _PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER { + struct { + USHORT CRSSoftwareVisibility:1; + USHORT Rsvd:15; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER, *PPCI_EXPRESS_ROOT_CAPABILITIES_REGISTER; + +typedef union _PCI_EXPRESS_ROOT_STATUS_REGISTER { + struct { + ULONG PMERequestorId:16; + ULONG PMEStatus:1; + ULONG PMEPending:1; + ULONG Rsvd:14; + } DUMMYSTRUCTNAME; + ULONG AsULONG; +} PCI_EXPRESS_ROOT_STATUS_REGISTER, *PPCI_EXPRESS_ROOT_STATUS_REGISTER; + +typedef struct _PCI_EXPRESS_CAPABILITY { + PCI_CAPABILITIES_HEADER Header; + PCI_EXPRESS_CAPABILITIES_REGISTER ExpressCapabilities; + PCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER DeviceCapabilities; + PCI_EXPRESS_DEVICE_CONTROL_REGISTER DeviceControl; + PCI_EXPRESS_DEVICE_STATUS_REGISTER DeviceStatus; + PCI_EXPRESS_LINK_CAPABILITIES_REGISTER LinkCapabilities; + PCI_EXPRESS_LINK_CONTROL_REGISTER LinkControl; + PCI_EXPRESS_LINK_STATUS_REGISTER LinkStatus; + PCI_EXPRESS_SLOT_CAPABILITIES_REGISTER SlotCapabilities; + PCI_EXPRESS_SLOT_CONTROL_REGISTER SlotControl; + PCI_EXPRESS_SLOT_STATUS_REGISTER SlotStatus; + PCI_EXPRESS_ROOT_CONTROL_REGISTER RootControl; + PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER RootCapabilities; + PCI_EXPRESS_ROOT_STATUS_REGISTER RootStatus; +} PCI_EXPRESS_CAPABILITY, *PPCI_EXPRESS_CAPABILITY; + +typedef enum { + MRLClosed = 0, + MRLOpen +} PCI_EXPRESS_MRL_STATE; + +typedef enum { + SlotEmpty = 0, + CardPresent +} PCI_EXPRESS_CARD_PRESENCE; + +typedef enum { + IndicatorOn = 1, + IndicatorBlink, + IndicatorOff +} PCI_EXPRESS_INDICATOR_STATE; + +typedef enum { + PowerOn = 0, + PowerOff +} PCI_EXPRESS_POWER_STATE; + +typedef enum { + L0sEntrySupport = 1, + L0sAndL1EntrySupport = 3 +} PCI_EXPRESS_ASPM_SUPPORT; + +typedef enum { + L0sAndL1EntryDisabled, + L0sEntryEnabled, + L1EntryEnabled, + L0sAndL1EntryEnabled +} PCI_EXPRESS_ASPM_CONTROL; + +typedef enum { + L0s_Below64ns = 0, + L0s_64ns_128ns, + L0s_128ns_256ns, + L0s_256ns_512ns, + L0s_512ns_1us, + L0s_1us_2us, + L0s_2us_4us, + L0s_Above4us +} PCI_EXPRESS_L0s_EXIT_LATENCY; + +typedef enum { + L1_Below1us = 0, + L1_1us_2us, + L1_2us_4us, + L1_4us_8us, + L1_8us_16us, + L1_16us_32us, + L1_32us_64us, + L1_Above64us +} PCI_EXPRESS_L1_EXIT_LATENCY; + +typedef enum { + PciExpressEndpoint = 0, + PciExpressLegacyEndpoint, + PciExpressRootPort = 4, + PciExpressUpstreamSwitchPort, + PciExpressDownstreamSwitchPort, + PciExpressToPciXBridge, + PciXToExpressBridge, + PciExpressRootComplexIntegratedEndpoint, + PciExpressRootComplexEventCollector +} PCI_EXPRESS_DEVICE_TYPE; + +typedef enum { + MaxPayload128Bytes = 0, + MaxPayload256Bytes, + MaxPayload512Bytes, + MaxPayload1024Bytes, + MaxPayload2048Bytes, + MaxPayload4096Bytes +} PCI_EXPRESS_MAX_PAYLOAD_SIZE; + +typedef union _PCI_EXPRESS_PME_REQUESTOR_ID { + struct { + USHORT FunctionNumber:3; + USHORT DeviceNumber:5; + USHORT BusNumber:8; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_PME_REQUESTOR_ID, *PPCI_EXPRESS_PME_REQUESTOR_ID; + +#if defined(_WIN64) + +#ifndef USE_DMA_MACROS +#define USE_DMA_MACROS +#endif + +#ifndef NO_LEGACY_DRIVERS +#define NO_LEGACY_DRIVERS +#endif + +#endif /* defined(_WIN64) */ + +typedef enum _PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE { + ResourceTypeSingle = 0, + ResourceTypeRange, + ResourceTypeExtendedCounterConfiguration, + ResourceTypeOverflow, + ResourceTypeMax +} PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE; + +typedef struct _PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR { + PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE Type; + ULONG Flags; + union { + ULONG CounterIndex; + ULONG ExtendedRegisterAddress; + struct { + ULONG Begin; + ULONG End; + } Range; + } u; +} PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR, *PPHYSICAL_COUNTER_RESOURCE_DESCRIPTOR; + +typedef struct _PHYSICAL_COUNTER_RESOURCE_LIST { + ULONG Count; + PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR Descriptors[ANYSIZE_ARRAY]; +} PHYSICAL_COUNTER_RESOURCE_LIST, *PPHYSICAL_COUNTER_RESOURCE_LIST; + +typedef VOID +(NTAPI *PciPin2Line)( + IN struct _BUS_HANDLER *BusHandler, + IN struct _BUS_HANDLER *RootHandler, + IN PCI_SLOT_NUMBER SlotNumber, + IN PPCI_COMMON_CONFIG PciData); + +typedef VOID +(NTAPI *PciLine2Pin)( + IN struct _BUS_HANDLER *BusHandler, + IN struct _BUS_HANDLER *RootHandler, + IN PCI_SLOT_NUMBER SlotNumber, + IN PPCI_COMMON_CONFIG PciNewData, + IN PPCI_COMMON_CONFIG PciOldData); + +typedef VOID +(NTAPI *PciReadWriteConfig)( + IN struct _BUS_HANDLER *BusHandler, + IN PCI_SLOT_NUMBER Slot, + IN PVOID Buffer, + IN ULONG Offset, + IN ULONG Length); + +#define PCI_DATA_TAG ' ICP' +#define PCI_DATA_VERSION 1 + +typedef struct _PCIBUSDATA { + ULONG Tag; + ULONG Version; + PciReadWriteConfig ReadConfig; + PciReadWriteConfig WriteConfig; + PciPin2Line Pin2Line; + PciLine2Pin Line2Pin; + PCI_SLOT_NUMBER ParentSlot; + PVOID Reserved[4]; +} PCIBUSDATA, *PPCIBUSDATA; + +#ifndef _PCIINTRF_X_ +#define _PCIINTRF_X_ + +typedef ULONG +(NTAPI *PCI_READ_WRITE_CONFIG)( + IN PVOID Context, + IN ULONG BusOffset, + IN ULONG Slot, + IN PVOID Buffer, + IN ULONG Offset, + IN ULONG Length); + +typedef VOID +(NTAPI *PCI_PIN_TO_LINE)( + IN PVOID Context, + IN PPCI_COMMON_CONFIG PciData); + +typedef VOID +(NTAPI *PCI_LINE_TO_PIN)( + IN PVOID Context, + IN PPCI_COMMON_CONFIG PciNewData, + IN PPCI_COMMON_CONFIG PciOldData); + +typedef VOID +(NTAPI *PCI_ROOT_BUS_CAPABILITY)( + IN PVOID Context, + OUT PPCI_ROOT_BUS_HARDWARE_CAPABILITY HardwareCapability); + +typedef VOID +(NTAPI *PCI_EXPRESS_WAKE_CONTROL)( + IN PVOID Context, + IN BOOLEAN EnableWake); + +typedef struct _PCI_BUS_INTERFACE_STANDARD { + USHORT Size; + USHORT Version; + PVOID Context; + PINTERFACE_REFERENCE InterfaceReference; + PINTERFACE_DEREFERENCE InterfaceDereference; + PCI_READ_WRITE_CONFIG ReadConfig; + PCI_READ_WRITE_CONFIG WriteConfig; + PCI_PIN_TO_LINE PinToLine; + PCI_LINE_TO_PIN LineToPin; + PCI_ROOT_BUS_CAPABILITY RootBusCapability; + PCI_EXPRESS_WAKE_CONTROL ExpressWakeControl; +} PCI_BUS_INTERFACE_STANDARD, *PPCI_BUS_INTERFACE_STANDARD; + +#define PCI_BUS_INTERFACE_STANDARD_VERSION 1 + +#endif /* _PCIINTRF_X_ */ + +#if (NTDDI_VERSION >= NTDDI_WIN7) + +#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX 0x00004000 +#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX 0x00008000 +#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_EX \ + (FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX | \ + FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX) + +#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_DEPRECATED 0x00000200 +#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_DEPRECATED 0x00000300 +#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_DEPRECATED 0x00000300 + +#else + +#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL 0x00000200 +#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL 0x00000300 +#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK 0x00000300 + +#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL +#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL +#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_EX FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK + +#endif /* (NTDDI_VERSION >= NTDDI_WIN7) */ + typedef enum _HAL_QUERY_INFORMATION_CLASS { HalInstalledBusInformation, HalProfileSourceInformation, @@ -421,39 +1133,6 @@ ULONG Version; PVOID Function[1]; } PM_DISPATCH_TABLE, *PPM_DISPATCH_TABLE; - -typedef enum _RESOURCE_TRANSLATION_DIRECTION { - TranslateChildToParent, - TranslateParentToChild -} RESOURCE_TRANSLATION_DIRECTION; - -typedef NTSTATUS -(NTAPI *PTRANSLATE_RESOURCE_HANDLER)( - IN OUT PVOID Context, - IN PCM_PARTIAL_RESOURCE_DESCRIPTOR Source, - IN RESOURCE_TRANSLATION_DIRECTION Direction, - IN ULONG AlternativesCount OPTIONAL, - IN IO_RESOURCE_DESCRIPTOR Alternatives[], - IN PDEVICE_OBJECT PhysicalDeviceObject, - OUT PCM_PARTIAL_RESOURCE_DESCRIPTOR Target); - -typedef NTSTATUS -(NTAPI *PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER)( - IN PVOID Context OPTIONAL, - IN PIO_RESOURCE_DESCRIPTOR Source, - IN PDEVICE_OBJECT PhysicalDeviceObject, - OUT PULONG TargetCount, - OUT PIO_RESOURCE_DESCRIPTOR *Target); - -typedef struct _TRANSLATOR_INTERFACE { - USHORT Size; - USHORT Version; - PVOID Context; - PINTERFACE_REFERENCE InterfaceReference; - PINTERFACE_DEREFERENCE InterfaceDereference; - PTRANSLATE_RESOURCE_HANDLER TranslateResources; - PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER TranslateResourceRequirements; -} TRANSLATOR_INTERFACE, *PTRANSLATOR_INTERFACE; typedef VOID (FASTCALL *pHalExamineMBR)( @@ -1867,42 +2546,10 @@ /* Hardware Abstraction Layer Types */ -typedef VOID -(NTAPI *PciPin2Line)( - IN struct _BUS_HANDLER *BusHandler, - IN struct _BUS_HANDLER *RootHandler, - IN PCI_SLOT_NUMBER SlotNumber, - IN PPCI_COMMON_CONFIG PciData); - -typedef VOID -(NTAPI *PciLine2Pin)( - IN struct _BUS_HANDLER *BusHandler, - IN struct _BUS_HANDLER *RootHandler, - IN PCI_SLOT_NUMBER SlotNumber, - IN PPCI_COMMON_CONFIG PciNewData, - IN PPCI_COMMON_CONFIG PciOldData); - -typedef VOID -(NTAPI *PciReadWriteConfig)( - IN struct _BUS_HANDLER *BusHandler, - IN PCI_SLOT_NUMBER Slot, - IN PVOID Buffer, - IN ULONG Offset, - IN ULONG Length); - -#define PCI_DATA_TAG ' ICP' -#define PCI_DATA_VERSION 1 - -typedef struct _PCIBUSDATA { - ULONG Tag; - ULONG Version; - PciReadWriteConfig ReadConfig; - PciReadWriteConfig WriteConfig; - PciPin2Line Pin2Line; - PciLine2Pin Line2Pin; - PCI_SLOT_NUMBER ParentSlot; - PVOID Reserved[4]; -} PCIBUSDATA, *PPCIBUSDATA; + + + + /* Hardware Abstraction Layer Functions */

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Ros-diffs June 2010