Ros-diffs June 2019

ros-diffs@reactos.org

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288 discussions

[reactos] 01/01: [WIN32SS][NTGDI] Strictly check in XFORMOBJ_iSetXform (#1676)
by Katayama Hirofumi MZ 24 Jun '19

24 Jun '19

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=bf06c94e15c47e549e824… commit bf06c94e15c47e549e824a1f82e672d40b150bc6 Author: Katayama Hirofumi MZ <katayama.hirofumi.mz(a)gmail.com> AuthorDate: Mon Jun 24 21:32:40 2019 +0900 Commit: GitHub <noreply(a)github.com> CommitDate: Mon Jun 24 21:32:40 2019 +0900 [WIN32SS][NTGDI] Strictly check in XFORMOBJ_iSetXform (#1676) Check if the determinant of the given transformation matrix is non-zero. If zero, the function returns DDI_ERROR without change. CORE-15554 --- win32ss/gdi/ntgdi/xformobj.c | 60 ++++++++++++++++++++++++++++++++------------ 1 file changed, 44 insertions(+), 16 deletions(-) diff --git a/win32ss/gdi/ntgdi/xformobj.c b/win32ss/gdi/ntgdi/xformobj.c index fccf5517b38..ebd8f6b19ef 100644 --- a/win32ss/gdi/ntgdi/xformobj.c +++ b/win32ss/gdi/ntgdi/xformobj.c @@ -104,12 +104,9 @@ HintFromAccel(ULONG flAccel) /** Internal functions ********************************************************/ ULONG -NTAPI -XFORMOBJ_UpdateAccel( - IN OUT XFORMOBJ *pxo) +FASTCALL +MX_UpdateAccel(IN OUT PMATRIX pmx) { - PMATRIX pmx = XFORMOBJ_pmx(pxo); - /* Copy Dx and Dy to FIX format */ pmx->fxDx = FLOATOBJ_GetFix(&pmx->efDx); pmx->fxDy = FLOATOBJ_GetFix(&pmx->efDy); @@ -143,6 +140,16 @@ XFORMOBJ_UpdateAccel( return HintFromAccel(pmx->flAccel); } +ULONG +NTAPI +XFORMOBJ_UpdateAccel( + IN OUT XFORMOBJ *pxo) +{ + PMATRIX pmx = XFORMOBJ_pmx(pxo); + + return MX_UpdateAccel(pmx); +} + ULONG NTAPI @@ -150,24 +157,45 @@ XFORMOBJ_iSetXform( IN OUT XFORMOBJ *pxo, IN const XFORML *pxform) { - PMATRIX pmx = XFORMOBJ_pmx(pxo); + PMATRIX pmx; + MATRIX mxTemp; + ULONG Hint; /* Check parameters */ if (!pxo || !pxform) return DDI_ERROR; - /* Check if the xform is valid */ - if ((pxform->eM11 == 0) || (pxform->eM22 == 0)) return DDI_ERROR; - /* Copy members */ - FLOATOBJ_SetFloat(&pmx->efM11, pxform->eM11); - FLOATOBJ_SetFloat(&pmx->efM12, pxform->eM12); - FLOATOBJ_SetFloat(&pmx->efM21, pxform->eM21); - FLOATOBJ_SetFloat(&pmx->efM22, pxform->eM22); - FLOATOBJ_SetFloat(&pmx->efDx, pxform->eDx); - FLOATOBJ_SetFloat(&pmx->efDy, pxform->eDy); + FLOATOBJ_SetFloat(&mxTemp.efM11, pxform->eM11); + FLOATOBJ_SetFloat(&mxTemp.efM12, pxform->eM12); + FLOATOBJ_SetFloat(&mxTemp.efM21, pxform->eM21); + FLOATOBJ_SetFloat(&mxTemp.efM22, pxform->eM22); + FLOATOBJ_SetFloat(&mxTemp.efDx, pxform->eDx); + FLOATOBJ_SetFloat(&mxTemp.efDy, pxform->eDy); /* Update accelerators and return complexity */ - return XFORMOBJ_UpdateAccel(pxo); + Hint = MX_UpdateAccel(&mxTemp); + + /* Check whether det = (M11 * M22 - M12 * M21) is non-zero */ + if (Hint == GX_SCALE) + { + if (FLOATOBJ_Equal0(&mxTemp.efM11) || FLOATOBJ_Equal0(&mxTemp.efM22)) + { + return DDI_ERROR; + } + } + else if (Hint == GX_GENERAL) + { + if (!MX_IsInvertible(&mxTemp)) + { + return DDI_ERROR; + } + } + + /* Store */ + pmx = XFORMOBJ_pmx(pxo); + *pmx = mxTemp; + + return Hint; }

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[reactos] 01/01: [BOOTVID] Diverse enhancements.
by Hermès Bélusca-Maïto 23 Jun '19

23 Jun '19

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=ede3fddad734ff37f6ab3… commit ede3fddad734ff37f6ab33d672f377c0e57b8be1 Author: Hermès Bélusca-Maïto <hermes.belusca-maito(a)reactos.org> AuthorDate: Sun Jun 23 21:05:28 2019 +0200 Commit: Hermès Bélusca-Maïto <hermes.belusca-maito(a)reactos.org> CommitDate: Sun Jun 23 23:59:48 2019 +0200 [BOOTVID] Diverse enhancements. - Import cmdcnst.h and vga.h headers from the 'vga_new' VGA Miniport Driver, that contain definitions related to VGA registers as well as command-stream functionality. - Replace a bunch of hardcoded values by their corresponding defintions. - Replace "Captain-Obvious" comments in VgaIsPresent() with actual explanations from the corresponding function in 'vga_new'. - Simplify the VgaInterpretCmdStream() function, based on the corresponding one from 'vga_new'. - Use concise comments in the 'AT_Initialization' command stream definition. - Import the 'VGA_640x480' initialization command stream from 'vga_new' and use it as the full VGA initialization stream whenever the HAL does not handle the VGA display (HalResetDisplay() returning FALSE). Otherwise we just use the 'AT_Initialization' command stream that performs minimal initialization. - Remove unused AT_Initialization and other declarations from ARM build. --- drivers/base/bootvid/arm/bootdata.c | 48 ---- drivers/base/bootvid/cmdcnst.h | 92 ++++++++ drivers/base/bootvid/i386/bootdata.c | 149 ++++++++---- drivers/base/bootvid/i386/bootvid.c | 446 ++++++++++++++++++----------------- drivers/base/bootvid/i386/vga.c | 70 +++--- drivers/base/bootvid/precomp.h | 12 +- drivers/base/bootvid/vga.h | 220 +++++++++++++++++ 7 files changed, 689 insertions(+), 348 deletions(-) diff --git a/drivers/base/bootvid/arm/bootdata.c b/drivers/base/bootvid/arm/bootdata.c index bb2491ca819..12f4a1dfe84 100644 --- a/drivers/base/bootvid/arm/bootdata.c +++ b/drivers/base/bootvid/arm/bootdata.c @@ -1,53 +1,5 @@ #include "precomp.h" -USHORT AT_Initialization[] = -{ - 0x10 | CMD_STREAM_READ, // Major Command = 0x10. Minor Command = 0x08. - 0x3DA, // Index Status 1 Register Port Address - - // - // This Stream performs a USHORT Array Indexed Write at port 0x3C0 - // - 0x20 | 0x01, // Major Command = 0x20. Minor Command = 0x01. - 0x3C0, // Attribute Controller Data Register - 0x10, // Loop Count = 16 (Number of Pallette Entries) - 0x0, // Index to select (Index = 0, palettes) - 0x00, // Palette 0 - 0x01, // Palette 1 - 0x02, // Palette 2 - 0x03, // Palette 3 - 0x04, // Palette 4 - 0x05, // Palette 5 - 0x06, // Palette 6 - 0x07, // Palette 7 - 0x08, // Palette 8 - 0x09, // Palette 9 - 0x0A, // Palette 10 - 0x0B, // Palette 11 - 0x0C, // Palette 12 - 0x0D, // Palette 13 - 0x0E, // Palette 14 - 0x0F, // Palette 15 - - // - // This Stream performs a UCHAR READ of port 0x3DA - // - 0x10 | CMD_STREAM_READ, // Major Command = 0x10. Minor Command = 0x08. - 0x3DA, // Index Status 1 Register Port Address - - // - // This Stream performs a UCHAR WRITE of value 0x20 at port 0x3C0 - // - 0x10 | CMD_STREAM_WRITE, // Major Command = 0x10. Minor Command = 0x00. - 0x3C0, // Attribute Controller Data Register - 0x20, // Set Palette Address Source - - // - // End of Stream Marker - // - 0x0 // End of command stream -}; - // // The character generator is in natural order, top of char is first element. // The used font is 8x13 from plan 9, copyright Markus Kuhn. diff --git a/drivers/base/bootvid/cmdcnst.h b/drivers/base/bootvid/cmdcnst.h new file mode 100644 index 00000000000..5b5dae91140 --- /dev/null +++ b/drivers/base/bootvid/cmdcnst.h @@ -0,0 +1,92 @@ +/* + * PROJECT: ReactOS VGA Miniport Driver + * LICENSE: Microsoft NT4 DDK Sample Code License + * PURPOSE: Command Code Definitions for VGA Command Streams + * PROGRAMMERS: Copyright (c) 1992 Microsoft Corporation + */ + +#pragma once + +//-------------------------------------------------------------------------- +// Definition of the set/clear mode command language. +// +// Each command is composed of a major portion and a minor portion. +// The major portion of a command can be found in the most significant +// nibble of a command byte, while the minor portion is in the least +// significant portion of a command byte. +// +// maj minor Description +// ---- ----- -------------------------------------------- +// 00 End of data +// +// 10 in and out type commands as described by flags +// flags: +// +// xxxx +// |||| +// |||+-------- unused +// ||+--------- 0/1 single/multiple values to output (in's are always +// |+---------- 0/1 8/16 bit operation single) +// +----------- 0/1 out/in instruction +// +// Outs +// ---------------------------------------------- +// 0 reg:W val:B +// 2 reg:W cnt:W val1:B val2:B...valN:B +// 4 reg:W val:W +// 6 reg:W cnt:W val1:W val2:W...valN:W +// +// Ins +// ---------------------------------------------- +// 8 reg:W +// a reg:W cnt:W +// c reg:W +// e reg:W cnt:W +// +// 20 Special purpose outs +// 00 do indexed outs for seq, crtc, and gdc +// indexreg:W cnt:B startindex:B val1:B val2:B...valN:B +// 01 do indexed outs for atc +// index-data_reg:W cnt:B startindex:B val1:B val2:B...valN:B +// 02 do masked outs +// indexreg:W andmask:B xormask:B +// +// F0 Nop +// +//--------------------------------------------------------------------------- + +// some useful equates - major commands + +#define EOD 0x000 // end of data +#define INOUT 0x010 // do ins or outs +#define METAOUT 0x020 // do special types of outs +#define NCMD 0x0f0 // Nop command + + +// flags for INOUT major command + +//#define UNUSED 0x01 // reserved +#define MULTI 0x02 // multiple or single outs +#define BW 0x04 // byte/word size of operation +#define IO 0x08 // out/in instruction + +// minor commands for METAOUT + +#define INDXOUT 0x00 // do indexed outs +#define ATCOUT 0x01 // do indexed outs for atc +#define MASKOUT 0x02 // do masked outs using and-xor masks + + +// composite INOUT type commands + +#define OB (INOUT) // output 8 bit value +#define OBM (INOUT+MULTI) // output multiple bytes +#define OW (INOUT+BW) // output single word value +#define OWM (INOUT+BW+MULTI) // output multiple words + +#define IB (INOUT+IO) // input byte +#define IBM (INOUT+IO+MULTI) // input multiple bytes +#define IW (INOUT+IO+BW) // input word +#define IWM (INOUT+IO+BW+MULTI) // input multiple words + +/* EOF */ diff --git a/drivers/base/bootvid/i386/bootdata.c b/drivers/base/bootvid/i386/bootdata.c index bb2491ca819..49fb6312aed 100644 --- a/drivers/base/bootvid/i386/bootdata.c +++ b/drivers/base/bootvid/i386/bootdata.c @@ -1,51 +1,120 @@ #include "precomp.h" +// +// Minimal Attribute Controller Registers initialization command stream. +// Compatible EGA. +// USHORT AT_Initialization[] = { - 0x10 | CMD_STREAM_READ, // Major Command = 0x10. Minor Command = 0x08. - 0x3DA, // Index Status 1 Register Port Address + /* Reset ATC to index mode */ + IB, + VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */, + + /* Write the AC registers */ + METAOUT+ATCOUT, + VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */, + 16, 0, // Values Count and Start Index + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, // Palette indices 0-5 + 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, // Palette indices 6-11 + 0x0C, 0x0D, 0x0E, 0x0F, // Palette indices 12-15 + + /* Reset ATC to index mode */ + IB, + VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */, + + /* Enable screen and disable palette access */ + OB, + VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */, + VIDEO_ENABLE, + + /* End of Stream */ + EOD +}; + +// +// 640x480 256-color 60Hz mode (BIOS mode 12) set command stream for VGA. +// Adapted from win32ss/drivers/miniport/vga_new/vgadata.c +// +USHORT VGA_640x480[] = +{ + /* Write the Sequencer Registers */ + OWM, + VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, + VGA_NUM_SEQUENCER_PORTS, // Values Count (5) + // HI: Value in SEQ_DATA_PORT, LO: Register index in SEQ_ADDRESS_PORT + 0x0100, // Synchronous reset on + 0x0101, // 8-Dot Mode + 0x0F02, // Memory Plane Write Enable on all planes 0-3 + 0x0003, // No character set selected + 0x0604, // Disable Odd/Even host mem addressing; Enable Extended Memory + + /* Write the Miscellaneous Register */ + OB, + VGA_BASE_IO_PORT + MISC_OUTPUT_REG_WRITE_PORT, + 0xE3, // V/H-SYNC polarity, Odd/Even High page select, RAM enable, + // I/O Address select (1: color/graphics adapter) + + /* Enable Graphics Mode */ + OW, + VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, + // HI: Value in GRAPH_DATA_PORT, LO: Register index in GRAPH_ADDRESS_PORT + 0x506, // Select A0000h-AFFFFh memory region, Disable Alphanumeric mode + + /* Synchronous reset off */ + OW, + VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, + // HI: Value in SEQ_DATA_PORT, LO: Register index in SEQ_ADDRESS_PORT + 0x0300, // Synchronous reset off (LO: IND_SYNC_RESET, HI: END_SYNC_RESET_VALUE) + + /* Unlock CRTC registers 0-7 */ + OW, + VGA_BASE_IO_PORT + CRTC_ADDRESS_PORT_COLOR, + 0x511, + + /* Write the CRTC registers */ + METAOUT+INDXOUT, + VGA_BASE_IO_PORT + CRTC_ADDRESS_PORT_COLOR, + VGA_NUM_CRTC_PORTS, 0, // Values Count (25) and Start Index + 0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0x0B, 0x3E, 0x00, 0x40, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xEA, 0x8C, 0xDF, 0x28, 0x00, 0xE7, 0x04, 0xE3, + 0xFF, + + /* Reset ATC to index mode */ + IB, + VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */, + + /* Write the AC registers */ + METAOUT+ATCOUT, + VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */, + VGA_NUM_ATTRIB_CONT_PORTS, 0, // Values Count (21) and Start Index + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, // Palette indices 0-5 + 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, // Palette indices 6-11 + 0x0C, 0x0D, 0x0E, 0x0F, // Palette indices 12-15 + 0x01, 0x00, 0x0F, 0x00, 0x00, + + /* Write the GC registers */ + METAOUT+INDXOUT, + VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, + VGA_NUM_GRAPH_CONT_PORTS, 0, // Values Count (9) and Start Index + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x0F, 0xFF, - // - // This Stream performs a USHORT Array Indexed Write at port 0x3C0 - // - 0x20 | 0x01, // Major Command = 0x20. Minor Command = 0x01. - 0x3C0, // Attribute Controller Data Register - 0x10, // Loop Count = 16 (Number of Pallette Entries) - 0x0, // Index to select (Index = 0, palettes) - 0x00, // Palette 0 - 0x01, // Palette 1 - 0x02, // Palette 2 - 0x03, // Palette 3 - 0x04, // Palette 4 - 0x05, // Palette 5 - 0x06, // Palette 6 - 0x07, // Palette 7 - 0x08, // Palette 8 - 0x09, // Palette 9 - 0x0A, // Palette 10 - 0x0B, // Palette 11 - 0x0C, // Palette 12 - 0x0D, // Palette 13 - 0x0E, // Palette 14 - 0x0F, // Palette 15 + /* Set the PEL mask */ + OB, + VGA_BASE_IO_PORT + DAC_PIXEL_MASK_PORT, + 0xFF, - // - // This Stream performs a UCHAR READ of port 0x3DA - // - 0x10 | CMD_STREAM_READ, // Major Command = 0x10. Minor Command = 0x08. - 0x3DA, // Index Status 1 Register Port Address + /* Reset ATC to index mode */ + IB, + VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */, - // - // This Stream performs a UCHAR WRITE of value 0x20 at port 0x3C0 - // - 0x10 | CMD_STREAM_WRITE, // Major Command = 0x10. Minor Command = 0x00. - 0x3C0, // Attribute Controller Data Register - 0x20, // Set Palette Address Source + /* Enable screen and disable palette access */ + OB, + VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */, + VIDEO_ENABLE, - // - // End of Stream Marker - // - 0x0 // End of command stream + /* End of Stream */ + EOD }; // diff --git a/drivers/base/bootvid/i386/bootvid.c b/drivers/base/bootvid/i386/bootvid.c index 89fc4f4a6ee..db81548a1ba 100644 --- a/drivers/base/bootvid/i386/bootvid.c +++ b/drivers/base/bootvid/i386/bootvid.c @@ -6,14 +6,11 @@ static BOOLEAN NTAPI VgaInterpretCmdStream(IN PUSHORT CmdStream) { - PUCHAR Base = (PUCHAR)VgaRegisterBase; USHORT Cmd; UCHAR Major, Minor; + USHORT Port; USHORT Count; UCHAR Index; - PUSHORT Buffer; - PUSHORT ShortPort; - PUCHAR Port; UCHAR Value; USHORT ShortValue; @@ -21,196 +18,136 @@ VgaInterpretCmdStream(IN PUSHORT CmdStream) if (!CmdStream) return TRUE; /* Loop as long as we have commands */ - while (*CmdStream) + while (*CmdStream != EOD) { - /* Get the Major and Minor Function */ - Cmd = *CmdStream; + /* Get the next command and its Major and Minor functions */ + Cmd = *CmdStream++; Major = Cmd & 0xF0; Minor = Cmd & 0x0F; - /* Move to the next command */ - CmdStream++; - - /* Check which major function this was */ - if (Major == 0x10) + /* Check which major function this is */ + if (Major == INOUT) { - /* Now let's see the minor function */ - if (Minor & CMD_STREAM_READ) + /* Check the minor function */ + if (Minor & IO /* CMD_STREAM_READ */) { - /* Now check the sub-type */ - if (Minor & CMD_STREAM_USHORT) + /* Check the sub-type */ + if (Minor & BW /* CMD_STREAM_USHORT */) { - /* The port is what is in the stream right now */ - ShortPort = UlongToPtr((ULONG)*CmdStream); - - /* Move to the next command */ - CmdStream++; - - /* Read USHORT from the port */ - READ_PORT_USHORT(PtrToUlong(Base) + ShortPort); + /* Get the port and read an USHORT from it */ + Port = *CmdStream++; + ShortValue = __inpw(Port); } - else + else // if (Minor & CMD_STREAM_WRITE) { - /* The port is what is in the stream right now */ - Port = UlongToPtr((ULONG)*CmdStream); - - /* Move to the next command */ - CmdStream++; - - /* Read UCHAR from the port */ - READ_PORT_UCHAR(PtrToUlong(Base) + Port); + /* Get the port and read an UCHAR from it */ + Port = *CmdStream++; + Value = __inpb(Port); } } - else if (Minor & CMD_STREAM_WRITE_ARRAY) + else if (Minor & MULTI /* CMD_STREAM_WRITE_ARRAY */) { - /* Now check the sub-type */ - if (Minor & CMD_STREAM_USHORT) + /* Check the sub-type */ + if (Minor & BW /* CMD_STREAM_USHORT */) { - /* The port is what is in the stream right now */ - ShortPort = UlongToPtr(Cmd); - - /* Move to the next command and get the count */ - Count = *(CmdStream++); - - /* The buffer is what's next in the command stream */ - Buffer = CmdStream++; + /* Get the port and the count of elements */ + Port = *CmdStream++; + Count = *CmdStream++; - /* Write USHORT to the port */ - WRITE_PORT_BUFFER_USHORT(PtrToUshort(Base) + ShortPort, Buffer, Count); + /* Write the USHORT to the port; the buffer is what's in the command stream */ + WRITE_PORT_BUFFER_USHORT((PUSHORT)(VgaRegisterBase + Port), CmdStream, Count); /* Move past the buffer in the command stream */ CmdStream += Count; } - else + else // if (Minor & CMD_STREAM_WRITE) { - /* The port is what is in the stream right now */ - Port = UlongToPtr(Cmd); + /* Get the port and the count of elements */ + Port = *CmdStream++; + Count = *CmdStream++; - /* Move to the next command and get the count */ - Count = *(CmdStream++); - - /* Add the base to the port */ - Port = PtrToUlong(Port) + Base; - - /* Move to next command */ - CmdStream++; - - /* Loop the cmd array */ - for (; Count; Count--, CmdStream++) + /* Loop the command array */ + for (; Count; --Count, ++CmdStream) { - /* Get the byte we're writing */ + /* Get the UCHAR and write it to the port */ Value = (UCHAR)*CmdStream; - - /* Write UCHAR to the port */ - WRITE_PORT_UCHAR(Port, Value); + __outpb(Port, Value); } } } - else if (Minor & CMD_STREAM_USHORT) + else if (Minor & BW /* CMD_STREAM_USHORT */) { - /* Get the ushort we're writing and advance in the stream */ - ShortValue = *CmdStream; - CmdStream++; + /* Get the port */ + Port = *CmdStream++; - /* Write USHORT to the port (which is in cmd) */ - WRITE_PORT_USHORT((PUSHORT)Base + Cmd, ShortValue); + /* Get the USHORT and write it to the port */ + ShortValue = *CmdStream++; + __outpw(Port, ShortValue); } - else + else // if (Minor & CMD_STREAM_WRITE) { - /* The port is what is in the stream right now */ - Port = UlongToPtr((ULONG)*CmdStream); - - /* Get the uchar we're writing */ - Value = (UCHAR)*++CmdStream; - - /* Move to the next command */ - CmdStream++; + /* Get the port */ + Port = *CmdStream++; - /* Write UCHAR to the port (which is in cmd) */ - WRITE_PORT_UCHAR(PtrToUlong(Base) + Port, Value); + /* Get the UCHAR and write it to the port */ + Value = (UCHAR)*CmdStream++; + __outpb(Port, Value); } } - else if (Major == 0x20) + else if (Major == METAOUT) { - /* Check the minor function. Note these are not flags anymore. */ + /* Check the minor function. Note these are not flags. */ switch (Minor) { - case 0: + case INDXOUT: { - /* The port is what is in the stream right now */ - ShortPort = UlongToPtr(*CmdStream); + /* Get the port, the count of elements and the start index */ + Port = *CmdStream++; + Count = *CmdStream++; + Index = (UCHAR)*CmdStream++; - /* Move to the next command and get the count */ - Count = *(CmdStream++); - - /* Move to the next command and get the value to write */ - ShortValue = *(CmdStream++); - - /* Add the base to the port */ - ShortPort = PtrToUlong(ShortPort) + (PUSHORT)Base; - - /* Move to next command */ - CmdStream++; - - /* Make sure we have data */ - if (!ShortValue) continue; - - /* Loop the cmd array */ - for (; Count; Count--, CmdStream++) + /* Loop the command array */ + for (; Count; --Count, ++Index, ++CmdStream) { - /* Get the byte we're writing */ - ShortValue += (*CmdStream) << 8; - - /* Write USHORT to the port */ - WRITE_PORT_USHORT(ShortPort, ShortValue); + /* Get the USHORT and write it to the port */ + ShortValue = (USHORT)Index + ((*CmdStream) << 8); + __outpw(Port, ShortValue); } break; } - case 1: + case ATCOUT: { - /* The port is what is in the stream right now. Add the base too */ - Port = *CmdStream + Base; + /* Get the port, the count of elements and the start index */ + Port = *CmdStream++; + Count = *CmdStream++; + Index = (UCHAR)*CmdStream++; - /* Move to the next command and get the count */ - Count = *++CmdStream; - - /* Move to the next command and get the index to write */ - Index = (UCHAR)*++CmdStream; - - /* Move to next command */ - CmdStream++; - - /* Loop the cmd array */ - for (; Count; Count--, Index++) + /* Loop the command array */ + for (; Count; --Count, ++Index, ++CmdStream) { /* Write the index */ - WRITE_PORT_UCHAR(Port, Index); + __outpb(Port, Index); - /* Get the byte we're writing */ + /* Get the UCHAR and write it to the port */ Value = (UCHAR)*CmdStream; - - /* Move to next command */ - CmdStream++; - - /* Write UCHAR value to the port */ - WRITE_PORT_UCHAR(Port, Value); + __outpb(Port, Value); } break; } - case 2: + case MASKOUT: { - /* The port is what is in the stream right now. Add the base too */ - Port = *CmdStream + Base; + /* Get the port */ + Port = *CmdStream++; /* Read the current value and add the stream data */ - Value = READ_PORT_UCHAR(Port); + Value = __inpb(Port); Value &= *CmdStream++; Value ^= *CmdStream++; /* Write the value */ - WRITE_PORT_UCHAR(Port, Value); + __outpb(Port, Value); break; } @@ -219,7 +156,7 @@ VgaInterpretCmdStream(IN PUSHORT CmdStream) return FALSE; } } - else if (Major != 0xF0) + else if (Major != NCMD) { /* Unknown major function, fail */ return FALSE; @@ -234,123 +171,181 @@ static BOOLEAN NTAPI VgaIsPresent(VOID) { - UCHAR VgaReg, VgaReg2, VgaReg3; - UCHAR SeqReg, SeqReg2; + UCHAR OrgGCAddr, OrgReadMap, OrgBitMask; + UCHAR OrgSCAddr, OrgMemMode; UCHAR i; - /* Read the VGA Address Register */ - VgaReg = __inpb(0x3CE); - - /* Select Read Map Select Register */ - __outpb(0x3CE, 4); - - /* Read it back... it should be 4 */ - if ((__inpb(0x3CE) & 0xF) != 4) + /* Remember the original state of the Graphics Controller Address register */ + OrgGCAddr = __inpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT); + + /* + * Write the Read Map register with a known state so we can verify + * that it isn't changed after we fool with the Bit Mask. This ensures + * that we're dealing with indexed registers, since both the Read Map and + * the Bit Mask are addressed at GRAPH_DATA_PORT. + */ + __outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_READ_MAP); + + /* + * If we can't read back the Graphics Address register setting we just + * performed, it's not readable and this isn't a VGA. + */ + if ((__inpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT) & GRAPH_ADDR_MASK) != IND_READ_MAP) return FALSE; - /* Read the VGA Data Register */ - VgaReg2 = __inpb(0x3CF); - - /* Enable all planes */ - __outpb(0x3CF, 3); + /* + * Set the Read Map register to a known state. + */ + OrgReadMap = __inpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT); + __outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, READ_MAP_TEST_SETTING); - /* Read it back... it should be 3 */ - if (__inpb(0x3CF) != 0x3) + /* Read it back... it should be the same */ + if (__inpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT) != READ_MAP_TEST_SETTING) { - /* Reset the registers and fail */ - __outpb(0x3CF, 0); + /* + * The Read Map setting we just performed can't be read back; not a + * VGA. Restore the default Read Map state and fail. + */ + __outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, READ_MAP_DEFAULT); return FALSE; } - /* Select Bit Mask Register */ - __outpb(0x3CE, 8); + /* Remember the original setting of the Bit Mask register */ + __outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_BIT_MASK); - /* Read it back... it should be 8 */ - if ((__inpb(0x3CE) & 0xF) != 8) + /* Read it back... it should be the same */ + if ((__inpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT) & GRAPH_ADDR_MASK) != IND_BIT_MASK) { - /* Reset the registers and fail */ - __outpb(0x3CE, 4); - __outpb(0x3CF, 0); + /* + * The Graphics Address register setting we just made can't be read + * back; not a VGA. Restore the default Read Map state and fail. + */ + __outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_READ_MAP); + __outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, READ_MAP_DEFAULT); return FALSE; } /* Read the VGA Data Register */ - VgaReg3 = __inpb(0x3CF); + OrgBitMask = __inpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT); - /* Loop bitmasks */ + /* + * Set up the initial test mask we'll write to and read from the Bit Mask, + * and loop on the bitmasks. + */ for (i = 0xBB; i; i >>= 1) { - /* Set bitmask */ - __outpb(0x3CF, i); + /* Write the test mask to the Bit Mask */ + __outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, i); /* Read it back... it should be the same */ - if (__inpb(0x3CF) != i) + if (__inpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT) != i) { - /* Reset the registers and fail */ - __outpb(0x3CF, 0xFF); - __outpb(0x3CE, 4); - __outpb(0x3CF, 0); + /* + * The Bit Mask is not properly writable and readable; not a VGA. + * Restore the Bit Mask and Read Map to their default states and fail. + */ + __outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, BIT_MASK_DEFAULT); + __outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_READ_MAP); + __outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, READ_MAP_DEFAULT); return FALSE; } } - /* Select Read Map Select Register */ - __outpb(0x3CE, 4); + /* + * There's something readable at GRAPH_DATA_PORT; now switch back and + * make sure that the Read Map register hasn't changed, to verify that + * we're dealing with indexed registers. + */ + __outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_READ_MAP); - /* Read it back... it should be 3 */ - if (__inpb(0x3CF) != 3) + /* Read it back */ + if (__inpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT) != READ_MAP_TEST_SETTING) { - /* Reset the registers and fail */ - __outpb(0x3CF, 0); - __outpb(0x3CE, 8); - __outpb(0x3CF, 0xFF); + /* + * The Read Map is not properly writable and readable; not a VGA. + * Restore the Bit Mask and Read Map to their default states, in case + * this is an EGA, so subsequent writes to the screen aren't garbled. + * Then fail. + */ + __outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, READ_MAP_DEFAULT); + __outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_BIT_MASK); + __outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, BIT_MASK_DEFAULT); return FALSE; } - /* Write the registers we read earlier */ - __outpb(0x3CF, VgaReg2); - __outpb(0x3CE, 8); - __outpb(0x3CF, VgaReg3); - __outpb(0x3CE, VgaReg); - - /* Read sequencer address */ - SeqReg = __inpb(0x3C4); - - /* Select memory mode register */ - __outpb(0x3C4, 4); - - /* Read it back... it should still be 4 */ - if ((__inpb(0x3C4) & 7) != 4) + /* + * We've pretty surely verified the existence of the Bit Mask register. + * Put the Graphics Controller back to the original state. + */ + __outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, OrgReadMap); + __outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_BIT_MASK); + __outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, OrgBitMask); + __outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, OrgGCAddr); + + /* + * Now, check for the existence of the Chain4 bit. + */ + + /* + * Remember the original states of the Sequencer Address and Memory Mode + * registers. + */ + OrgSCAddr = __inpb(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT); + __outpb(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, IND_MEMORY_MODE); + + /* Read it back... it should be the same */ + if ((__inpb(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT) & SEQ_ADDR_MASK) != IND_MEMORY_MODE) { - /* Fail */ + /* + * Couldn't read back the Sequencer Address register setting + * we just performed, fail. + */ return FALSE; } /* Read sequencer Data */ - SeqReg2 = __inpb(0x3C5); + OrgMemMode = __inpb(VGA_BASE_IO_PORT + SEQ_DATA_PORT); - /* Write null plane */ - __outpw(0x3C4, 0x100); + /* + * Toggle the Chain4 bit and read back the result. This must be done during + * sync reset, since we're changing the chaining state. + */ - /* Select memory mode register */ - __outpb(0x3C4, 4); + /* Begin sync reset */ + __outpw(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, (IND_SYNC_RESET + (START_SYNC_RESET_VALUE << 8))); - /* Write sequencer flag */ - __outpb(0x3C5, SeqReg2 ^ 8); + /* Toggle the Chain4 bit */ + __outpb(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, IND_MEMORY_MODE); + __outpb(VGA_BASE_IO_PORT + SEQ_DATA_PORT, OrgMemMode ^ CHAIN4_MASK); - /* Read it back */ - if (__inpb(0x3C5) != (SeqReg2 ^ 8)) + /* Read it back... it should be the same */ + if (__inpb(VGA_BASE_IO_PORT + SEQ_DATA_PORT) != (OrgMemMode ^ CHAIN4_MASK)) { - /* Not the same value... restore registers and fail */ - __outpb(0x3C5, 2); - __outpw(0x3C4, 0x300); + /* + * Chain4 bit is not there, not a VGA. + * Set text mode default for Memory Mode register. + */ + __outpb(VGA_BASE_IO_PORT + SEQ_DATA_PORT, MEMORY_MODE_TEXT_DEFAULT); + + /* End sync reset */ + __outpw(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, (IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8))); + + /* Fail */ return FALSE; } - /* Now write the registers we read */ - __outpb(0x3C5, SeqReg2); - __outpw(0x3C4, 0x300); - __outpb(0x3C4, SeqReg); + /* + * It's a VGA. + */ + + /* Restore the original Memory Mode setting */ + __outpb(VGA_BASE_IO_PORT + SEQ_DATA_PORT, OrgMemMode); + + /* End sync reset */ + __outpw(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, (IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8))); + + /* Restore the original Sequencer Address setting */ + __outpb(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, OrgSCAddr); /* VGA is present! */ return TRUE; @@ -404,7 +399,7 @@ VidInitialize(IN BOOLEAN SetMode) if (VgaIsPresent()) { /* Translate the VGA Memory Address */ - VgaAddress.LowPart = 0xA0000; + VgaAddress.LowPart = MEM_VGA; VgaAddress.HighPart = 0; AddressSpace = 0; Result = HalFindBusAddressTranslation(VgaAddress, @@ -428,7 +423,7 @@ VidInitialize(IN BOOLEAN SetMode) { /* Map it */ Base = (ULONG_PTR)MmMapIoSpace(TranslatedAddress, - 0x20000, + MEM_VGA_SIZE, MmNonCached); } else @@ -443,13 +438,21 @@ VidInitialize(IN BOOLEAN SetMode) /* Now check if we have to set the mode */ if (SetMode) { - /* Reset the display */ - HalResetDisplay(); + /* Clear the current position */ curr_x = 0; curr_y = 0; - /* Initialize it */ - VgaInterpretCmdStream(AT_Initialization); + /* Reset the display and initialize it */ + if (HalResetDisplay()) + { + /* The HAL handled the display, re-initialize only the AC registers */ + VgaInterpretCmdStream(AT_Initialization); + } + else + { + /* The HAL didn't handle the display, fully re-initialize the VGA */ + VgaInterpretCmdStream(VGA_640x480); + } } /* VGA is ready */ @@ -468,9 +471,16 @@ VidResetDisplay(IN BOOLEAN HalReset) curr_y = 0; /* Clear the screen with HAL if we were asked to */ - if (HalReset) HalResetDisplay(); + if (HalReset) + { + if (!HalResetDisplay()) + { + /* The HAL didn't handle the display, fully re-initialize the VGA */ + VgaInterpretCmdStream(VGA_640x480); + } + } - /* Re-initialize the VGA Display */ + /* Always re-initialize the AC registers */ VgaInterpretCmdStream(AT_Initialization); /* Re-initialize the palette and fill the screen black */ diff --git a/drivers/base/bootvid/i386/vga.c b/drivers/base/bootvid/i386/vga.c index cc2032deaaf..382e825d7ac 100644 --- a/drivers/base/bootvid/i386/vga.c +++ b/drivers/base/bootvid/i386/vga.c @@ -79,13 +79,13 @@ ReadWriteMode(IN UCHAR Mode) UCHAR Value; /* Switch to graphics mode register */ - __outpb(0x3CE, 5); + __outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_GRAPH_MODE); /* Get the current register value, minus the current mode */ - Value = __inpb(0x3CF) & 0xF4; + Value = __inpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT) & 0xF4; /* Set the new mode */ - __outpb(0x3CF, Mode | Value); + __outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, Mode | Value); } FORCEINLINE @@ -100,7 +100,7 @@ SetPixel(IN ULONG Left, PixelPosition = (PUCHAR)(VgaBase + (Left >> 3) + (Top * 80)); /* Select the bitmask register and write the mask */ - __outpw(0x3CE, (PixelMask[Left & 7] << 8) | 8); + __outpw(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, (PixelMask[Left & 7] << 8) | IND_BIT_MASK); /* Read the current pixel value and add our color */ WRITE_REGISTER_UCHAR(PixelPosition, @@ -110,7 +110,7 @@ SetPixel(IN ULONG Left, #define SET_PIXELS(_PixelPtr, _PixelMask, _TextColor) \ do { \ /* Select the bitmask register and write the mask */ \ - __outpw(0x3CE, ((_PixelMask) << 8) | 8); \ + __outpw(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, ((_PixelMask) << 8) | IND_BIT_MASK); \ /* Set the new color */ \ WRITE_REGISTER_UCHAR((_PixelPtr), (UCHAR)(_TextColor)); \ } while (0); @@ -139,10 +139,10 @@ DisplayCharacter(IN CHAR Character, ReadWriteMode(10); /* Clear the 4 planes (we're already in unchained mode here) */ - __outpw(0x3C4, 0xF02); + __outpw(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, 0x0F02); /* Select the color don't care register */ - __outpw(0x3CE, 7); + __outpw(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, 7); /* Calculate shift */ Shift = Left & 7; @@ -252,12 +252,12 @@ SetPaletteEntryRGB(IN ULONG Id, PCHAR Colors = (PCHAR)&Rgb; /* Set the palette index */ - __outpb(0x3C8, (UCHAR)Id); + __outpb(VGA_BASE_IO_PORT + DAC_ADDRESS_WRITE_PORT, (UCHAR)Id); /* Set RGB colors */ - __outpb(0x3C9, Colors[2] >> 2); - __outpb(0x3C9, Colors[1] >> 2); - __outpb(0x3C9, Colors[0] >> 2); + __outpb(VGA_BASE_IO_PORT + DAC_DATA_REG_PORT, Colors[2] >> 2); + __outpb(VGA_BASE_IO_PORT + DAC_DATA_REG_PORT, Colors[1] >> 2); + __outpb(VGA_BASE_IO_PORT + DAC_DATA_REG_PORT, Colors[0] >> 2); } static VOID @@ -282,12 +282,12 @@ SetPaletteEntry(IN ULONG Id, IN ULONG PaletteEntry) { /* Set the palette index */ - __outpb(0x3C8, (UCHAR)Id); + __outpb(VGA_BASE_IO_PORT + DAC_ADDRESS_WRITE_PORT, (UCHAR)Id); /* Set RGB colors */ - __outpb(0x3C9, PaletteEntry & 0xFF); - __outpb(0x3C9, (PaletteEntry >>= 8) & 0xFF); - __outpb(0x3C9, (PaletteEntry >> 8) & 0xFF); + __outpb(VGA_BASE_IO_PORT + DAC_DATA_REG_PORT, PaletteEntry & 0xFF); + __outpb(VGA_BASE_IO_PORT + DAC_DATA_REG_PORT, (PaletteEntry >>= 8) & 0xFF); + __outpb(VGA_BASE_IO_PORT + DAC_DATA_REG_PORT, (PaletteEntry >> 8) & 0xFF); } VOID @@ -324,10 +324,10 @@ VgaScroll(IN ULONG Scroll) PUCHAR OldPosition, NewPosition; /* Clear the 4 planes */ - __outpw(0x3C4, 0xF02); + __outpw(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, 0x0F02); /* Set the bitmask to 0xFF for all 4 planes */ - __outpw(0x3CE, 0xFF08); + __outpw(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, 0xFF08); /* Set Mode 1 */ ReadWriteMode(1); @@ -365,10 +365,10 @@ PreserveRow(IN ULONG CurrentTop, ULONG Count; /* Clear the 4 planes */ - __outpw(0x3C4, 0xF02); + __outpw(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, 0x0F02); /* Set the bitmask to 0xFF for all 4 planes */ - __outpw(0x3CE, 0xFF08); + __outpw(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, 0xFF08); /* Set Mode 1 */ ReadWriteMode(1); @@ -443,10 +443,10 @@ BitBlt(IN ULONG Left, ReadWriteMode(10); /* Clear the 4 planes (we're already in unchained mode here) */ - __outpw(0x3C4, 0xF02); + __outpw(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, 0x0F02); /* Select the color don't care register */ - __outpw(0x3CE, 7); + __outpw(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, 7); /* 4bpp blitting */ dy = Top; @@ -491,10 +491,10 @@ RleBitBlt(IN ULONG Left, ReadWriteMode(10); /* Clear the 4 planes (we're already in unchained mode here) */ - __outpw(0x3C4, 0xF02); + __outpw(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, 0x0F02); /* Select the color don't care register */ - __outpw(0x3CE, 7); + __outpw(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, 7); /* Set Y height and current X value and start loop */ YDelta = Top + Height - 1; @@ -743,11 +743,9 @@ VOID NTAPI VidCleanUp(VOID) { - /* Select bit mask register */ - __outpb(0x3CE, 8); - - /* Clear it */ - __outpb(0x3CF, 255); + /* Select bit mask register and clear it */ + __outpb(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, IND_BIT_MASK); + __outpb(VGA_BASE_IO_PORT + GRAPH_DATA_PORT, BIT_MASK_DEFAULT); } /* @@ -982,7 +980,7 @@ VidScreenToBufferBlt(IN PUCHAR Buffer, ReadWriteMode(0); /* Set the current plane */ - __outpw(0x3CE, (Plane << 8) | 4); + __outpw(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, (Plane << 8) | IND_READ_MAP); /* Make sure we have a height */ if (Height > 0) @@ -1056,9 +1054,9 @@ VidSolidColorFill(IN ULONG Left, /* Get the left and right masks, shifts, and delta */ LeftOffset = Left >> 3; - lMask = (lMaskTable[Left & 0x7] << 8) | 8; + lMask = (lMaskTable[Left & 0x7] << 8) | IND_BIT_MASK; RightOffset = Right >> 3; - rMask = (rMaskTable[Right & 0x7] << 8) | 8; + rMask = (rMaskTable[Right & 0x7] << 8) | IND_BIT_MASK; Distance = RightOffset - LeftOffset; /* If there is no distance, then combine the right and left masks */ @@ -1068,16 +1066,16 @@ VidSolidColorFill(IN ULONG Left, ReadWriteMode(10); /* Clear the 4 planes (we're already in unchained mode here) */ - __outpw(0x3C4, 0xF02); + __outpw(VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, 0x0F02); /* Select the color don't care register */ - __outpw(0x3CE, 7); + __outpw(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, 7); /* Calculate pixel position for the read */ Offset = (PUCHAR)(VgaBase + (Top * 80) + LeftOffset); /* Select the bitmask register and write the mask */ - __outpw(0x3CE, (USHORT)lMask); + __outpw(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, (USHORT)lMask); /* Check if the top coord is below the bottom one */ if (Top <= Bottom) @@ -1102,7 +1100,7 @@ VidSolidColorFill(IN ULONG Left, Distance--; /* Select the bitmask register and write the mask */ - __outpw(0x3CE, (USHORT)rMask); + __outpw(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, (USHORT)rMask); /* Check if the top coord is below the bottom one */ if (Top <= Bottom) @@ -1127,7 +1125,7 @@ VidSolidColorFill(IN ULONG Left, Offset = (PUCHAR)(VgaBase + (Top * 80) + LeftOffset + 1); /* Set the bitmask to 0xFF for all 4 planes */ - __outpw(0x3CE, 0xFF08); + __outpw(VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, 0xFF08); /* Check if the top coord is below the bottom one */ if (Top <= Bottom) diff --git a/drivers/base/bootvid/precomp.h b/drivers/base/bootvid/precomp.h index 087a6bbf575..407447e762b 100644 --- a/drivers/base/bootvid/precomp.h +++ b/drivers/base/bootvid/precomp.h @@ -1,7 +1,6 @@ #ifndef _BOOTVID_PCH_ #define _BOOTVID_PCH_ -#include <ntddk.h> #include <ntifs.h> #include <ndk/halfuncs.h> #include <drivers/bootvid/bootvid.h> @@ -11,11 +10,9 @@ #define BOOTCHAR_HEIGHT 13 -/* Command Stream Definitions */ -#define CMD_STREAM_WRITE 0x0 -#define CMD_STREAM_WRITE_ARRAY 0x2 -#define CMD_STREAM_USHORT 0x4 -#define CMD_STREAM_READ 0x8 +#ifndef _M_ARM +#include "vga.h" +#endif /* _M_ARM */ /* Bitmap Header */ typedef struct tagBITMAPINFOHEADER @@ -42,11 +39,14 @@ NTAPI InitializePalette(VOID); /* Globals */ +#ifndef _M_ARM extern ULONG curr_x; extern ULONG curr_y; extern ULONG_PTR VgaRegisterBase; extern ULONG_PTR VgaBase; extern USHORT AT_Initialization[]; +extern USHORT VGA_640x480[]; +#endif /* _M_ARM */ extern UCHAR FontData[256 * BOOTCHAR_HEIGHT]; #define __inpb(Port) \ diff --git a/drivers/base/bootvid/vga.h b/drivers/base/bootvid/vga.h new file mode 100644 index 00000000000..573106e89ee --- /dev/null +++ b/drivers/base/bootvid/vga.h @@ -0,0 +1,220 @@ +/* + * PROJECT: ReactOS VGA Miniport Driver + * LICENSE: Microsoft NT4 DDK Sample Code License + * PURPOSE: Definitions for VGA + * PROGRAMMERS: Copyright (c) 1992 Microsoft Corporation + * ReactOS Portable Systems Group + */ + +#ifndef _BOOTVID_VGA_H_ +#define _BOOTVID_VGA_H_ + +#pragma once + +#include "cmdcnst.h" + +// +// Base address of VGA memory range. Also used as base address of VGA +// memory when loading a font, which is done with the VGA mapped at A0000. +// + +#define MEM_VGA 0xA0000 +#define MEM_VGA_SIZE 0x20000 + +// +// For memory mapped IO +// + +#define MEMORY_MAPPED_IO_OFFSET (0xB8000 - 0xA0000) + +// +// Port definitions for filling the ACCESS_RANGES structure in the miniport +// information, defines the range of I/O ports the VGA spans. +// There is a break in the IO ports - a few ports are used for the parallel +// port. Those cannot be defined in the ACCESS_RANGE, but are still mapped +// so all VGA ports are in one address range. +// + +#define VGA_BASE_IO_PORT 0x000003B0 +#define VGA_START_BREAK_PORT 0x000003BB +#define VGA_END_BREAK_PORT 0x000003C0 +#define VGA_MAX_IO_PORT 0x000003DF + +// +// VGA register definitions +// +// eVb: 3.1 [VGA] - Use offsets from the VGA Port Address instead of absolute +#define CRTC_ADDRESS_PORT_MONO 0x0004 // CRT Controller Address and +#define CRTC_DATA_PORT_MONO 0x0005 // Data registers in mono mode +#define FEAT_CTRL_WRITE_PORT_MONO 0x000A // Feature Control write port + // in mono mode +#define INPUT_STATUS_1_MONO 0x000A // Input Status 1 register read + // port in mono mode +#define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO + // Register to read to reset + // Attribute Controller index/data + +#define ATT_ADDRESS_PORT 0x0010 // Attribute Controller Address and +#define ATT_DATA_WRITE_PORT 0x0010 // Data registers share one port + // for writes, but only Address is + // readable at 0x3C0 +#define ATT_DATA_READ_PORT 0x0011 // Attribute Controller Data reg is + // readable here +#define MISC_OUTPUT_REG_WRITE_PORT 0x0012 // Miscellaneous Output reg write + // port +#define INPUT_STATUS_0_PORT 0x0012 // Input Status 0 register read + // port +#define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 // Bit 0 enables/disables the + // entire VGA subsystem +#define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address and +#define SEQ_DATA_PORT 0x0015 // Data registers +#define DAC_PIXEL_MASK_PORT 0x0016 // DAC pixel mask reg +#define DAC_ADDRESS_READ_PORT 0x0017 // DAC register read index reg, + // write-only +#define DAC_STATE_PORT 0x0017 // DAC state (read/write), + // read-only +#define DAC_ADDRESS_WRITE_PORT 0x0018 // DAC register write index reg +#define DAC_DATA_REG_PORT 0x0019 // DAC data transfer reg +#define FEAT_CTRL_READ_PORT 0x001A // Feature Control read port +#define MISC_OUTPUT_REG_READ_PORT 0x001C // Miscellaneous Output reg read + // port +#define GRAPH_ADDRESS_PORT 0x001E // Graphics Controller Address +#define GRAPH_DATA_PORT 0x001F // and Data registers + +#define CRTC_ADDRESS_PORT_COLOR 0x0024 // CRT Controller Address and +#define CRTC_DATA_PORT_COLOR 0x0025 // Data registers in color mode +#define FEAT_CTRL_WRITE_PORT_COLOR 0x002A // Feature Control write port +#define INPUT_STATUS_1_COLOR 0x002A // Input Status 1 register read + // port in color mode +// eVb: 3.2 [END] +#define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR + // Register to read to reset + // Attribute Controller index/data + // toggle in color mode + +// +// VGA indexed register indexes. +// + +#define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start +#define IND_CURSOR_END 0x0B // and End registers +#define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location +#define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers +#define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync + // End register, which has the bit + // that protects/unprotects CRTC + // index registers 0-7 +#define IND_CR2C 0x2C // Nordic LCD Interface Register +#define IND_CR2D 0x2D // Nordic LCD Display Control +#define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC +#define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC +#define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr +#define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr +#define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr +#define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr +#define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq +#define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer +#define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq +#define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in + // CRTC +#define IND_CRTC_COMPAT 0x34 // index of CRTC Compatibility reg + // in CRTC +#define IND_PERF_TUNING 0x16 // index of performance tuning in Seq +#define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start + // synchronous reset +#define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end + // synchronous reset + +// +// Values for Attribute Controller Index register to turn video off +// and on, by setting bit 5 to 0 (off) or 1 (on). +// + +#define VIDEO_DISABLE 0 +#define VIDEO_ENABLE 0x20 + +#define INDEX_ENABLE_AUTO_START 0x31 + +// Masks to keep only the significant bits of the Graphics Controller and +// Sequencer Address registers. Masking is necessary because some VGAs, such +// as S3-based ones, don't return unused bits set to 0, and some SVGAs use +// these bits if extensions are enabled. +// + +#define GRAPH_ADDR_MASK 0x0F +#define SEQ_ADDR_MASK 0x07 + +// +// Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register. +// + +#define CHAIN4_MASK 0x08 + +// +// Value written to the Read Map register when identifying the existence of +// a VGA in VgaInitialize. This value must be different from the final test +// value written to the Bit Mask in that routine. +// + +#define READ_MAP_TEST_SETTING 0x03 + +// +// Default text mode setting for various registers, used to restore their +// states if VGA detection fails after they've been modified. +// + +#define MEMORY_MODE_TEXT_DEFAULT 0x02 +#define BIT_MASK_DEFAULT 0xFF +#define READ_MAP_DEFAULT 0x00 + + +// +// Palette-related info. +// + +// +// Highest valid DAC color register index. +// + +#define VIDEO_MAX_COLOR_REGISTER 0xFF + +// +// Highest valid palette register index +// + +#define VIDEO_MAX_PALETTE_REGISTER 0x0F + +// +// Mode into which to put the VGA before starting a VDM, so it's a plain +// vanilla VGA. (This is the mode's index in ModesVGA[], currently standard +// 80x25 text mode.) +// + +#define DEFAULT_MODE 0 + +// +// Number of bytes to save in each plane. +// + +#define VGA_PLANE_SIZE 0x10000 + +// +// Number of each type of indexed register in a standard VGA, used by +// validator and state save/restore functions. +// +// Note: VDMs currently only support basic VGAs only. +// + +#define VGA_NUM_SEQUENCER_PORTS 5 +#define VGA_NUM_CRTC_PORTS 25 +#define VGA_NUM_GRAPH_CONT_PORTS 9 +#define VGA_NUM_ATTRIB_CONT_PORTS 21 +#define VGA_NUM_DAC_ENTRIES 256 + +#define EXT_NUM_GRAPH_CONT_PORTS 0 +#define EXT_NUM_SEQUENCER_PORTS 0 +#define EXT_NUM_CRTC_PORTS 0 +#define EXT_NUM_ATTRIB_CONT_PORTS 0 +#define EXT_NUM_DAC_ENTRIES 0 + +#endif /* _BOOTVID_VGA_H_ */

1 0

[reactos] 01/01: [INFLIB] Fix INFCONTEXT structure to be compatible with the official definition (#1603)
by Timo Kreuzer 23 Jun '19

23 Jun '19

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=a75e4db855059604ef299… commit a75e4db855059604ef29989a2fa5b8e75189cf8c Author: Timo Kreuzer <timo.kreuzer(a)reactos.org> AuthorDate: Sun Jun 23 22:35:19 2019 +0200 Commit: GitHub <noreply(a)github.com> CommitDate: Sun Jun 23 22:35:19 2019 +0200 [INFLIB] Fix INFCONTEXT structure to be compatible with the official definition (#1603) * [INFLIB] Fix INFCONTEXT structure to be compatible with the official definition. This makes inflib work on x64. --- sdk/lib/inflib/infcore.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++ sdk/lib/inflib/infget.c | 62 +++++++++++++++++++++++------------------- sdk/lib/inflib/infpriv.h | 14 ++++++++-- sdk/lib/inflib/infput.c | 30 ++++++++++++++------- 4 files changed, 136 insertions(+), 40 deletions(-) diff --git a/sdk/lib/inflib/infcore.c b/sdk/lib/inflib/infcore.c index 7e187359e2a..7618f9e2401 100644 --- a/sdk/lib/inflib/infcore.c +++ b/sdk/lib/inflib/infcore.c @@ -191,6 +191,7 @@ InfpAddSection(PINFCACHE Cache, } ZEROMEMORY (Section, Size); + Section->Id = ++Cache->NextSectionId; /* Copy section name */ strcpyW(Section->Name, Name); @@ -231,6 +232,7 @@ InfpAddLine(PINFCACHESECTION Section) } ZEROMEMORY(Line, sizeof(INFCACHELINE)); + Line->Id = ++Section->NextLineId; /* Append line */ if (Section->FirstLine == NULL) @@ -249,6 +251,74 @@ InfpAddLine(PINFCACHESECTION Section) return Line; } +PINFCACHESECTION +InfpFindSectionById(PINFCACHE Cache, UINT Id) +{ + PINFCACHESECTION Section; + + for (Section = Cache->FirstSection; + Section != NULL; + Section = Section->Next) + { + if (Section->Id == Id) + { + return Section; + } + } + + return NULL; +} + +PINFCACHESECTION +InfpGetSectionForContext(PINFCONTEXT Context) +{ + PINFCACHE Cache; + + if (Context == NULL) + { + return NULL; + } + + Cache = (PINFCACHE)Context->Inf; + if (Cache == NULL) + { + return NULL; + } + + return InfpFindSectionById(Cache, Context->Section); +} + +PINFCACHELINE +InfpFindLineById(PINFCACHESECTION Section, UINT Id) +{ + PINFCACHELINE Line; + + for (Line = Section->FirstLine; + Line != NULL; + Line = Line->Next) + { + if (Line->Id == Id) + { + return Line; + } + } + + return NULL; +} + +PINFCACHELINE +InfpGetLineForContext(PINFCONTEXT Context) +{ + PINFCACHESECTION Section; + + Section = InfpGetSectionForContext(Context); + if (Section == NULL) + { + return NULL; + } + + return InfpFindLineById(Section, Context->Line); +} PVOID InfpAddKeyToLine(PINFCACHELINE Line, diff --git a/sdk/lib/inflib/infget.c b/sdk/lib/inflib/infget.c index 70b3473ff83..b1f963ea7c9 100644 --- a/sdk/lib/inflib/infget.c +++ b/sdk/lib/inflib/infget.c @@ -213,8 +213,8 @@ InfpFindFirstLine(PINFCACHE Cache, return INF_STATUS_NO_MEMORY; } (*Context)->Inf = (PVOID)Cache; - (*Context)->Section = (PVOID)CacheSection; - (*Context)->Line = (PVOID)CacheLine; + (*Context)->Section = CacheSection->Id; + (*Context)->Line = CacheLine->Id; return INF_STATUS_SUCCESS; } @@ -229,10 +229,10 @@ InfpFindNextLine(PINFCONTEXT ContextIn, if (ContextIn == NULL || ContextOut == NULL) return INF_STATUS_INVALID_PARAMETER; - if (ContextIn->Line == NULL) + CacheLine = InfpGetLineForContext(ContextIn); + if (CacheLine == NULL) return INF_STATUS_INVALID_PARAMETER; - CacheLine = (PINFCACHELINE)ContextIn->Line; if (CacheLine->Next == NULL) return INF_STATUS_NOT_FOUND; @@ -241,7 +241,7 @@ InfpFindNextLine(PINFCONTEXT ContextIn, ContextOut->Inf = ContextIn->Inf; ContextOut->Section = ContextIn->Section; } - ContextOut->Line = (PVOID)(CacheLine->Next); + ContextOut->Line = CacheLine->Next->Id; return INF_STATUS_SUCCESS; } @@ -252,15 +252,17 @@ InfpFindFirstMatchLine(PINFCONTEXT ContextIn, PCWSTR Key, PINFCONTEXT ContextOut) { + PINFCACHESECTION Section; PINFCACHELINE CacheLine; if (ContextIn == NULL || ContextOut == NULL || Key == NULL || *Key == 0) return INF_STATUS_INVALID_PARAMETER; - if (ContextIn->Inf == NULL || ContextIn->Section == NULL) - return INF_STATUS_INVALID_PARAMETER; + Section = InfpGetSectionForContext(ContextIn); + if (Section == NULL) + return INF_STATUS_INVALID_PARAMETER; - CacheLine = ((PINFCACHESECTION)(ContextIn->Section))->FirstLine; + CacheLine = Section->FirstLine; while (CacheLine != NULL) { if (CacheLine->Key != NULL && strcmpiW (CacheLine->Key, Key) == 0) @@ -271,7 +273,7 @@ InfpFindFirstMatchLine(PINFCONTEXT ContextIn, ContextOut->Inf = ContextIn->Inf; ContextOut->Section = ContextIn->Section; } - ContextOut->Line = (PVOID)CacheLine; + ContextOut->Line = CacheLine->Id; return INF_STATUS_SUCCESS; } @@ -288,15 +290,17 @@ InfpFindNextMatchLine(PINFCONTEXT ContextIn, PCWSTR Key, PINFCONTEXT ContextOut) { + PINFCACHESECTION Section; PINFCACHELINE CacheLine; if (ContextIn == NULL || ContextOut == NULL || Key == NULL || *Key == 0) return INF_STATUS_INVALID_PARAMETER; - if (ContextIn->Inf == NULL || ContextIn->Section == NULL || ContextIn->Line == NULL) - return INF_STATUS_INVALID_PARAMETER; + Section = InfpGetSectionForContext(ContextIn); + if (Section == NULL) + return INF_STATUS_INVALID_PARAMETER; - CacheLine = (PINFCACHELINE)ContextIn->Line; + CacheLine = InfpGetLineForContext(ContextIn); while (CacheLine != NULL) { if (CacheLine->Key != NULL && strcmpiW (CacheLine->Key, Key) == 0) @@ -307,7 +311,7 @@ InfpFindNextMatchLine(PINFCONTEXT ContextIn, ContextOut->Inf = ContextIn->Inf; ContextOut->Section = ContextIn->Section; } - ContextOut->Line = (PVOID)CacheLine; + ContextOut->Line = CacheLine->Id; return INF_STATUS_SUCCESS; } @@ -360,10 +364,12 @@ InfpGetLineCount(HINF InfHandle, LONG InfpGetFieldCount(PINFCONTEXT Context) { - if (Context == NULL || Context->Line == NULL) - return 0; + PINFCACHELINE Line; - return ((PINFCACHELINE)Context->Line)->FieldCount; + Line = InfpGetLineForContext(Context); + if (Line == NULL) + return 0; + return Line->FieldCount; } @@ -380,7 +386,7 @@ InfpGetBinaryField(PINFCONTEXT Context, ULONG Size; PUCHAR Ptr; - if (Context == NULL || Context->Line == NULL || FieldIndex == 0) + if (Context == NULL || FieldIndex == 0) { DPRINT("Invalid parameter\n"); return INF_STATUS_INVALID_PARAMETER; @@ -389,7 +395,7 @@ InfpGetBinaryField(PINFCONTEXT Context, if (RequiredSize != NULL) *RequiredSize = 0; - CacheLine = (PINFCACHELINE)Context->Line; + CacheLine = InfpGetLineForContext(Context); if (FieldIndex > (ULONG)CacheLine->FieldCount) return INF_STATUS_NOT_FOUND; @@ -433,13 +439,13 @@ InfpGetIntField(PINFCONTEXT Context, ULONG Index; PWCHAR Ptr; - if (Context == NULL || Context->Line == NULL || IntegerValue == NULL) + if (Context == NULL || IntegerValue == NULL) { DPRINT("Invalid parameter\n"); return INF_STATUS_INVALID_PARAMETER; } - CacheLine = (PINFCACHELINE)Context->Line; + CacheLine = InfpGetLineForContext(Context); if (FieldIndex > (ULONG)CacheLine->FieldCount) { @@ -480,7 +486,7 @@ InfpGetMultiSzField(PINFCONTEXT Context, ULONG Size; PWCHAR Ptr; - if (Context == NULL || Context->Line == NULL || FieldIndex == 0) + if (Context == NULL || FieldIndex == 0) { DPRINT("Invalid parameter\n"); return INF_STATUS_INVALID_PARAMETER; @@ -489,7 +495,7 @@ InfpGetMultiSzField(PINFCONTEXT Context, if (RequiredSize != NULL) *RequiredSize = 0; - CacheLine = (PINFCACHELINE)Context->Line; + CacheLine = InfpGetLineForContext(Context); if (FieldIndex > (ULONG)CacheLine->FieldCount) return INF_STATUS_INVALID_PARAMETER; @@ -548,7 +554,7 @@ InfpGetStringField(PINFCONTEXT Context, PWCHAR Ptr; SIZE_T Size; - if (Context == NULL || Context->Line == NULL) + if (Context == NULL) { DPRINT("Invalid parameter\n"); return INF_STATUS_INVALID_PARAMETER; @@ -557,7 +563,7 @@ InfpGetStringField(PINFCONTEXT Context, if (RequiredSize != NULL) *RequiredSize = 0; - CacheLine = (PINFCACHELINE)Context->Line; + CacheLine = InfpGetLineForContext(Context); if (FieldIndex > (ULONG)CacheLine->FieldCount) return INF_STATUS_INVALID_PARAMETER; @@ -607,13 +613,13 @@ InfpGetData(PINFCONTEXT Context, { PINFCACHELINE CacheKey; - if (Context == NULL || Context->Line == NULL || Data == NULL) + if (Context == NULL || Data == NULL) { DPRINT("Invalid parameter\n"); return INF_STATUS_INVALID_PARAMETER; } - CacheKey = (PINFCACHELINE)Context->Line; + CacheKey = InfpGetLineForContext(Context); if (Key != NULL) *Key = CacheKey->Key; @@ -642,13 +648,13 @@ InfpGetDataField(PINFCONTEXT Context, PINFCACHEFIELD CacheField; ULONG Index; - if (Context == NULL || Context->Line == NULL || Data == NULL) + if (Context == NULL || Data == NULL) { DPRINT("Invalid parameter\n"); return INF_STATUS_INVALID_PARAMETER; } - CacheLine = (PINFCACHELINE)Context->Line; + CacheLine = InfpGetLineForContext(Context); if (FieldIndex > (ULONG)CacheLine->FieldCount) return INF_STATUS_INVALID_PARAMETER; diff --git a/sdk/lib/inflib/infpriv.h b/sdk/lib/inflib/infpriv.h index 1df8bb4d065..a91a1ae5a07 100644 --- a/sdk/lib/inflib/infpriv.h +++ b/sdk/lib/inflib/infpriv.h @@ -30,6 +30,7 @@ typedef struct _INFCACHELINE { struct _INFCACHELINE *Next; struct _INFCACHELINE *Prev; + UINT Id; LONG FieldCount; @@ -47,8 +48,10 @@ typedef struct _INFCACHESECTION PINFCACHELINE FirstLine; PINFCACHELINE LastLine; + UINT Id; LONG LineCount; + UINT NextLineId; WCHAR Name[1]; } INFCACHESECTION, *PINFCACHESECTION; @@ -58,6 +61,7 @@ typedef struct _INFCACHE LANGID LanguageId; PINFCACHESECTION FirstSection; PINFCACHESECTION LastSection; + UINT NextSectionId; PINFCACHESECTION StringsSection; } INFCACHE, *PINFCACHE; @@ -66,8 +70,8 @@ typedef struct _INFCONTEXT { PINFCACHE Inf; PINFCACHE CurrentInf; - PINFCACHESECTION Section; - PINFCACHELINE Line; + UINT Section; + UINT Line; } INFCONTEXT; typedef int INFSTATUS; @@ -142,5 +146,11 @@ extern INFSTATUS InfpAddLineWithKey(PINFCONTEXT Context, PCWSTR Key); extern INFSTATUS InfpAddField(PINFCONTEXT Context, PCWSTR Data); extern VOID InfpFreeContext(PINFCONTEXT Context); +PINFCACHELINE +InfpFindLineById(PINFCACHESECTION Section, UINT Id); +PINFCACHESECTION +InfpGetSectionForContext(PINFCONTEXT Context); +PINFCACHELINE +InfpGetLineForContext(PINFCONTEXT Context); /* EOF */ diff --git a/sdk/lib/inflib/infput.c b/sdk/lib/inflib/infput.c index c049f3fdcf5..7661582659c 100644 --- a/sdk/lib/inflib/infput.c +++ b/sdk/lib/inflib/infput.c @@ -191,6 +191,7 @@ InfpFindOrAddSection(PINFCACHE Cache, PCWSTR Section, PINFCONTEXT *Context) { + PINFCACHESECTION CacheSection; DPRINT("InfpFindOrAddSection section %S\n", Section); *Context = MALLOC(sizeof(INFCONTEXT)); @@ -201,13 +202,13 @@ InfpFindOrAddSection(PINFCACHE Cache, } (*Context)->Inf = Cache; - (*Context)->Section = InfpFindSection(Cache, Section); - (*Context)->Line = NULL; - if (NULL == (*Context)->Section) + (*Context)->Line = 0; + CacheSection = InfpFindSection(Cache, Section); + if (NULL == CacheSection) { DPRINT("Section not found, creating it\n"); - (*Context)->Section = InfpAddSection(Cache, Section); - if (NULL == (*Context)->Section) + CacheSection = InfpAddSection(Cache, Section); + if (NULL == CacheSection) { DPRINT("Failed to create section\n"); FREE(*Context); @@ -215,26 +216,32 @@ InfpFindOrAddSection(PINFCACHE Cache, } } + (*Context)->Section = CacheSection->Id; return INF_STATUS_SUCCESS; } INFSTATUS InfpAddLineWithKey(PINFCONTEXT Context, PCWSTR Key) { + PINFCACHESECTION Section; + PINFCACHELINE Line; + if (NULL == Context) { DPRINT1("Invalid parameter\n"); return INF_STATUS_INVALID_PARAMETER; } - Context->Line = InfpAddLine(Context->Section); - if (NULL == Context->Line) + Section = InfpGetSectionForContext(Context); + Line = InfpAddLine(Section); + if (NULL == Line) { DPRINT("Failed to create line\n"); return INF_STATUS_NO_MEMORY; } + Context->Line = Line->Id; - if (NULL != Key && NULL == InfpAddKeyToLine(Context->Line, Key)) + if (NULL != Key && NULL == InfpAddKeyToLine(Line, Key)) { DPRINT("Failed to add key\n"); return INF_STATUS_NO_MEMORY; @@ -246,13 +253,16 @@ InfpAddLineWithKey(PINFCONTEXT Context, PCWSTR Key) INFSTATUS InfpAddField(PINFCONTEXT Context, PCWSTR Data) { - if (NULL == Context || NULL == Context->Line) + PINFCACHELINE Line; + + if (NULL == Context) { DPRINT1("Invalid parameter\n"); return INF_STATUS_INVALID_PARAMETER; } - if (NULL == InfpAddFieldToLine(Context->Line, Data)) + Line = InfpGetLineForContext(Context); + if (NULL == InfpAddFieldToLine(Line, Data)) { DPRINT("Failed to add field\n"); return INF_STATUS_NO_MEMORY;

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[reactos] 01/01: [SETUPAPI][UMPNPMGR] PNP_UnregisterNotification: Add 2 unknown parameters
by Eric Kohl 23 Jun '19

23 Jun '19

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=a9c4c079553f43a3206e4… commit a9c4c079553f43a3206e4fb7a8b16633c1db4fcb Author: Eric Kohl <eric.kohl(a)reactos.org> AuthorDate: Sun Jun 23 21:45:54 2019 +0200 Commit: Eric Kohl <eric.kohl(a)reactos.org> CommitDate: Sun Jun 23 21:45:54 2019 +0200 [SETUPAPI][UMPNPMGR] PNP_UnregisterNotification: Add 2 unknown parameters --- base/services/umpnpmgr/rpcserver.c | 7 +++++-- dll/win32/setupapi/cfgmgr.c | 2 ++ sdk/include/reactos/idl/pnp.idl | 2 ++ 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/base/services/umpnpmgr/rpcserver.c b/base/services/umpnpmgr/rpcserver.c index 422415fd1af..9277aa94c9a 100644 --- a/base/services/umpnpmgr/rpcserver.c +++ b/base/services/umpnpmgr/rpcserver.c @@ -3530,6 +3530,8 @@ DWORD WINAPI PNP_RegisterNotification( handle_t hBinding, + DWORD dwUnknown2, + DWORD dwUnknown3, BYTE *pNotificationFilter, DWORD ulNotificationFilterSize, DWORD ulFlags, @@ -3539,8 +3541,9 @@ PNP_RegisterNotification( PNOTIFY_DATA pNotifyData; #endif - DPRINT1("PNP_RegisterNotification(%p %p %lu 0x%lx %p)\n", - hBinding, pNotificationFilter, ulNotificationFilterSize, ulFlags, pulNotify); + DPRINT1("PNP_RegisterNotification(%p %lx %lx %p %lu 0x%lx %p)\n", + hBinding, dwUnknown2, dwUnknown3, pNotificationFilter, + ulNotificationFilterSize, ulFlags, pulNotify); #if 0 pNotifyData = RtlAllocateHeap(GetProcessHeap(), HEAP_ZERO_MEMORY, sizeof(NOTIFY_DATA)); diff --git a/dll/win32/setupapi/cfgmgr.c b/dll/win32/setupapi/cfgmgr.c index 0037c1dbef3..c0fe4675cb8 100644 --- a/dll/win32/setupapi/cfgmgr.c +++ b/dll/win32/setupapi/cfgmgr.c @@ -634,6 +634,8 @@ CMP_RegisterNotification( RpcTryExcept { ret = PNP_RegisterNotification(BindingHandle, + 0, + 0, (BYTE*)lpvNotificationFilter, ((DEV_BROADCAST_HDR*)lpvNotificationFilter)->dbch_size, ulFlags, diff --git a/sdk/include/reactos/idl/pnp.idl b/sdk/include/reactos/idl/pnp.idl index a4d7b1cac80..bbcf1c196af 100644 --- a/sdk/include/reactos/idl/pnp.idl +++ b/sdk/include/reactos/idl/pnp.idl @@ -875,6 +875,8 @@ interface pnp __stdcall PNP_RegisterNotification( [in] handle_t hBinding, + [in] DWORD dwUnknown2, + [in] DWORD dwUnknown3, [in, size_is(ulNotificationFilterSize)] BYTE *pNotificationFilter, [in] DWORD ulNotificationFilterSize, [in] DWORD ulFlags,

1 0

[reactos] 01/01: [SETUPAPI][UMPNPMGR] Improve CMP_RegisterNotification/PNP_RegisterNotification
by Eric Kohl 23 Jun '19

23 Jun '19

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=ca0406131ccf0dcf2ca40… commit ca0406131ccf0dcf2ca401c54ac33f600ce46af0 Author: Eric Kohl <eric.kohl(a)reactos.org> AuthorDate: Sun Jun 23 19:26:44 2019 +0200 Commit: Eric Kohl <eric.kohl(a)reactos.org> CommitDate: Sun Jun 23 19:31:34 2019 +0200 [SETUPAPI][UMPNPMGR] Improve CMP_RegisterNotification/PNP_RegisterNotification Pass the notification filter to PNP_RegisterNotification as a byte-pointer to the filter and the size of the filter. --- base/services/umpnpmgr/rpcserver.c | 6 ++++-- dll/win32/setupapi/cfgmgr.c | 2 ++ sdk/include/reactos/idl/pnp.idl | 2 ++ 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/base/services/umpnpmgr/rpcserver.c b/base/services/umpnpmgr/rpcserver.c index fc20f0d3355..422415fd1af 100644 --- a/base/services/umpnpmgr/rpcserver.c +++ b/base/services/umpnpmgr/rpcserver.c @@ -3530,6 +3530,8 @@ DWORD WINAPI PNP_RegisterNotification( handle_t hBinding, + BYTE *pNotificationFilter, + DWORD ulNotificationFilterSize, DWORD ulFlags, DWORD *pulNotify) { @@ -3537,8 +3539,8 @@ PNP_RegisterNotification( PNOTIFY_DATA pNotifyData; #endif - DPRINT1("PNP_RegisterNotification(%p 0x%lx %p)\n", - hBinding, ulFlags, pulNotify); + DPRINT1("PNP_RegisterNotification(%p %p %lu 0x%lx %p)\n", + hBinding, pNotificationFilter, ulNotificationFilterSize, ulFlags, pulNotify); #if 0 pNotifyData = RtlAllocateHeap(GetProcessHeap(), HEAP_ZERO_MEMORY, sizeof(NOTIFY_DATA)); diff --git a/dll/win32/setupapi/cfgmgr.c b/dll/win32/setupapi/cfgmgr.c index 8215d47ac63..0037c1dbef3 100644 --- a/dll/win32/setupapi/cfgmgr.c +++ b/dll/win32/setupapi/cfgmgr.c @@ -634,6 +634,8 @@ CMP_RegisterNotification( RpcTryExcept { ret = PNP_RegisterNotification(BindingHandle, + (BYTE*)lpvNotificationFilter, + ((DEV_BROADCAST_HDR*)lpvNotificationFilter)->dbch_size, ulFlags, &pNotifyData->ulNotifyData); } diff --git a/sdk/include/reactos/idl/pnp.idl b/sdk/include/reactos/idl/pnp.idl index 844c694c1a3..a4d7b1cac80 100644 --- a/sdk/include/reactos/idl/pnp.idl +++ b/sdk/include/reactos/idl/pnp.idl @@ -875,6 +875,8 @@ interface pnp __stdcall PNP_RegisterNotification( [in] handle_t hBinding, + [in, size_is(ulNotificationFilterSize)] BYTE *pNotificationFilter, + [in] DWORD ulNotificationFilterSize, [in] DWORD ulFlags, [out] DWORD *pulNotifyData);

1 0

[reactos] 02/02: [BOOTVID] Fixes for VgaIsPresent() and VidInitialize().
by Hermès Bélusca-Maïto 23 Jun '19

23 Jun '19

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=8f04a09e748ce5c9f3e57… commit 8f04a09e748ce5c9f3e5779d5964aeffa8979eda Author: Hermès Bélusca-Maïto <hermes.belusca-maito(a)reactos.org> AuthorDate: Sun Jun 23 03:03:40 2019 +0200 Commit: Hermès Bélusca-Maïto <hermes.belusca-maito(a)reactos.org> CommitDate: Sun Jun 23 03:07:19 2019 +0200 [BOOTVID] Fixes for VgaIsPresent() and VidInitialize(). - VgaIsPresent(): Re-select the memory mode register before playing around with the sequencer flag. Otherwise the VGA may not be detected correctly from time to time. - VidInitialize(): Simplify the initialization loop, reset AddressSpace to its "default" value of 1 when calling HalFindBusAddressTranslation() on 'NullAddress'. --- drivers/base/bootvid/i386/bootvid.c | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/drivers/base/bootvid/i386/bootvid.c b/drivers/base/bootvid/i386/bootvid.c index 2909b6c4a93..89fc4f4a6ee 100644 --- a/drivers/base/bootvid/i386/bootvid.c +++ b/drivers/base/bootvid/i386/bootvid.c @@ -332,6 +332,9 @@ VgaIsPresent(VOID) /* Write null plane */ __outpw(0x3C4, 0x100); + /* Select memory mode register */ + __outpb(0x3C4, 4); + /* Write sequencer flag */ __outpb(0x3C5, SeqReg2 ^ 8); @@ -365,24 +368,25 @@ VidInitialize(IN BOOLEAN SetMode) ULONG_PTR Context = 0; PHYSICAL_ADDRESS TranslatedAddress; PHYSICAL_ADDRESS NullAddress = {{0, 0}}, VgaAddress; - ULONG AddressSpace = 1; + ULONG AddressSpace; BOOLEAN Result; ULONG_PTR Base; /* Make sure that we have a bus translation function */ if (!HalFindBusAddressTranslation) return FALSE; - /* Get the VGA Register address */ - Result = HalFindBusAddressTranslation(NullAddress, - &AddressSpace, - &TranslatedAddress, - &Context, - TRUE); - if (!Result) return FALSE; - /* Loop trying to find possible VGA base addresses */ while (TRUE) { + /* Get the VGA Register address */ + AddressSpace = 1; + Result = HalFindBusAddressTranslation(NullAddress, + &AddressSpace, + &TranslatedAddress, + &Context, + TRUE); + if (!Result) return FALSE; + /* See if this is I/O Space, which we need to map */ if (!AddressSpace) { @@ -409,20 +413,14 @@ VidInitialize(IN BOOLEAN SetMode) &Context, FALSE); if (Result) break; - - /* Try to see if there's any other address */ - Result = HalFindBusAddressTranslation(NullAddress, - &AddressSpace, - &TranslatedAddress, - &Context, - TRUE); - if (!Result) return FALSE; } else { /* It's not, so unmap the I/O space if we mapped it */ if (!AddressSpace) MmUnmapIoSpace((PVOID)VgaRegisterBase, 0x400); } + + /* Continue trying to see if there's any other address */ } /* Success! See if this is I/O Space, which we need to map */

1 0

[reactos] 01/02: [BOOTVID] Simplify the code by introducing and using IO port helper macros.
by Hermès Bélusca-Maïto 23 Jun '19

23 Jun '19

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=025cfb108bdadda465237… commit 025cfb108bdadda46523750d9859aadd5bce353d Author: Hermès Bélusca-Maïto <hermes.belusca-maito(a)reactos.org> AuthorDate: Sun Jun 23 02:29:01 2019 +0200 Commit: Hermès Bélusca-Maïto <hermes.belusca-maito(a)reactos.org> CommitDate: Sun Jun 23 02:59:43 2019 +0200 [BOOTVID] Simplify the code by introducing and using IO port helper macros. - Move around two header includes. - Remove a redundant assignment in VgaInterpretCmdStream(). --- drivers/base/bootvid/i386/bootvid.c | 101 +++++++++++++++++------------------- drivers/base/bootvid/i386/vga.c | 12 ++--- drivers/base/bootvid/precomp.h | 18 ++++++- 3 files changed, 67 insertions(+), 64 deletions(-) diff --git a/drivers/base/bootvid/i386/bootvid.c b/drivers/base/bootvid/i386/bootvid.c index 333e5de4faa..2909b6c4a93 100644 --- a/drivers/base/bootvid/i386/bootvid.c +++ b/drivers/base/bootvid/i386/bootvid.c @@ -1,8 +1,5 @@ #include "precomp.h" -#include <ntifs.h> -#include <ndk/halfuncs.h> - /* PRIVATE FUNCTIONS *********************************************************/ static BOOLEAN @@ -227,9 +224,6 @@ VgaInterpretCmdStream(IN PUSHORT CmdStream) /* Unknown major function, fail */ return FALSE; } - - /* Get the next command */ - Cmd = *CmdStream; } /* If we got here, return success */ @@ -245,114 +239,115 @@ VgaIsPresent(VOID) UCHAR i; /* Read the VGA Address Register */ - VgaReg = READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE); + VgaReg = __inpb(0x3CE); /* Select Read Map Select Register */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 4); + __outpb(0x3CE, 4); - /* Read it back...it should be 4 */ - if (((READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE)) & 0xF) != 4) return FALSE; + /* Read it back... it should be 4 */ + if ((__inpb(0x3CE) & 0xF) != 4) + return FALSE; /* Read the VGA Data Register */ - VgaReg2 = READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF); + VgaReg2 = __inpb(0x3CF); /* Enable all planes */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 3); + __outpb(0x3CF, 3); - /* Read it back...it should be 3 */ - if (READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF) != 0x3) + /* Read it back... it should be 3 */ + if (__inpb(0x3CF) != 0x3) { /* Reset the registers and fail */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 0); + __outpb(0x3CF, 0); return FALSE; } /* Select Bit Mask Register */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 8); + __outpb(0x3CE, 8); - /* Read it back...it should be 8 */ - if (((READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE)) & 0xF) != 8) + /* Read it back... it should be 8 */ + if ((__inpb(0x3CE) & 0xF) != 8) { /* Reset the registers and fail */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 4); - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 0); + __outpb(0x3CE, 4); + __outpb(0x3CF, 0); return FALSE; } /* Read the VGA Data Register */ - VgaReg3 = READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF); + VgaReg3 = __inpb(0x3CF); /* Loop bitmasks */ for (i = 0xBB; i; i >>= 1) { /* Set bitmask */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, i); + __outpb(0x3CF, i); - /* Read it back...it should be the same */ - if (READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF) != i) + /* Read it back... it should be the same */ + if (__inpb(0x3CF) != i) { /* Reset the registers and fail */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 0xFF); - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 4); - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 0); + __outpb(0x3CF, 0xFF); + __outpb(0x3CE, 4); + __outpb(0x3CF, 0); return FALSE; } } /* Select Read Map Select Register */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 4); + __outpb(0x3CE, 4); - /* Read it back...it should be 3 */ - if (READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF) != 3) + /* Read it back... it should be 3 */ + if (__inpb(0x3CF) != 3) { /* Reset the registers and fail */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 0); - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 8); - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 0xFF); + __outpb(0x3CF, 0); + __outpb(0x3CE, 8); + __outpb(0x3CF, 0xFF); return FALSE; } /* Write the registers we read earlier */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, VgaReg2); - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 8); - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, VgaReg3); - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, VgaReg); + __outpb(0x3CF, VgaReg2); + __outpb(0x3CE, 8); + __outpb(0x3CF, VgaReg3); + __outpb(0x3CE, VgaReg); /* Read sequencer address */ - SeqReg = READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C4); + SeqReg = __inpb(0x3C4); /* Select memory mode register */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C4, 4); + __outpb(0x3C4, 4); - /* Read it back...it should still be 4 */ - if (((READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C4)) & 7) != 4) + /* Read it back... it should still be 4 */ + if ((__inpb(0x3C4) & 7) != 4) { - /* Fail */ + /* Fail */ return FALSE; } /* Read sequencer Data */ - SeqReg2 = READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C5); + SeqReg2 = __inpb(0x3C5); /* Write null plane */ - WRITE_PORT_USHORT((PUSHORT)VgaRegisterBase + 0x3C4, 0x100); + __outpw(0x3C4, 0x100); /* Write sequencer flag */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C5, SeqReg2 ^ 8); + __outpb(0x3C5, SeqReg2 ^ 8); /* Read it back */ - if ((READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C5)) != (SeqReg2 ^ 8)) + if (__inpb(0x3C5) != (SeqReg2 ^ 8)) { - /* Not the same value...restore registers and fail */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C5, 2); - WRITE_PORT_USHORT((PUSHORT)VgaRegisterBase + 0x3C4, 0x300); + /* Not the same value... restore registers and fail */ + __outpb(0x3C5, 2); + __outpw(0x3C4, 0x300); return FALSE; } /* Now write the registers we read */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C5, SeqReg2); - WRITE_PORT_USHORT((PUSHORT)VgaRegisterBase + 0x3C4, 0x300); - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C4, SeqReg); + __outpb(0x3C5, SeqReg2); + __outpw(0x3C4, 0x300); + __outpb(0x3C4, SeqReg); /* VGA is present! */ return TRUE; @@ -458,7 +453,7 @@ VidInitialize(IN BOOLEAN SetMode) /* Initialize it */ VgaInterpretCmdStream(AT_Initialization); } - + /* VGA is ready */ return TRUE; } diff --git a/drivers/base/bootvid/i386/vga.c b/drivers/base/bootvid/i386/vga.c index dcb02837512..cc2032deaaf 100644 --- a/drivers/base/bootvid/i386/vga.c +++ b/drivers/base/bootvid/i386/vga.c @@ -70,12 +70,6 @@ ULONG curr_y = 0; static ULONG VidTextColor = 0xF; static BOOLEAN CarriageReturn = FALSE; -#define __outpb(Port, Value) \ - WRITE_PORT_UCHAR((PUCHAR)(VgaRegisterBase + (Port)), (UCHAR)(Value)) - -#define __outpw(Port, Value) \ - WRITE_PORT_USHORT((PUSHORT)(VgaRegisterBase + (Port)), (USHORT)(Value)) - /* PRIVATE FUNCTIONS *********************************************************/ static VOID @@ -88,7 +82,7 @@ ReadWriteMode(IN UCHAR Mode) __outpb(0x3CE, 5); /* Get the current register value, minus the current mode */ - Value = READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF) & 0xF4; + Value = __inpb(0x3CF) & 0xF4; /* Set the new mode */ __outpb(0x3CF, Mode | Value); @@ -750,10 +744,10 @@ NTAPI VidCleanUp(VOID) { /* Select bit mask register */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 8); + __outpb(0x3CE, 8); /* Clear it */ - WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 255); + __outpb(0x3CF, 255); } /* diff --git a/drivers/base/bootvid/precomp.h b/drivers/base/bootvid/precomp.h index 33fb58c7483..087a6bbf575 100644 --- a/drivers/base/bootvid/precomp.h +++ b/drivers/base/bootvid/precomp.h @@ -2,12 +2,14 @@ #define _BOOTVID_PCH_ #include <ntddk.h> +#include <ntifs.h> +#include <ndk/halfuncs.h> #include <drivers/bootvid/bootvid.h> /* Define if FontData has upside down characters */ #undef CHAR_GEN_UPSIDE_DOWN -#define BOOTCHAR_HEIGHT 13 +#define BOOTCHAR_HEIGHT 13 /* Command Stream Definitions */ #define CMD_STREAM_WRITE 0x0 @@ -40,11 +42,23 @@ NTAPI InitializePalette(VOID); /* Globals */ -extern USHORT AT_Initialization[]; extern ULONG curr_x; extern ULONG curr_y; extern ULONG_PTR VgaRegisterBase; extern ULONG_PTR VgaBase; +extern USHORT AT_Initialization[]; extern UCHAR FontData[256 * BOOTCHAR_HEIGHT]; +#define __inpb(Port) \ + READ_PORT_UCHAR((PUCHAR)(VgaRegisterBase + (Port))) + +#define __inpw(Port) \ + READ_PORT_USHORT((PUSHORT)(VgaRegisterBase + (Port))) + +#define __outpb(Port, Value) \ + WRITE_PORT_UCHAR((PUCHAR)(VgaRegisterBase + (Port)), (UCHAR)(Value)) + +#define __outpw(Port, Value) \ + WRITE_PORT_USHORT((PUSHORT)(VgaRegisterBase + (Port)), (USHORT)(Value)) + #endif /* _BOOTVID_PCH_ */

1 0

[reactos] 03/03: [VGA_NEW] Fix confusion between CRTC Controller and Graphics Controller registers.
by Hermès Bélusca-Maïto 23 Jun '19

23 Jun '19

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=0f3f8b2a35fa58c60214a… commit 0f3f8b2a35fa58c60214a08d4deb6cdc7fa0c5ce Author: Hermès Bélusca-Maïto <hermes.belusca-maito(a)reactos.org> AuthorDate: Sat Jun 22 23:27:26 2019 +0200 Commit: Hermès Bélusca-Maïto <hermes.belusca-maito(a)reactos.org> CommitDate: Sun Jun 23 02:12:24 2019 +0200 [VGA_NEW] Fix confusion between CRTC Controller and Graphics Controller registers. --- win32ss/drivers/miniport/vga_new/vga.h | 1 - win32ss/drivers/miniport/vga_new/vgadata.c | 14 +++++++------- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/win32ss/drivers/miniport/vga_new/vga.h b/win32ss/drivers/miniport/vga_new/vga.h index 792eb031116..56dd52f1289 100644 --- a/win32ss/drivers/miniport/vga_new/vga.h +++ b/win32ss/drivers/miniport/vga_new/vga.h @@ -114,7 +114,6 @@ #define CRTC_ADDRESS_COLOR_OFFSET 0x24 #define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A - // toggle in color mode // // VGA indexed register indexes. // diff --git a/win32ss/drivers/miniport/vga_new/vgadata.c b/win32ss/drivers/miniport/vga_new/vgadata.c index 128ee50044c..dd3bd56c44e 100644 --- a/win32ss/drivers/miniport/vga_new/vgadata.c +++ b/win32ss/drivers/miniport/vga_new/vgadata.c @@ -96,9 +96,9 @@ USHORT VGA_640x480[] = { CRTC_ADDRESS_PORT_COLOR, 0x511, - METAOUT+INDXOUT, // program gdc registers - GRAPH_ADDRESS_PORT, - VGA_NUM_CRTC_PORTS,0, // count, startindex + METAOUT+INDXOUT, // program crtc registers + CRTC_ADDRESS_PORT_COLOR, + VGA_NUM_CRTC_PORTS,0, // count, startindex 0x5F,0x4F,0x50,0x82,0x54,0x80,0x0B,0x3E,0x00,0x40,0x0,0x0,0x0,0x0,0x0,0x0, 0xEA,0x8C,0xDF,0x28,0x0,0xE7,0x4,0xE3,0xFF, @@ -165,8 +165,8 @@ USHORT VGA_TEXT_0[] = { CRTC_ADDRESS_PORT_COLOR, 0xE11, - METAOUT+INDXOUT, // program gdc registers - GRAPH_ADDRESS_PORT, + METAOUT+INDXOUT, // program crtc registers + CRTC_ADDRESS_PORT_COLOR, VGA_NUM_CRTC_PORTS,0, // count, startindex 0x5F,0x4F,0x50,0x82,0x55,0x81,0xBF,0x1F,0x00,0x4F,0xD,0xE,0x0,0x0,0x0,0x0, 0x9c,0x8E,0x8F,0x28,0x1F,0x96,0xB9,0xA3,0xFF, @@ -234,8 +234,8 @@ USHORT VGA_TEXT_1[] = { CRTC_ADDRESS_PORT_COLOR, 0x511, - METAOUT+INDXOUT, // program gdc registers - GRAPH_ADDRESS_PORT, + METAOUT+INDXOUT, // program crtc registers + CRTC_ADDRESS_PORT_COLOR, VGA_NUM_CRTC_PORTS,0, // count, startindex 0x5F,0x4F,0x50,0x82,0x55,0x81,0xBF,0x1F,0x00,0x4D,0xB,0xC,0x0,0x0,0x0,0x0, 0x83,0x85,0x5D,0x28,0x1F,0x63,0xBA,0xA3,0xFF,

1 0

[reactos] 02/03: [NTVDM] Fix whitespace.
by Hermès Bélusca-Maïto 23 Jun '19

23 Jun '19

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=6c5d38c22a7d13ece6979… commit 6c5d38c22a7d13ece6979159fb8a3d026d2684c6 Author: Hermès Bélusca-Maïto <hermes.belusca-maito(a)reactos.org> AuthorDate: Sat Jun 22 23:24:13 2019 +0200 Commit: Hermès Bélusca-Maïto <hermes.belusca-maito(a)reactos.org> CommitDate: Sun Jun 23 02:12:24 2019 +0200 [NTVDM] Fix whitespace. --- subsystems/mvdm/ntvdm/bios/vidbios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsystems/mvdm/ntvdm/bios/vidbios.c b/subsystems/mvdm/ntvdm/bios/vidbios.c index 54ce259c7be..f580f3fb834 100644 --- a/subsystems/mvdm/ntvdm/bios/vidbios.c +++ b/subsystems/mvdm/ntvdm/bios/vidbios.c @@ -232,7 +232,7 @@ static VGA_REGISTERS VideoMode_640x480_16color = 0xE3, /* Sequencer Registers */ - {0x00, 0x01, 0x0F, 0x00, 0x06}, + {0x00, 0x01, 0x0F, 0x00, 0x06}, /* CRTC Registers */ {0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0x0B, 0x3E, 0x00, 0x40, 0x00, 0x00,

1 0

[reactos] 01/03: [WIN32K] Fix spelling typo.
by Hermès Bélusca-Maïto 23 Jun '19

23 Jun '19

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=78d20a9b3a85b7c4d1e10… commit 78d20a9b3a85b7c4d1e108301f5792d42132217f Author: Hermès Bélusca-Maïto <hermes.belusca-maito(a)reactos.org> AuthorDate: Sat Jun 22 23:03:10 2019 +0200 Commit: Hermès Bélusca-Maïto <hermes.belusca-maito(a)reactos.org> CommitDate: Sun Jun 23 02:12:23 2019 +0200 [WIN32K] Fix spelling typo. --- win32ss/gdi/eng/xlateobj.c | 2 +- win32ss/user/ntuser/clipboard.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/win32ss/gdi/eng/xlateobj.c b/win32ss/gdi/eng/xlateobj.c index 53d2cebc71f..2fcdcc1291f 100644 --- a/win32ss/gdi/eng/xlateobj.c +++ b/win32ss/gdi/eng/xlateobj.c @@ -387,7 +387,7 @@ EXLATEOBJ_vInitialize( return; } - /* Check if both of the pallettes are indexed */ + /* Check if both of the palettes are indexed */ if (!(ppalSrc->flFlags & PAL_INDEXED) || !(ppalDst->flFlags & PAL_INDEXED)) { /* At least one palette is not indexed, calculate shifts/masks */ diff --git a/win32ss/user/ntuser/clipboard.c b/win32ss/user/ntuser/clipboard.c index 95f44894a20..d144220a18f 100644 --- a/win32ss/user/ntuser/clipboard.c +++ b/win32ss/user/ntuser/clipboard.c @@ -345,7 +345,7 @@ IntAddSynthesizedFormats(PWINSTATION_OBJECT pWinStaObj) IntAddFormatedData(pWinStaObj, CF_METAFILEPICT, DATA_SYNTH_USER, FALSE, TRUE); /* Note: We need to render the DIB or DIBV5 format as soon as possible - because pallette information may change */ + because palette information may change */ if (!bHaveDib && bHaveBm) IntSynthesizeDib(pWinStaObj, IntGetFormatElement(pWinStaObj, CF_BITMAP)->hData); }

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