Ros-diffs October 2023

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[reactos] 05/06: [NTOS:KE/x64] Use structures for CPUID
by Timo Kreuzer 03 Oct '23

03 Oct '23

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=1a7ab2fe6826f679d67b8… commit 1a7ab2fe6826f679d67b827eb9e872ae7fa5ed98 Author: Timo Kreuzer <timo.kreuzer(a)reactos.org> AuthorDate: Sun Aug 27 12:08:37 2023 +0300 Commit: Timo Kreuzer <timo.kreuzer(a)reactos.org> CommitDate: Tue Oct 3 19:45:44 2023 +0300 [NTOS:KE/x64] Use structures for CPUID --- ntoskrnl/ke/amd64/cpu.c | 67 ++++++++++++++++++++++++++----------------------- 1 file changed, 36 insertions(+), 31 deletions(-) diff --git a/ntoskrnl/ke/amd64/cpu.c b/ntoskrnl/ke/amd64/cpu.c index d5086b950d3..f01784f5b07 100644 --- a/ntoskrnl/ke/amd64/cpu.c +++ b/ntoskrnl/ke/amd64/cpu.c @@ -10,6 +10,7 @@ /* INCLUDES *****************************************************************/ #include <ntoskrnl.h> +#include <x86x64/Cpuid.h> #define NDEBUG #include <debug.h> @@ -152,7 +153,8 @@ KiGetFeatureBits(VOID) PKPRCB Prcb = KeGetCurrentPrcb(); ULONG Vendor; ULONG64 FeatureBits = 0; - CPU_INFO CpuInfo; + CPUID_VERSION_INFO_REGS VersionInfo; + CPUID_EXTENDED_FUNCTION_REGS extendedFunction; /* Get the Vendor ID */ Vendor = Prcb->CpuVendor; @@ -161,38 +163,39 @@ KiGetFeatureBits(VOID) if (!Vendor) return FeatureBits; /* Get the CPUID Info. */ - KiCpuId(&CpuInfo, 1); + __cpuid(VersionInfo.AsInt32, CPUID_VERSION_INFO); /* Set the initial APIC ID */ - Prcb->InitialApicId = (UCHAR)(CpuInfo.Ebx >> 24); + Prcb->InitialApicId = (UCHAR)VersionInfo.Ebx.Bits.InitialLocalApicId; /* Convert all CPUID Feature bits into our format */ - if (CpuInfo.Edx & X86_FEATURE_VME) FeatureBits |= KF_CR4; - if (CpuInfo.Edx & X86_FEATURE_PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4; - if (CpuInfo.Edx & X86_FEATURE_TSC) FeatureBits |= KF_RDTSC; - if (CpuInfo.Edx & X86_FEATURE_CX8) FeatureBits |= KF_CMPXCHG8B; - if (CpuInfo.Edx & X86_FEATURE_SYSCALL) FeatureBits |= KF_FAST_SYSCALL; - if (CpuInfo.Edx & X86_FEATURE_MTTR) FeatureBits |= KF_MTRR; - if (CpuInfo.Edx & X86_FEATURE_PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4; - if (CpuInfo.Edx & X86_FEATURE_CMOV) FeatureBits |= KF_CMOV; - if (CpuInfo.Edx & X86_FEATURE_PAT) FeatureBits |= KF_PAT; - if (CpuInfo.Edx & X86_FEATURE_DS) FeatureBits |= KF_DTS; - if (CpuInfo.Edx & X86_FEATURE_MMX) FeatureBits |= KF_MMX; - if (CpuInfo.Edx & X86_FEATURE_FXSR) FeatureBits |= KF_FXSR; - if (CpuInfo.Edx & X86_FEATURE_SSE) FeatureBits |= KF_XMMI; - if (CpuInfo.Edx & X86_FEATURE_SSE2) FeatureBits |= KF_XMMI64; - - if (CpuInfo.Ecx & X86_FEATURE_SSE3) FeatureBits |= KF_SSE3; - //if (CpuInfo.Ecx & X86_FEATURE_SSSE3) FeatureBits |= KF_SSSE3; - if (CpuInfo.Ecx & X86_FEATURE_CX16) FeatureBits |= KF_CMPXCHG16B; - //if (CpuInfo.Ecx & X86_FEATURE_SSE41) FeatureBits |= KF_SSE4_1; - if (CpuInfo.Ecx & X86_FEATURE_XSAVE) FeatureBits |= KF_XSTATE; + if (VersionInfo.Edx.Bits.VME) FeatureBits |= KF_CR4; + if (VersionInfo.Edx.Bits.PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4; + if (VersionInfo.Edx.Bits.TSC) FeatureBits |= KF_RDTSC; + if (VersionInfo.Edx.Bits.CX8) FeatureBits |= KF_CMPXCHG8B; + if (VersionInfo.Edx.Bits.SEP) FeatureBits |= KF_FAST_SYSCALL; + if (VersionInfo.Edx.Bits.MTRR) FeatureBits |= KF_MTRR; + if (VersionInfo.Edx.Bits.PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4; + if (VersionInfo.Edx.Bits.CMOV) FeatureBits |= KF_CMOV; + if (VersionInfo.Edx.Bits.PAT) FeatureBits |= KF_PAT; + if (VersionInfo.Edx.Bits.DS) FeatureBits |= KF_DTS; + if (VersionInfo.Edx.Bits.MMX) FeatureBits |= KF_MMX; + if (VersionInfo.Edx.Bits.FXSR) FeatureBits |= KF_FXSR; + if (VersionInfo.Edx.Bits.SSE) FeatureBits |= KF_XMMI; + if (VersionInfo.Edx.Bits.SSE2) FeatureBits |= KF_XMMI64; + + if (VersionInfo.Ecx.Bits.SSE3) FeatureBits |= KF_SSE3; + if (VersionInfo.Ecx.Bits.SSSE3) FeatureBits |= KF_SSSE3; + if (VersionInfo.Ecx.Bits.CMPXCHG16B) FeatureBits |= KF_CMPXCHG16B; + if (VersionInfo.Ecx.Bits.SSE4_1) FeatureBits |= KF_SSE4_1; + if (VersionInfo.Ecx.Bits.XSAVE) FeatureBits |= KF_XSTATE; /* Check if the CPU has hyper-threading */ - if (CpuInfo.Edx & X86_FEATURE_HT) + if (VersionInfo.Edx.Bits.HTT) { /* Set the number of logical CPUs */ - Prcb->LogicalProcessorsPerPhysicalProcessor = (UCHAR)(CpuInfo.Ebx >> 16); + Prcb->LogicalProcessorsPerPhysicalProcessor = + VersionInfo.Ebx.Bits.MaximumAddressableIdsForLogicalProcessors; if (Prcb->LogicalProcessorsPerPhysicalProcessor > 1) { /* We're on dual-core */ @@ -206,23 +209,25 @@ KiGetFeatureBits(VOID) } /* Check extended cpuid features */ - KiCpuId(&CpuInfo, 0x80000000); - if ((CpuInfo.Eax & 0xffffff00) == 0x80000000) + __cpuid(extendedFunction.AsInt32, CPUID_EXTENDED_FUNCTION); + if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000) { /* Check if CPUID 0x80000001 is supported */ - if (CpuInfo.Eax >= 0x80000001) + if (extendedFunction.MaxLeaf >= 0x80000001) { + CPUID_EXTENDED_CPU_SIG_REGS extSig; + /* Check which extended features are available. */ - KiCpuId(&CpuInfo, 0x80000001); + __cpuid(extSig.AsInt32, CPUID_EXTENDED_CPU_SIG); /* Check if NX-bit is supported */ - if (CpuInfo.Edx & X86_FEATURE_NX) FeatureBits |= KF_NX_BIT; + if (extSig.Intel.Edx.Bits.NX) FeatureBits |= KF_NX_BIT; /* Now handle each features for each CPU Vendor */ switch (Vendor) { case CPU_AMD: - if (CpuInfo.Edx & 0x80000000) FeatureBits |= KF_3DNOW; + if (extSig.Amd.Edx.Bits.ThreeDNow) FeatureBits |= KF_3DNOW; break; } }

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[reactos] 04/06: [SDK] Add CPUID and MSR definitions for x86/x64
by Timo Kreuzer 03 Oct '23

03 Oct '23

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=6048ebeff9988428b795d… commit 6048ebeff9988428b795d177f1fe3dc9fa6e2470 Author: Timo Kreuzer <timo.kreuzer(a)reactos.org> AuthorDate: Sun Aug 27 11:18:40 2023 +0300 Commit: Timo Kreuzer <timo.kreuzer(a)reactos.org> CommitDate: Tue Oct 3 19:45:44 2023 +0300 [SDK] Add CPUID and MSR definitions for x86/x64 - Import definitions from edk2 (see https://github.com/tianocore/edk2/tree/master/MdePkg/Include/Register) - Add additional unions as well as AMD SVM CPUID --- sdk/include/reactos/x86x64/Amd/Cpuid.h | 733 +++ sdk/include/reactos/x86x64/Cpuid.h | 205 + .../reactos/x86x64/Intel/ArchitecturalMsr.h | 6532 ++++++++++++++++++++ sdk/include/reactos/x86x64/Intel/Cpuid.h | 4083 ++++++++++++ sdk/include/reactos/x86x64/Msr.h | 91 + 5 files changed, 11644 insertions(+) diff --git a/sdk/include/reactos/x86x64/Amd/Cpuid.h b/sdk/include/reactos/x86x64/Amd/Cpuid.h new file mode 100644 index 00000000000..d26b8270b73 --- /dev/null +++ b/sdk/include/reactos/x86x64/Amd/Cpuid.h @@ -0,0 +1,733 @@ +/** @file + CPUID leaf definitions. + + Provides defines for CPUID leaf indexes. Data structures are provided for + registers returned by a CPUID leaf that contain one or more bit fields. + If a register returned is a single 32-bit value, then a data structure is + not provided for that register. + + Copyright (c) 2017, Advanced Micro Devices. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34 + +**/ + +#ifndef __AMD_CPUID_H__ +#define __AMD_CPUID_H__ + +/** +CPUID Signature Information + +@param EAX CPUID_SIGNATURE (0x00) + +@retval EAX Returns the highest value the CPUID instruction recognizes for + returning basic processor information. The value is returned is + processor specific. +@retval EBX First 4 characters of a vendor identification string. +@retval ECX Last 4 characters of a vendor identification string. +@retval EDX Middle 4 characters of a vendor identification string. + +**/ + +/// +/// @{ CPUID signature values returned by AMD processors +/// +#define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h') +#define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i') +#define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D') +/// +/// @} +/// + +/** + CPUID Extended Processor Signature and Features + + @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001) + + @retval EAX Extended Family, Model, Stepping Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX. + @retval EBX Brand Identifier + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX. + @retval ECX Extended Feature Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX. + @retval EDX Extended Feature Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX. +**/ + +/** + CPUID Extended Processor Signature and Features EAX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Stepping. + /// + UINT32 Stepping : 4; + /// + /// [Bits 7:4] Base Model. + /// + UINT32 BaseModel : 4; + /// + /// [Bits 11:8] Base Family. + /// + UINT32 BaseFamily : 4; + /// + /// [Bit 15:12] Reserved. + /// + UINT32 Reserved1 : 4; + /// + /// [Bits 19:16] Extended Model. + /// + UINT32 ExtModel : 4; + /// + /// [Bits 27:20] Extended Family. + /// + UINT32 ExtFamily : 8; + /// + /// [Bit 31:28] Reserved. + /// + UINT32 Reserved2 : 4; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EAX; + +/** + CPUID Extended Processor Signature and Features EBX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 27:0] Reserved. + /// + UINT32 Reserved : 28; + /// + /// [Bit 31:28] Package Type. + /// + UINT32 PkgType : 4; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EBX; + +/** + CPUID Extended Processor Signature and Features ECX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LAHF/SAHF available in 64-bit mode. + /// + UINT32 LAHF_SAHF : 1; + /// + /// [Bit 1] Core multi-processing legacy mode. + /// + UINT32 CmpLegacy : 1; + /// + /// [Bit 2] Secure Virtual Mode feature. + /// + UINT32 SVM : 1; + /// + /// [Bit 3] Extended APIC register space. + /// + UINT32 ExtApicSpace : 1; + /// + /// [Bit 4] LOCK MOV CR0 means MOV CR8. + /// + UINT32 AltMovCr8 : 1; + /// + /// [Bit 5] LZCNT instruction support. + /// + UINT32 LZCNT : 1; + /// + /// [Bit 6] SSE4A instruction support. + /// + UINT32 SSE4A : 1; + /// + /// [Bit 7] Misaligned SSE Mode. + /// + UINT32 MisAlignSse : 1; + /// + /// [Bit 8] ThreeDNow Prefetch instructions. + /// + UINT32 PREFETCHW : 1; + /// + /// [Bit 9] OS Visible Work-around support. + /// + UINT32 OSVW : 1; + /// + /// [Bit 10] Instruction Based Sampling. + /// + UINT32 IBS : 1; + /// + /// [Bit 11] Extended Operation Support. + /// + UINT32 XOP : 1; + /// + /// [Bit 12] SKINIT and STGI support. + /// + UINT32 SKINIT : 1; + /// + /// [Bit 13] Watchdog Timer support. + /// + UINT32 WDT : 1; + /// + /// [Bit 14] Reserved. + /// + UINT32 Reserved1 : 1; + /// + /// [Bit 15] Lightweight Profiling support. + /// + UINT32 LWP : 1; + /// + /// [Bit 16] 4-Operand FMA instruction support. + /// + UINT32 FMA4 : 1; + /// + /// [Bit 17] Translation Cache Extension. + /// + UINT32 TCE : 1; + /// + /// [Bit 21:18] Reserved. + /// + UINT32 Reserved2 : 4; + /// + /// [Bit 22] Topology Extensions support. + /// + UINT32 TopologyExtensions : 1; + /// + /// [Bit 23] Core Performance Counter Extensions. + /// + UINT32 PerfCtrExtCore : 1; + /// + /// [Bit 25:24] Reserved. + /// + UINT32 Reserved3 : 2; + /// + /// [Bit 26] Data Breakpoint Extension. + /// + UINT32 DataBreakpointExtension : 1; + /// + /// [Bit 27] Performance Time-Stamp Counter. + /// + UINT32 PerfTsc : 1; + /// + /// [Bit 28] L3 Performance Counter Extensions. + /// + UINT32 PerfCtrExtL3 : 1; + /// + /// [Bit 29] MWAITX and MONITORX capability. + /// + UINT32 MwaitExtended : 1; + /// + /// [Bit 31:30] Reserved. + /// + UINT32 Reserved4 : 2; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_ECX; + +/** + CPUID Extended Processor Signature and Features EDX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] x87 floating point unit on-chip. + /// + UINT32 FPU : 1; + /// + /// [Bit 1] Virtual-mode enhancements. + /// + UINT32 VME : 1; + /// + /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE. + /// + UINT32 DE : 1; + /// + /// [Bit 3] Page-size extensions (4 MB pages). + /// + UINT32 PSE : 1; + /// + /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD. + /// + UINT32 TSC : 1; + /// + /// [Bit 5] MSRs, with RDMSR and WRMSR instructions. + /// + UINT32 MSR : 1; + /// + /// [Bit 6] Physical-address extensions (PAE). + /// + UINT32 PAE : 1; + /// + /// [Bit 7] Machine check exception, CR4.MCE. + /// + UINT32 MCE : 1; + /// + /// [Bit 8] CMPXCHG8B instruction. + /// + UINT32 CMPXCHG8B : 1; + /// + /// [Bit 9] APIC exists and is enabled. + /// + UINT32 APIC : 1; + /// + /// [Bit 10] Reserved. + /// + UINT32 Reserved1 : 1; + /// + /// [Bit 11] SYSCALL and SYSRET instructions. + /// + UINT32 SYSCALL_SYSRET : 1; + /// + /// [Bit 12] Memory-type range registers. + /// + UINT32 MTRR : 1; + /// + /// [Bit 13] Page global extension, CR4.PGE. + /// + UINT32 PGE : 1; + /// + /// [Bit 14] Machine check architecture, MCG_CAP. + /// + UINT32 MCA : 1; + /// + /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV. + /// + UINT32 CMOV : 1; + /// + /// [Bit 16] Page attribute table. + /// + UINT32 PAT : 1; + /// + /// [Bit 17] Page-size extensions. + /// + UINT32 PSE36 : 1; + /// + /// [Bit 19:18] Reserved. + /// + UINT32 Reserved2 : 2; + /// + /// [Bit 20] No-execute page protection. + /// + UINT32 NX : 1; + /// + /// [Bit 21] Reserved. + /// + UINT32 Reserved3 : 1; + /// + /// [Bit 22] AMD Extensions to MMX instructions. + /// + UINT32 MmxExt : 1; + /// + /// [Bit 23] MMX instructions. + /// + UINT32 MMX : 1; + /// + /// [Bit 24] FXSAVE and FXRSTOR instructions. + /// + UINT32 FFSR : 1; + /// + /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations. + /// + UINT32 FFXSR : 1; + /// + /// [Bit 26] 1-GByte large page support. + /// + UINT32 Page1GB : 1; + /// + /// [Bit 27] RDTSCP instructions. + /// + UINT32 RDTSCP : 1; + /// + /// [Bit 28] Reserved. + /// + UINT32 Reserved4 : 1; + /// + /// [Bit 29] Long Mode. + /// + UINT32 LM : 1; + /// + /// [Bit 30] 3DNow! instructions. + /// + UINT32 ThreeDNow : 1; + /// + /// [Bit 31] AMD Extensions to 3DNow! instructions. + /// + UINT32 ThreeDNowExt : 1; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EDX; + +/** +CPUID Linear Physical Address Size + +@param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) + +@retval EAX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX. +@retval EBX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX. +@retval ECX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX. +@retval EDX Reserved. +**/ + +/** + CPUID Linear Physical Address Size EAX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Maximum physical byte address size in bits. + /// + UINT32 PhysicalAddressBits : 8; + /// + /// [Bits 15:8] Maximum linear byte address size in bits. + /// + UINT32 LinearAddressBits : 8; + /// + /// [Bits 23:16] Maximum guest physical byte address size in bits. + /// + UINT32 GuestPhysAddrSize : 8; + /// + /// [Bit 31:24] Reserved. + /// + UINT32 Reserved : 8; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX; + +/** + CPUID Linear Physical Address Size EBX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 0] Clear Zero Instruction. + /// + UINT32 CLZERO : 1; + /// + /// [Bits 1] Instructions retired count support. + /// + UINT32 IRPerf : 1; + /// + /// [Bits 2] Restore error pointers for XSave instructions. + /// + UINT32 XSaveErPtr : 1; + /// + /// [Bit 31:3] Reserved. + /// + UINT32 Reserved : 29; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX; + +/** + CPUID Linear Physical Address Size ECX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Number of threads - 1. + /// + UINT32 NC : 8; + /// + /// [Bit 11:8] Reserved. + /// + UINT32 Reserved1 : 4; + /// + /// [Bits 15:12] APIC ID size. + /// + UINT32 ApicIdCoreIdSize : 4; + /// + /// [Bits 17:16] Performance time-stamp counter size. + /// + UINT32 PerfTscSize : 2; + /// + /// [Bit 31:18] Reserved. + /// + UINT32 Reserved2 : 14; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX; + +/** + CPUID AMD Processor Topology + + @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E) + + @retval EAX Extended APIC ID described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_EAX. + @retval EBX Core Identifiers described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX. + @retval ECX Node Identifiers described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX. + @retval EDX Reserved. +**/ +#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E + +/** + CPUID AMD Processor Topology EAX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] Extended APIC Id. + /// + UINT32 ExtendedApicId; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX; + +/** + CPUID AMD Processor Topology EBX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Core Id. + /// + UINT32 CoreId : 8; + /// + /// [Bits 15:8] Threads per core. + /// + UINT32 ThreadsPerCore : 8; + /// + /// [Bit 31:16] Reserved. + /// + UINT32 Reserved : 16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX; + +/** + CPUID AMD Processor Topology ECX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Node Id. + /// + UINT32 NodeId : 8; + /// + /// [Bits 10:8] Nodes per processor. + /// + UINT32 NodesPerProcessor : 3; + /// + /// [Bit 31:11] Reserved. + /// + UINT32 Reserved : 21; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX; + +/** + CPUID Memory Encryption Information + + @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F) + + @retval EAX Returns the memory encryption feature support status. + @retval EBX If memory encryption feature is present then return + the page table bit number used to enable memory encryption support + and reducing of physical address space in bits. + @retval ECX Returns number of encrypted guest supported simultaneously. + @retval EDX Returns minimum SEV enabled and SEV disabled ASID. + + Example usage + @code + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + + AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx); + @endcode +**/ + +#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F + +/** + CPUID Memory Encryption support information EAX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Secure Memory Encryption (Sme) Support + /// + UINT32 SmeBit : 1; + + /// + /// [Bit 1] Secure Encrypted Virtualization (Sev) Support + /// + UINT32 SevBit : 1; + + /// + /// [Bit 2] Page flush MSR support + /// + UINT32 PageFlushMsrBit : 1; + + /// + /// [Bit 3] Encrypted state support + /// + UINT32 SevEsBit : 1; + + /// + /// [Bit 31:4] Reserved + /// + UINT32 ReservedBits : 28; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EAX; + +/** + CPUID Memory Encryption support information EBX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 5:0] Page table bit number used to enable memory encryption + /// + UINT32 PtePosBits : 6; + + /// + /// [Bit 11:6] Reduction of system physical address space bits when + /// memory encryption is enabled + /// + UINT32 ReducedPhysBits : 5; + + /// + /// [Bit 31:12] Reserved + /// + UINT32 ReservedBits : 21; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EBX; + +/** + CPUID Memory Encryption support information ECX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] Number of encrypted guest supported simultaneously + /// + UINT32 NumGuests; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_ECX; + +/** + CPUID Memory Encryption support information EDX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID + /// + UINT32 MinAsid; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EDX; + +#endif diff --git a/sdk/include/reactos/x86x64/Cpuid.h b/sdk/include/reactos/x86x64/Cpuid.h new file mode 100644 index 00000000000..0a27d581e17 --- /dev/null +++ b/sdk/include/reactos/x86x64/Cpuid.h @@ -0,0 +1,205 @@ + +#define CHAR8 char + +#include "Intel/Cpuid.h" +#include "Amd/Cpuid.h" + +// CPUID_SIGNATURE (0) +typedef union +{ + INT32 AsInt32[4]; + struct + { + UINT32 MaxLeaf; + CHAR SignatureScrambled[12]; + }; +} CPUID_SIGNATURE_REGS; + +// CPUID_VERSION_INFO (1) +typedef union +{ + INT32 AsInt32[4]; + struct + { + CPUID_VERSION_INFO_EAX Eax; + CPUID_VERSION_INFO_EBX Ebx; + CPUID_VERSION_INFO_ECX Ecx; + CPUID_VERSION_INFO_EDX Edx; + }; +} CPUID_VERSION_INFO_REGS; + +// CPUID_EXTENDED_FUNCTION (0x80000000) +typedef union +{ + INT32 AsInt32[4]; + struct + { + UINT32 MaxLeaf; + UINT32 ReservedEbx; + UINT32 ReservedEcx; + UINT32 ReservedEdx; + }; +} CPUID_EXTENDED_FUNCTION_REGS; + +// CPUID_THERMAL_POWER_MANAGEMENT (6) +typedef union +{ + INT32 AsInt32[4]; + struct + { + CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax; + CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx; + CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx; + UINT32 ReservedEdx; + }; + struct + { + UINT32 Eax; + UINT32 Ebx; + struct + { + UINT32 HardwareCoordinationFeedback : 1; + UINT32 ACNT2 : 1; // See https://en.wikipedia.org/wiki/CPUID + } Ecx; + } Undoc; +} CPUID_THERMAL_POWER_MANAGEMENT_REGS; + +// CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07) +typedef union +{ + INT32 AsInt32[4]; + struct + { + UINT32 Eax; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx; + }; +} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_REGS; + +// CPUID_EXTENDED_STATE (0x0D) +// CPUID_EXTENDED_STATE_MAIN_LEAF (0x00) +typedef union +{ + INT32 AsInt32[4]; + struct + { + CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + }; +} CPUID_EXTENDED_STATE_MAIN_LEAF_REGS; + +// CPUID_EXTENDED_STATE (0x0D) +// CPUID_EXTENDED_STATE_SUB_LEAF (0x01) +typedef union +{ + INT32 AsInt32[4]; + struct + { + CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax; + struct + { + UINT32 XSaveAreaSize; // The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS. + } Ebx; + CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx; + struct + { + UINT32 Edx; // Reports the supported bits of the upper 32 bits of the IA32_XSS MSR.IA32_XSS[n + 32] can be set to 1 only if EDX[n] is 1. + } Edx; + }; +} CPUID_EXTENDED_STATE_SUB_LEAF_EAX_REGS; + +// CPUID_EXTENDED_CPU_SIG (0x80000001) +typedef union +{ + INT32 AsInt32[4]; + struct + { + UINT32 Signature; + UINT32 ReservedEbx; + CPUID_EXTENDED_CPU_SIG_ECX Ecx; + CPUID_EXTENDED_CPU_SIG_EDX Edx; + } Intel; + struct + { + CPUID_AMD_EXTENDED_CPU_SIG_EAX Eax; + CPUID_AMD_EXTENDED_CPU_SIG_EBX Ebx; + CPUID_AMD_EXTENDED_CPU_SIG_ECX Ecx; + CPUID_AMD_EXTENDED_CPU_SIG_EDX Edx; + } Amd; +} CPUID_EXTENDED_CPU_SIG_REGS; + + +// Additional AMD specific CPUID: +// See +// - AMD64 Architecture Programmer’s Manual Volume 2: System Programming (https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/progra…) +// - http://www.flounder.com/cpuid_explorer2.htm#CPUID(0x8000000A) +// - https://www.spinics.net/lists/kvm/msg279165.html +// - https://qemu-devel.nongnu.narkive.com/zgmvxGLq/patch-0-3-svm-feature-suppor… +// - https://github.com/torvalds/linux/blob/28f20a19294da7df158dfca259d0e2b5866b… + +#define CPUID_AMD_SVM_FEATURES 0x8000000A + +typedef union +{ + struct + { + UINT SVMRev : 8; // EAX[7..0] + UINT Reserved : 24; // EAX[31..8] + } Bits; + + UINT32 Uint32; +} CPUID_AMD_SVM_FEATURES_EAX; + +typedef union +{ + struct + { + UINT32 NP : 1; // EDX[0] Nested paging support + UINT32 LbrVirt : 1; // EDX[1] LBR virtualization + UINT32 SVML : 1; // EDX[2] SVM Lock + UINT32 NRIPS : 1; // EDX[3] Next RIP save on VMEXIT + UINT32 TscRateMsr : 1; // EDX[4] MSR based TSC ratio control + UINT32 VmcbClean : 1; // EDX[5] VMCB Clean bits support + UINT32 FlushByAsid : 1; // EDX[6] Flush by ASID support + UINT32 DecodeAssists : 1; // EDX[7] Decode assists support + UINT32 Reserved1 : 2; // EDX[9:8] Reserved + UINT32 PauseFilter : 1; // EDX[10] Pause filter support + UINT32 Reserved2 : 1; // EDX[11] Reserved + UINT32 PauseFilterThreshold : 1; // EDX[12] Pause filter threshold support + UINT32 AVIC : 1; // EDX[13:13] Advanced Virtual Interrupt Controller + UINT32 Unknown14 : 1; // EDX[14] Unknown. Described in AMD doc as X2AVIC, but that was probably a typo, since x2AVIC is bit 18. + UINT32 VMSAVEVirt : 1; // EDX[15] MSAVE and VMLOAD Virtualization + UINT32 VGIF : 1; // EDX[16] Virtual Global-Interrupt Flag + UINT32 GMET : 1; // EDX[17] Guest Mode Execute Trap Extension + UINT32 x2AVIC : 1; // EDX[18] Virtual x2APIC + UINT32 SSSCheck : 1; // EDX[19] AKA SupervisorShadowStack + UINT32 V_SPEC_CTRL : 1; // EDX[20] Virtual SPEC_CTRL + UINT32 ROGPT : 1; // EDX[21] + UINT32 Unknown22 : 1; // EDX[22] + UINT32 HOST_MCE_OVERRIDE : 1; // EDX[23] + UINT32 TLBSYNC : 1; // EDX[24] TLBSYNC instruction can be intercepted + UINT32 VNMI : 1; // EDX[25] NMI Virtualization support + UINT32 IbsVirt : 1; // EDX[26] Instruction Based Sampling Virtualization + UINT32 LVTReadAllowed : 1; // EDX[27] + UINT32 Unknown28 : 1; // EDX[28] + UINT32 BusLockThreshold : 1; // EDX[29] + } Bits; + + UINT32 Uint32; +} CPUID_AMD_SVM_FEATURES_EDX; + +// CPUID_AMD_SVM_FEATURES (0x8000000A) +typedef union +{ + INT32 AsInt32[4]; + struct + { + CPUID_AMD_SVM_FEATURES_EAX Eax; + UINT32 NumberOfSupportedASIDs; + UINT32 Ecx; + CPUID_AMD_SVM_FEATURES_EDX Edx; + }; +} CPUID_AMD_SVM_FEATURES_REGS; diff --git a/sdk/include/reactos/x86x64/Intel/ArchitecturalMsr.h b/sdk/include/reactos/x86x64/Intel/ArchitecturalMsr.h new file mode 100644 index 00000000000..26bc6ba3138 --- /dev/null +++ b/sdk/include/reactos/x86x64/Intel/ArchitecturalMsr.h @@ -0,0 +1,6532 @@ +/** @file + Intel Architectural MSR Definitions. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __INTEL_ARCHITECTURAL_MSR_H__ +#define __INTEL_ARCHITECTURAL_MSR_H__ + +/** + See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H). + + @param ECX MSR_IA32_P5_MC_ADDR (0x00000000) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR); + AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr); + @endcode + @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM. +**/ +#define MSR_IA32_P5_MC_ADDR 0x00000000 + +/** + See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H. + + @param ECX MSR_IA32_P5_MC_TYPE (0x00000001) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE); + AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr); + @endcode + @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM. +**/ +#define MSR_IA32_P5_MC_TYPE 0x00000001 + +/** + See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced + at Display Family / Display Model 0F_03H. + + @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE); + AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr); + @endcode + @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM. +**/ +#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006 + +/** + See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family / + Display Model 05_01H. + + @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER); + AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr); + @endcode + @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM. +**/ +#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010 + +/** + Platform ID (RO) The operating system can use this MSR to determine "slot" + information for the processor and the proper microcode update to load. + Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_PLATFORM_ID (0x00000017) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PLATFORM_ID_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PLATFORM_ID_REGISTER. + + Example usage + @code + MSR_IA32_PLATFORM_ID_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID); + @endcode + @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM. +**/ +#define MSR_IA32_PLATFORM_ID 0x00000017 + +/** + MSR information returned for MSR index #MSR_IA32_PLATFORM_ID +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1 : 32; + UINT32 Reserved2 : 18; + /// + /// [Bits 52:50] Platform Id (RO) Contains information concerning the + /// intended platform for the processor. + /// 52 51 50 + /// -- -- -- + /// 0 0 0 Processor Flag 0. + /// 0 0 1 Processor Flag 1 + /// 0 1 0 Processor Flag 2 + /// 0 1 1 Processor Flag 3 + /// 1 0 0 Processor Flag 4 + /// 1 0 1 Processor Flag 5 + /// 1 1 0 Processor Flag 6 + /// 1 1 1 Processor Flag 7 + /// + UINT32 PlatformId : 3; + UINT32 Reserved3 : 11; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PLATFORM_ID_REGISTER; + +/** + 06_01H. + + @param ECX MSR_IA32_APIC_BASE (0x0000001B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_APIC_BASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_APIC_BASE_REGISTER. + + Example usage + @code + MSR_IA32_APIC_BASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); + AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64); + @endcode + @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM. +**/ +#define MSR_IA32_APIC_BASE 0x0000001B + +/** + MSR information returned for MSR index #MSR_IA32_APIC_BASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1 : 8; + /// + /// [Bit 8] BSP flag (R/W). + /// + UINT32 BSP : 1; + UINT32 Reserved2 : 1; + /// + /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display + /// Model 06_1AH. + /// + UINT32 EXTD : 1; + /// + /// [Bit 11] APIC Global Enable (R/W). + /// + UINT32 EN : 1; + /// + /// [Bits 31:12] APIC Base (R/W). + /// + UINT32 ApicBase : 20; + /// + /// [Bits 63:32] APIC Base (R/W). + /// + UINT32 ApicBaseHi : 32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_APIC_BASE_REGISTER; + +/** + Control Features in Intel 64 Processor (R/W). If any one enumeration + condition for defined bit field holds. + + @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. + + Example usage + @code + MSR_IA32_FEATURE_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL); + AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64); + @endcode + @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM. +**/ +#define MSR_IA32_FEATURE_CONTROL 0x0000003A + +/** + MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from + /// being written, writes to this bit will result in GP(0). Note: Once the + /// Lock bit is set, the contents of this register cannot be modified. + /// Therefore the lock bit must be set after configuring support for Intel + /// Virtualization Technology and prior to transferring control to an + /// option ROM or the OS. Hence, once the Lock bit is set, the entire + /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD + /// is not deasserted. If any one enumeration condition for defined bit + /// field position greater than bit 0 holds. + /// + UINT32 Lock : 1; + /// + /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a + /// system executive to use VMX in conjunction with SMX to support + /// Intel(R) Trusted Execution Technology. BIOS must set this bit only + /// when the CPUID function 1 returns VMX feature flag and SMX feature + /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 && + /// CPUID.01H:ECX[6] = 1. + /// + UINT32 EnableVmxInsideSmx : 1; + /// + /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX + /// for system executive that do not require SMX. BIOS must set this bit + /// only when the CPUID function 1 returns VMX feature flag set (ECX bit + /// 5). If CPUID.01H:ECX[5] = 1. + /// + UINT32 EnableVmxOutsideSmx : 1; + UINT32 Reserved1 : 5; + /// + /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit + /// in the field represents an enable control for a corresponding SENTER + /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If + /// CPUID.01H:ECX[6] = 1. + /// + UINT32 SenterLocalFunctionEnables : 7; + /// + /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable + /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit + /// 6] is set. If CPUID.01H:ECX[6] = 1. + /// + UINT32 SenterGlobalEnable : 1; + UINT32 Reserved2 : 1; + /// + /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to + /// enable runtime reconfiguration of SGX Launch Control via + /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1. + /// + UINT32 SgxLaunchControlEnable : 1; + /// + /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX + /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1. + /// + UINT32 SgxEnable : 1; + UINT32 Reserved3 : 1; + /// + /// [Bit 20] LMCE On (R/WL): When set, system software can program the + /// MSRs associated with LMCE to configure delivery of some machine check + /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1. + /// + UINT32 LmceOn : 1; + UINT32 Reserved4 : 11; + UINT32 Reserved5 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_FEATURE_CONTROL_REGISTER; + +/** + Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H, + ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for + a logical processor. Reset value is Zero. A write to IA32_TSC will modify + the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does + not affect the internal invariant TSC hardware. + + @param ECX MSR_IA32_TSC_ADJUST (0x0000003B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST); + AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr); + @endcode + @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM. +**/ +#define MSR_IA32_TSC_ADJUST 0x0000003B + +/** + BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a + microcode update to be loaded into the processor. See Section 9.11.6, + "Microcode Update Loader." A processor may prevent writing to this MSR when + loading guest states on VM entries or saving guest states on VM exits. + Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = 0; + AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr); + @endcode + @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM. +**/ +#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 + +/** + BIOS Update Signature (RO) Returns the microcode update signature following + the execution of CPUID.01H. A processor may prevent writing to this MSR when + loading guest states on VM entries or saving guest states on VM exits. + Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. + + Example usage + @code + MSR_IA32_BIOS_SIGN_ID_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID); + @endcode + @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM. +**/ +#define MSR_IA32_BIOS_SIGN_ID 0x0000008B + +/** + MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved : 32; + /// + /// [Bits 63:32] Microcode update signature. This field contains the + /// signature of the currently loaded microcode update when read following + /// the execution of the CPUID instruction, function 1. It is required + /// that this register field be pre-loaded with zero prior to executing + /// the CPUID, function 1. If the field remains equal to zero, then there + /// is no microcode update loaded. Another nonzero value will be the + /// signature. + /// + UINT32 MicrocodeUpdateSignature : 32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_BIOS_SIGN_ID_REGISTER; + +/** + IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the + SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the + default value is the digest of Intel's signing key. Read permitted If + CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H): + EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1. + + @param ECX MSR_IA32_SGXLEPUBKEYHASHn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn); + AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr); + @endcode + @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM. + MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM. + MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM. + MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM. + @{ +**/ +#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C +#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D +#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E +#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F +/// @} + +/** + SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] = + 1. + + @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. + + Example usage + @code + MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL); + AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64); + @endcode + @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM. +**/ +#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B + +/** + MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this + /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment + /// (see Section 34.15.6), the dual-monitor treatment cannot be activated + /// if the bit is 0. This bit is cleared when the logical processor is + /// reset. + /// + UINT32 Valid : 1; + UINT32 Reserved1 : 1; + /// + /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If + /// IA32_VMX_MISC[28]. + /// + UINT32 BlockSmi : 1; + UINT32 Reserved2 : 9; + /// + /// [Bits 31:12] MSEG Base (R/W). + /// + UINT32 MsegBase : 20; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_SMM_MONITOR_CTL_REGISTER; + +/** + MSEG header that is located at the physical address specified by the MsegBase + field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER. +**/ +typedef struct { + /// + /// Different processors may use different MSEG revision identifiers. These + /// identifiers enable software to avoid using an MSEG header formatted for + /// one processor on a processor that uses a different format. Software can + /// discover the MSEG revision identifier that a processor uses by reading + /// the VMX capability MSR IA32_VMX_MISC. + // + UINT32 MsegHeaderRevision; + /// + /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field + /// is the IA-32e mode SMM feature bit. It indicates whether the logical + /// processor will be in IA-32e mode after the STM is activated. + /// + UINT32 MonitorFeatures; + UINT32 GdtrLimit; + UINT32 GdtrBaseOffset; + UINT32 CsSelector; + UINT32 EipOffset; + UINT32 EspOffset; + UINT32 Cr3Offset; + /// + /// Pad header so total size is 2KB + /// + UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)]; +} MSEG_HEADER; + +/// +/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER +/// +#define STM_FEATURES_IA32E 0x1 +/// +/// @} +/// + +/** + Base address of the logical processor's SMRAM image (RO, SMM only). If + IA32_VMX_MISC[15]. + + @param ECX MSR_IA32_SMBASE (0x0000009E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_SMBASE); + @endcode + @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM. +**/ +#define MSR_IA32_SMBASE 0x0000009E + +/** + General Performance Counters (R/W). + MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n. + + @param ECX MSR_IA32_PMCn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_PMC0); + AsmWriteMsr64 (MSR_IA32_PMC0, Msr); + @endcode + @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM. + MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM. + MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM. + MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM. + MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM. + MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM. + MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM. + MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM. + @{ +**/ +#define MSR_IA32_PMC0 0x000000C1 +#define MSR_IA32_PMC1 0x000000C2 +#define MSR_IA32_PMC2 0x000000C3 +#define MSR_IA32_PMC3 0x000000C4 +#define MSR_IA32_PMC4 0x000000C5 +#define MSR_IA32_PMC5 0x000000C6 +#define MSR_IA32_PMC6 0x000000C7 +#define MSR_IA32_PMC7 0x000000C8 +/// @} + +/** + TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1. + C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative + to TSC freq.) when the logical processor is in C0. Cleared upon overflow / + wrap-around of IA32_APERF. + + @param ECX MSR_IA32_MPERF (0x000000E7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MPERF); + AsmWriteMsr64 (MSR_IA32_MPERF, Msr); + @endcode + @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM. +**/ +#define MSR_IA32_MPERF 0x000000E7 + +/** + Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = + 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at + the coordinated clock frequency, when the logical processor is in C0. + Cleared upon overflow / wrap-around of IA32_MPERF. + + @param ECX MSR_IA32_APERF (0x000000E8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_APERF); + AsmWriteMsr64 (MSR_IA32_APERF, Msr); + @endcode + @note MSR_IA32_APERF is defined as IA32_APERF in SDM. +**/ +#define MSR_IA32_APERF 0x000000E8 + +/** + MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.". + Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_MTRRCAP (0x000000FE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MTRRCAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MTRRCAP_REGISTER. + + Example usage + @code + MSR_IA32_MTRRCAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP); + @endcode + @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM. +**/ +#define MSR_IA32_MTRRCAP 0x000000FE + +/** + MSR information returned for MSR index #MSR_IA32_MTRRCAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] VCNT: The number of variable memory type ranges in the + /// processor. + /// + UINT32 VCNT : 8; + /// + /// [Bit 8] Fixed range MTRRs are supported when set. + /// + UINT32 FIX : 1; + UINT32 Reserved1 : 1; + /// + /// [Bit 10] WC Supported when set. + /// + UINT32 WC : 1; + /// + /// [Bit 11] SMRR Supported when set. + /// + UINT32 SMRR : 1; + UINT32 Reserved2 : 20; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MTRRCAP_REGISTER; + +/** + SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_SYSENTER_CS (0x00000174) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_SYSENTER_CS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_SYSENTER_CS_REGISTER. + + Example usage + @code + MSR_IA32_SYSENTER_CS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS); + AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64); + @endcode + @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM. +**/ +#define MSR_IA32_SYSENTER_CS 0x00000174 + +/** + MSR information returned for MSR index #MSR_IA32_SYSENTER_CS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] CS Selector. + /// + UINT32 CS : 16; + UINT32 Reserved1 : 16; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_SYSENTER_CS_REGISTER; + +/** + SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_SYSENTER_ESP (0x00000175) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP); + AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr); + @endcode + @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM. +**/ +#define MSR_IA32_SYSENTER_ESP 0x00000175 + +/** + SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_SYSENTER_EIP (0x00000176) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP); + AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr); + @endcode + @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM. +**/ +#define MSR_IA32_SYSENTER_EIP 0x00000176 + +/** + Global Machine Check Capability (RO). Introduced at Display Family / Display + Model 06_01H. + + @param ECX MSR_IA32_MCG_CAP (0x00000179) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MCG_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MCG_CAP_REGISTER. + + Example usage + @code + MSR_IA32_MCG_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); + @endcode + @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM. +**/ +#define MSR_IA32_MCG_CAP 0x00000179 + +/** + MSR information returned for MSR index #MSR_IA32_MCG_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Count: Number of reporting banks. + /// + UINT32 Count : 8; + /// + /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set. + /// + UINT32 MCG_CTL_P : 1; + /// + /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present + /// if this bit is set. + /// + UINT32 MCG_EXT_P : 1; + /// + /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present. + /// Introduced at Display Family / Display Model 06_01H. + /// + UINT32 MCP_CMCI_P : 1; + /// + /// [Bit 11] MCG_TES_P: Threshold-based error status register are present + /// if this bit is set. + /// + UINT32 MCG_TES_P : 1; + UINT32 Reserved1 : 4; + /// + /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state + /// registers present. + /// + UINT32 MCG_EXT_CNT : 8; + /// + /// [Bit 24] MCG_SER_P: The processor supports software error recovery if + /// this bit is set. + /// + UINT32 MCG_SER_P : 1; + UINT32 Reserved2 : 1; + /// + /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform + /// firmware to be invoked when an error is detected so that it may + /// provide additional platform specific information in an ACPI format + /// "Generic Error Data Entry" that augments the data included in machine + /// check bank registers. Introduced at Display Family / Display Model + /// 06_3EH. + /// + UINT32 MCG_ELOG_P : 1; + /// + /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended + /// state in IA32_MCG_STATUS and associated MSR necessary to configure + /// Local Machine Check Exception (LMCE). Introduced at Display Family / + /// Display Model 06_3EH. + /// + UINT32 MCG_LMCE_P : 1; + UINT32 Reserved3 : 4; + UINT32 Reserved4 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MCG_CAP_REGISTER; + +/** + Global Machine Check Status (R/W0). Introduced at Display Family / Display + Model 06_01H. + + @param ECX MSR_IA32_MCG_STATUS (0x0000017A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MCG_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MCG_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_MCG_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS); + AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64); + @endcode + @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM. +**/ +#define MSR_IA32_MCG_STATUS 0x0000017A + +/** + MSR information returned for MSR index #MSR_IA32_MCG_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display + /// Model 06_01H. + /// + UINT32 RIPV : 1; + /// + /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display + /// Model 06_01H. + /// + UINT32 EIPV : 1; + /// + /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family + /// / Display Model 06_01H. + /// + UINT32 MCIP : 1; + /// + /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1. + /// + UINT32 LMCE_S : 1; + UINT32 Reserved1 : 28; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MCG_STATUS_REGISTER; + +/** + Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1. + + @param ECX MSR_IA32_MCG_CTL (0x0000017B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL); + AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr); + @endcode + @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM. +**/ +#define MSR_IA32_MCG_CTL 0x0000017B + +/** + Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n. + + @param ECX MSR_IA32_PERFEVTSELn + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERFEVTSEL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERFEVTSEL_REGISTER. + + Example usage + @code + MSR_IA32_PERFEVTSEL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0); + AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64); + @endcode + @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. + MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. + MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM. + MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM. + @{ +**/ +#define MSR_IA32_PERFEVTSEL0 0x00000186 +#define MSR_IA32_PERFEVTSEL1 0x00000187 +#define MSR_IA32_PERFEVTSEL2 0x00000188 +#define MSR_IA32_PERFEVTSEL3 0x00000189 +/// @} + +/** + MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to + #MSR_IA32_PERFEVTSEL3 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Event Select: Selects a performance event logic unit. + /// + UINT32 EventSelect : 8; + /// + /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to + /// detect on the selected event logic. + /// + UINT32 UMASK : 8; + /// + /// [Bit 16] USR: Counts while in privilege level is not ring 0. + /// + UINT32 USR : 1; + /// + /// [Bit 17] OS: Counts while in privilege level is ring 0. + /// + UINT32 OS : 1; + /// + /// [Bit 18] Edge: Enables edge detection if set. + /// + UINT32 E : 1; + /// + /// [Bit 19] PC: enables pin control. + /// + UINT32 PC : 1; + /// + /// [Bit 20] INT: enables interrupt on counter overflow. + /// + UINT32 INT : 1; + /// + /// [Bit 21] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. + /// + UINT32 ANY : 1; + /// + /// [Bit 22] EN: enables the corresponding performance counter to commence + /// counting when this bit is set. + /// + UINT32 EN : 1; + /// + /// [Bit 23] INV: invert the CMASK. + /// + UINT32 INV : 1; + /// + /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding + /// performance counter increments each cycle if the event count is + /// greater than or equal to the CMASK. + /// + UINT32 CMASK : 8; + UINT32 Reserved : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERFEVTSEL_REGISTER; + +/** + Current performance state(P-State) operating point (RO). Introduced at + Display Family / Display Model 0F_03H. + + @param ECX MSR_IA32_PERF_STATUS (0x00000198) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_PERF_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS); + @endcode + @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM. +**/ +#define MSR_IA32_PERF_STATUS 0x00000198 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Current performance State Value. + /// + UINT32 State : 16; + UINT32 Reserved1 : 16; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_STATUS_REGISTER; + +/** + (R/W). Introduced at Display Family / Display Model 0F_03H. + + @param ECX MSR_IA32_PERF_CTL (0x00000199) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_CTL_REGISTER. + + Example usage + @code + MSR_IA32_PERF_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL); + AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM. +**/ +#define MSR_IA32_PERF_CTL 0x00000199 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Target performance State Value. + /// + UINT32 TargetState : 16; + UINT32 Reserved1 : 16; + /// + /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH + /// (Mobile only). + /// + UINT32 IDA : 1; + UINT32 Reserved2 : 31; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_CTL_REGISTER; + +/** + Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled + Clock Modulation.". If CPUID.01H:EDX[22] = 1. + + @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER. + + Example usage + @code + MSR_IA32_CLOCK_MODULATION_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION); + AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64); + @endcode + @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM. +**/ +#define MSR_IA32_CLOCK_MODULATION 0x0000019A + +/** + MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If + /// CPUID.06H:EAX[5] = 1. + /// + UINT32 ExtendedOnDemandClockModulationDutyCycle : 1; + /// + /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded + /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1. + /// + UINT32 OnDemandClockModulationDutyCycle : 3; + /// + /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation. + /// If CPUID.01H:EDX[22] = 1. + /// + UINT32 OnDemandClockModulationEnable : 1; + UINT32 Reserved1 : 27; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_CLOCK_MODULATION_REGISTER; + +/** + Thermal Interrupt Control (R/W) Enables and disables the generation of an + interrupt on temperature transitions detected with the processor's thermal + sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.". + If CPUID.01H:EDX[22] = 1 + + @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER. + + Example usage + @code + MSR_IA32_THERM_INTERRUPT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT); + AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64); + @endcode + @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM. +**/ +#define MSR_IA32_THERM_INTERRUPT 0x0000019B + +/** + MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 HighTempEnable : 1; + /// + /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 LowTempEnable : 1; + /// + /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 PROCHOT_Enable : 1; + /// + /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 FORCEPR_Enable : 1; + /// + /// [Bit 4] Critical Temperature Interrupt Enable. + /// If CPUID.01H:EDX[22] = 1. + /// + UINT32 CriticalTempEnable : 1; + UINT32 Reserved1 : 3; + /// + /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1. + /// + UINT32 Threshold1 : 7; + /// + /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 Threshold1Enable : 1; + /// + /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1. + /// + UINT32 Threshold2 : 7; + /// + /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 Threshold2Enable : 1; + /// + /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1. + /// + UINT32 PowerLimitNotificationEnable : 1; + UINT32 Reserved2 : 7; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_THERM_INTERRUPT_REGISTER; + +/** + Thermal Status Information (RO) Contains status information about the + processor's thermal sensor and automatic thermal monitoring facilities. See + Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1. + + @param ECX MSR_IA32_THERM_STATUS (0x0000019C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_THERM_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_THERM_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_THERM_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS); + @endcode + @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM. +**/ +#define MSR_IA32_THERM_STATUS 0x0000019C + +/** + MSR information returned for MSR index #MSR_IA32_THERM_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1. + /// + UINT32 ThermalStatus : 1; + /// + /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1. + /// + UINT32 ThermalStatusLog : 1; + /// + /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1. + /// + UINT32 PROCHOT_FORCEPR_Event : 1; + /// + /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1. + /// + UINT32 PROCHOT_FORCEPR_Log : 1; + /// + /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1. + /// + UINT32 CriticalTempStatus : 1; + /// + /// [Bit 5] Critical Temperature Status log (R/WC0). + /// If CPUID.01H:EDX[22] = 1. + /// + UINT32 CriticalTempStatusLog : 1; + /// + /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1. + /// + UINT32 ThermalThreshold1Status : 1; + /// + /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1. + /// + UINT32 ThermalThreshold1Log : 1; + /// + /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1. + /// + UINT32 ThermalThreshold2Status : 1; + /// + /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1. + /// + UINT32 ThermalThreshold2Log : 1; + /// + /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1. + /// + UINT32 PowerLimitStatus : 1; + /// + /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1. + /// + UINT32 PowerLimitLog : 1; + /// + /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1. + /// + UINT32 CurrentLimitStatus : 1; + /// + /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1. + /// + UINT32 CurrentLimitLog : 1; + /// + /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1. + /// + UINT32 CrossDomainLimitStatus : 1; + /// + /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1. + /// + UINT32 CrossDomainLimitLog : 1; + /// + /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1. + /// + UINT32 DigitalReadout : 7; + UINT32 Reserved1 : 4; + /// + /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] = + /// 1. + /// + UINT32 ResolutionInDegreesCelsius : 4; + /// + /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1. + /// + UINT32 ReadingValid : 1; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_THERM_STATUS_REGISTER; + +/** + Enable Misc. Processor Features (R/W) Allows a variety of processor + functions to be enabled and disabled. + + @param ECX MSR_IA32_MISC_ENABLE (0x000001A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MISC_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MISC_ENABLE_REGISTER. + + Example usage + @code + MSR_IA32_MISC_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE); + AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64); + @endcode + @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. +**/ +#define MSR_IA32_MISC_ENABLE 0x000001A0 + +/** + MSR information returned for MSR index #MSR_IA32_MISC_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for + /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings + /// are disabled. Introduced at Display Family / Display Model 0F_0H. + /// + UINT32 FastStrings : 1; + UINT32 Reserved1 : 2; + /// + /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting + /// this bit enables the thermal control circuit (TCC) portion of the + /// Intel Thermal Monitor feature. This allows the processor to + /// automatically reduce power consumption in response to TCC activation. + /// 0 = Disabled. Note: In some products clearing this bit might be + /// ignored in critical thermal conditions, and TM1, TM2 and adaptive + /// thermal throttling will still be activated. The default value of this + /// field varies with product. See respective tables where default value is + /// listed. Introduced at Display Family / Display Model 0F_0H. + /// + UINT32 AutomaticThermalControlCircuit : 1; + UINT32 Reserved2 : 3; + /// + /// [Bit 7] Performance Monitoring Available (R) 1 = Performance + /// monitoring enabled 0 = Performance monitoring disabled. Introduced at + /// Display Family / Display Model 0F_0H. + /// + UINT32 PerformanceMonitoring : 1; + UINT32 Reserved3 : 3; + /// + /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't + /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at + /// Display Family / Display Model 0F_0H. + /// + UINT32 BTS : 1; + /// + /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 = + /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display + /// Family / Display Model 06_0FH. + /// + UINT32 PEBS : 1; + UINT32 Reserved4 : 3; + /// + /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced + /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep + /// Technology enabled. If CPUID.01H: ECX[7] =1. + /// + UINT32 EIST : 1; + UINT32 Reserved5 : 1; + /// + /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the + /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This + /// indicates that MONITOR/MWAIT are not supported. Software attempts to + /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit + /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit + /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit + /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it + /// in the default state. Writing this bit when the SSE3 feature flag is + /// set to 0 may generate a #GP exception. Introduced at Display Family / + /// Display Model 0F_03H. + /// + UINT32 MONITOR : 1; + UINT32 Reserved6 : 3; + /// + /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H + /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup + /// question that allows users to specify when the installed OS does not + /// support CPUID functions greater than 2. Before setting this bit, BIOS + /// must execute the CPUID.0H and examine the maximum value returned in + /// EAX[7:0]. If the maximum value is greater than 2, this bit is + /// supported. Otherwise, this bit is not supported. Setting this bit when + /// the maximum value is not greater than 2 may generate a #GP exception. + /// Setting this bit may cause unexpected behavior in software that + /// depends on the availability of CPUID leaves greater than 2. Introduced + /// at Display Family / Display Model 0F_03H. + /// + UINT32 LimitCpuidMaxval : 1; + /// + /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are + /// disabled. xTPR messages are optional messages that allow the processor + /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1. + /// + UINT32 xTPR_Message_Disable : 1; + UINT32 Reserved7 : 8; + UINT32 Reserved8 : 2; + /// + /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit + /// feature (XD Bit) is disabled and the XD Bit extended feature flag will + /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the + /// Execute Disable Bit feature (if available) allows the OS to enable PAE + /// paging and take advantage of data only pages. BIOS must not alter the + /// contents of this bit location, if XD bit is not supported. Writing + /// this bit to 1 when the XD Bit extended feature flag is set to 0 may + /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1. + /// + UINT32 XD : 1; + UINT32 Reserved9 : 29; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MISC_ENABLE_REGISTER; + +/** + Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1. + + @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER. + + Example usage + @code + MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS); + AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64); + @endcode + @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM. +**/ +#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0 + +/** + MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest + /// performance. 15 indicates preference to maximize energy saving. + /// + UINT32 PowerPolicyPreference : 4; + UINT32 Reserved1 : 28; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_ENERGY_PERF_BIAS_REGISTER; + +/** + Package Thermal Status Information (RO) Contains status information about + the package's thermal sensor. See Section 14.8, "Package Level Thermal + Management.". If CPUID.06H: EAX[6] = 1. + + @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS); + @endcode + @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM. +**/ +#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1 + +/** + MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Pkg Thermal Status (RO):. + /// + UINT32 ThermalStatus : 1; + /// + /// [Bit 1] Pkg Thermal Status Log (R/W):. + /// + UINT32 ThermalStatusLog : 1; + /// + /// [Bit 2] Pkg PROCHOT # event (RO). + /// + UINT32 PROCHOT_Event : 1; + /// + /// [Bit 3] Pkg PROCHOT # log (R/WC0). + /// + UINT32 PROCHOT_Log : 1; + /// + /// [Bit 4] Pkg Critical Temperature Status (RO). + /// + UINT32 CriticalTempStatus : 1; + /// + /// [Bit 5] Pkg Critical Temperature Status log (R/WC0). + /// + UINT32 CriticalTempStatusLog : 1; + /// + /// [Bit 6] Pkg Thermal Threshold #1 Status (RO). + /// + UINT32 ThermalThreshold1Status : 1; + /// + /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0). + /// + UINT32 ThermalThreshold1Log : 1; + /// + /// [Bit 8] Pkg Thermal Threshold #2 Status (RO). + /// + UINT32 ThermalThreshold2Status : 1; + /// + /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0). + /// + UINT32 ThermalThreshold2Log : 1; + /// + /// [Bit 10] Pkg Power Limitation Status (RO). + /// + UINT32 PowerLimitStatus : 1; + /// + /// [Bit 11] Pkg Power Limitation log (R/WC0). + /// + UINT32 PowerLimitLog : 1; + UINT32 Reserved1 : 4; + /// + /// [Bits 22:16] Pkg Digital Readout (RO). + /// + UINT32 DigitalReadout : 7; + UINT32 Reserved2 : 9; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER; + +/** + Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of + an interrupt on temperature transitions detected with the package's thermal + sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H: + EAX[6] = 1. + + @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER. + + Example usage + @code + MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT); + AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64); + @endcode + @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM. +**/ +#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2 + +/** + MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Pkg High-Temperature Interrupt Enable. + /// + UINT32 HighTempEnable : 1; + /// + /// [Bit 1] Pkg Low-Temperature Interrupt Enable. + /// + UINT32 LowTempEnable : 1; + /// + /// [Bit 2] Pkg PROCHOT# Interrupt Enable. + /// + UINT32 PROCHOT_Enable : 1; + UINT32 Reserved1 : 1; + /// + /// [Bit 4] Pkg Overheat Interrupt Enable. + /// + UINT32 OverheatEnable : 1; + UINT32 Reserved2 : 3; + /// + /// [Bits 14:8] Pkg Threshold #1 Value. + /// + UINT32 Threshold1 : 7; + /// + /// [Bit 15] Pkg Threshold #1 Interrupt Enable. + /// + UINT32 Threshold1Enable : 1; + /// + /// [Bits 22:16] Pkg Threshold #2 Value. + /// + UINT32 Threshold2 : 7; + /// + /// [Bit 23] Pkg Threshold #2 Interrupt Enable. + /// + UINT32 Threshold2Enable : 1; + /// + /// [Bit 24] Pkg Power Limit Notification Enable. + /// + UINT32 PowerLimitNotificationEnable : 1; + UINT32 Reserved3 : 7; + UINT32 Reserved4 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER; + +/** + Trace/Profile Resource Control (R/W). Introduced at Display Family / Display + Model 06_0EH. + + @param ECX MSR_IA32_DEBUGCTL (0x000001D9) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_DEBUGCTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_DEBUGCTL_REGISTER. + + Example usage + @code + MSR_IA32_DEBUGCTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL); + AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64); + @endcode + @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM. +**/ +#define MSR_IA32_DEBUGCTL 0x000001D9 + +/** + MSR information returned for MSR index #MSR_IA32_DEBUGCTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a + /// running trace of the most recent branches taken by the processor in + /// the LBR stack. Introduced at Display Family / Display Model 06_01H. + /// + UINT32 LBR : 1; + /// + /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat + /// EFLAGS.TF as single-step on branches instead of single-step on + /// instructions. Introduced at Display Family / Display Model 06_01H. + /// + UINT32 BTF : 1; + UINT32 Reserved1 : 4; + /// + /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be + /// sent. Introduced at Display Family / Display Model 06_0EH. + /// + UINT32 TR : 1; + /// + /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to + /// be logged in a BTS buffer. Introduced at Display Family / Display + /// Model 06_0EH. + /// + UINT32 BTS : 1; + /// + /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular + /// fashion. When this bit is set, an interrupt is generated by the BTS + /// facility when the BTS buffer is full. Introduced at Display Family / + /// Display Model 06_0EH. + /// + UINT32 BTINT : 1; + /// + /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0. + /// Introduced at Display Family / Display Model 06_0FH. + /// + UINT32 BTS_OFF_OS : 1; + /// + /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0. + /// Introduced at Display Family / Display Model 06_0FH. + /// + UINT32 BTS_OFF_USR : 1; + /// + /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a + /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 FREEZE_LBRS_ON_PMI : 1; + /// + /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the + /// global counter control MSR are frozen (address 38FH) on a PMI request. + /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 FREEZE_PERFMON_ON_PMI : 1; + /// + /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to + /// receive and generate PMI on behalf of the uncore. Introduced at + /// Display Family / Display Model 06_1AH. + /// + UINT32 ENABLE_UNCORE_PMI : 1; + /// + /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace + /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1. + /// + UINT32 FREEZE_WHILE_SMM : 1; + /// + /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If + /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1). + /// + UINT32 RTM_DEBUG : 1; + UINT32 Reserved2 : 16; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_DEBUGCTL_REGISTER; + +/** + SMRR Base Address (Writeable only in SMM) Base address of SMM memory range. + If IA32_MTRRCAP.SMRR[11] = 1. + + @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER. + + Example usage + @code + MSR_IA32_SMRR_PHYSBASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE); + AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64); + @endcode + @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM. +**/ +#define MSR_IA32_SMRR_PHYSBASE 0x000001F2 + +/** + MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Type. Specifies memory type of the range. + /// + UINT32 Type : 8; + UINT32 Reserved1 : 4; + /// + /// [Bits 31:12] PhysBase. SMRR physical Base Address. + /// + UINT32 PhysBase : 20; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_SMRR_PHYSBASE_REGISTER; + +/** + SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If + IA32_MTRRCAP[SMRR] = 1. + + @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER. + + Example usage + @code + MSR_IA32_SMRR_PHYSMASK_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK); + AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64); + @endcode + @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM. +**/ +#define MSR_IA32_SMRR_PHYSMASK 0x000001F3 + +/** + MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1 : 11; + /// + /// [Bit 11] Valid Enable range mask. + /// + UINT32 Valid : 1; + /// + /// [Bits 31:12] PhysMask SMRR address range mask. + /// + UINT32 PhysMask : 20; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_SMRR_PHYSMASK_REGISTER; + +/** + DCA Capability (R). If CPUID.01H: ECX[18] = 1. + + @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP); + @endcode + @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM. +**/ +#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8 + +/** + If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1. + + @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP); + AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr); + @endcode + @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM. +**/ +#define MSR_IA32_CPU_DCA_CAP 0x000001F9 + +/** + DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1. + + @param ECX MSR_IA32_DCA_0_CAP (0x000001FA) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_DCA_0_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_DCA_0_CAP_REGISTER. + + Example usage + @code + MSR_IA32_DCA_0_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP); + AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64); + @endcode + @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM. +**/ +#define MSR_IA32_DCA_0_CAP 0x000001FA + +/** + MSR information returned for MSR index #MSR_IA32_DCA_0_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no + /// defeatures are set. + /// + UINT32 DCA_ACTIVE : 1; + /// + /// [Bits 2:1] TRANSACTION. + /// + UINT32 TRANSACTION : 2; + /// + /// [Bits 6:3] DCA_TYPE. + /// + UINT32 DCA_TYPE : 4; + /// + /// [Bits 10:7] DCA_QUEUE_SIZE. + /// + UINT32 DCA_QUEUE_SIZE : 4; + UINT32 Reserved1 : 2; + /// + /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW + /// side-effect. + /// + UINT32 DCA_DELAY : 4; + UINT32 Reserved2 : 7; + /// + /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit. + /// + UINT32 SW_BLOCK : 1; + UINT32 Reserved3 : 1; + /// + /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1). + /// + UINT32 HW_BLOCK : 1; + UINT32 Reserved4 : 5; + UINT32 Reserved5 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_DCA_0_CAP_REGISTER; + +/** + MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". + If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n. + + @param ECX MSR_IA32_MTRR_PHYSBASEn + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER. + + Example usage + @code + MSR_IA32_MTRR_PHYSBASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0); + AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64); + @endcode + @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. + MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. + MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. + MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. + MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. + MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. + MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. + MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. + MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. + MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM. + @{ +**/ +#define MSR_IA32_MTRR_PHYSBASE0 0x00000200 +#define MSR_IA32_MTRR_PHYSBASE1 0x00000202 +#define MSR_IA32_MTRR_PHYSBASE2 0x00000204 +#define MSR_IA32_MTRR_PHYSBASE3 0x00000206 +#define MSR_IA32_MTRR_PHYSBASE4 0x00000208 +#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A +#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C +#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E +#define MSR_IA32_MTRR_PHYSBASE8 0x00000210 +#define MSR_IA32_MTRR_PHYSBASE9 0x00000212 +/// @} + +/** + MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to + #MSR_IA32_MTRR_PHYSBASE9 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Type. Specifies memory type of the range. + /// + UINT32 Type : 8; + UINT32 Reserved1 : 4; + /// + /// [Bits 31:12] PhysBase. MTRR physical Base Address. + /// + UINT32 PhysBase : 20; + /// + /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address. + /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the + /// maximum physical address range supported by the processor. It is + /// reported by CPUID leaf function 80000008H. If CPUID does not support + /// leaf 80000008H, the processor supports 36-bit physical address size, + /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved. + /// + UINT32 PhysBaseHi : 32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MTRR_PHYSBASE_REGISTER; + +/** + MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". + If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n. + + @param ECX MSR_IA32_MTRR_PHYSMASKn + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER. + + Example usage + @code + MSR_IA32_MTRR_PHYSMASK_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0); + AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64); + @endcode + @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. + MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. + MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. + MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. + MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. + MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. + MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. + MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. + MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. + MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM. + @{ +**/ +#define MSR_IA32_MTRR_PHYSMASK0 0x00000201 +#define MSR_IA32_MTRR_PHYSMASK1 0x00000203 +#define MSR_IA32_MTRR_PHYSMASK2 0x00000205 +#define MSR_IA32_MTRR_PHYSMASK3 0x00000207 +#define MSR_IA32_MTRR_PHYSMASK4 0x00000209 +#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B +#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D +#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F +#define MSR_IA32_MTRR_PHYSMASK8 0x00000211 +#define MSR_IA32_MTRR_PHYSMASK9 0x00000213 +/// @} + +/** + MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to + #MSR_IA32_MTRR_PHYSMASK9 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1 : 11; + /// + /// [Bit 11] Valid Enable range mask. + /// + UINT32 V : 1; + /// + /// [Bits 31:12] PhysMask. MTRR address range mask. + /// + UINT32 PhysMask : 20; + /// + /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask. + /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the + /// maximum physical address range supported by the processor. It is + /// reported by CPUID leaf function 80000008H. If CPUID does not support + /// leaf 80000008H, the processor supports 36-bit physical address size, + /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved. + /// + UINT32 PhysMaskHi : 32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MTRR_PHYSMASK_REGISTER; + +/** + MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX64K_00000 0x00000250 + +/** + MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX16K_80000 0x00000258 + +/** + MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259 + +/** + See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268 + +/** + MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269 + +/** + MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A + +/** + MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B + +/** + MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C + +/** + MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D + +/** + MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E + +/** + MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F + +/** + IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1. + + @param ECX MSR_IA32_PAT (0x00000277) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PAT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PAT_REGISTER. + + Example usage + @code + MSR_IA32_PAT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT); + AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64); + @endcode + @note MSR_IA32_PAT is defined as IA32_PAT in SDM. +**/ +#define MSR_IA32_PAT 0x00000277 + +/** + MSR information returned for MSR index #MSR_IA32_PAT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] PA0. + /// + UINT32 PA0 : 3; + UINT32 Reserved1 : 5; + /// + /// [Bits 10:8] PA1. + /// + UINT32 PA1 : 3; + UINT32 Reserved2 : 5; + /// + /// [Bits 18:16] PA2. + /// + UINT32 PA2 : 3; + UINT32 Reserved3 : 5; + /// + /// [Bits 26:24] PA3. + /// + UINT32 PA3 : 3; + UINT32 Reserved4 : 5; + /// + /// [Bits 34:32] PA4. + /// + UINT32 PA4 : 3; + UINT32 Reserved5 : 5; + /// + /// [Bits 42:40] PA5. + /// + UINT32 PA5 : 3; + UINT32 Reserved6 : 5; + /// + /// [Bits 50:48] PA6. + /// + UINT32 PA6 : 3; + UINT32 Reserved7 : 5; + /// + /// [Bits 58:56] PA7. + /// + UINT32 PA7 : 3; + UINT32 Reserved8 : 5; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PAT_REGISTER; + +/** + Provides the programming interface to use corrected MC error signaling + capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n. + + @param ECX MSR_IA32_MCn_CTL2 + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MC_CTL2_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MC_CTL2_REGISTER. + + Example usage + @code + MSR_IA32_MC_CTL2_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2); + AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64); + @endcode + @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. + MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. + MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. + MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. + MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. + MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. + MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. + MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. + MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. + MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. + MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. + MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. + MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. + MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. + MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. + MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. + MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. + MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. + MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. + MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. + MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. + MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. + MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. + MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. + MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. + MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. + MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. + MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. + MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. + MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. + MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. + MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM. + @{ +**/ +#define MSR_IA32_MC0_CTL2 0x00000280 +#define MSR_IA32_MC1_CTL2 0x00000281 +#define MSR_IA32_MC2_CTL2 0x00000282 +#define MSR_IA32_MC3_CTL2 0x00000283 +#define MSR_IA32_MC4_CTL2 0x00000284 +#define MSR_IA32_MC5_CTL2 0x00000285 +#define MSR_IA32_MC6_CTL2 0x00000286 +#define MSR_IA32_MC7_CTL2 0x00000287 +#define MSR_IA32_MC8_CTL2 0x00000288 +#define MSR_IA32_MC9_CTL2 0x00000289 +#define MSR_IA32_MC10_CTL2 0x0000028A +#define MSR_IA32_MC11_CTL2 0x0000028B +#define MSR_IA32_MC12_CTL2 0x0000028C +#define MSR_IA32_MC13_CTL2 0x0000028D +#define MSR_IA32_MC14_CTL2 0x0000028E +#define MSR_IA32_MC15_CTL2 0x0000028F +#define MSR_IA32_MC16_CTL2 0x00000290 +#define MSR_IA32_MC17_CTL2 0x00000291 +#define MSR_IA32_MC18_CTL2 0x00000292 +#define MSR_IA32_MC19_CTL2 0x00000293 +#define MSR_IA32_MC20_CTL2 0x00000294 +#define MSR_IA32_MC21_CTL2 0x00000295 +#define MSR_IA32_MC22_CTL2 0x00000296 +#define MSR_IA32_MC23_CTL2 0x00000297 +#define MSR_IA32_MC24_CTL2 0x00000298 +#define MSR_IA32_MC25_CTL2 0x00000299 +#define MSR_IA32_MC26_CTL2 0x0000029A +#define MSR_IA32_MC27_CTL2 0x0000029B +#define MSR_IA32_MC28_CTL2 0x0000029C +#define MSR_IA32_MC29_CTL2 0x0000029D +#define MSR_IA32_MC30_CTL2 0x0000029E +#define MSR_IA32_MC31_CTL2 0x0000029F +/// @} + +/** + MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2 + to #MSR_IA32_MC31_CTL2 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 14:0] Corrected error count threshold. + /// + UINT32 CorrectedErrorCountThreshold : 15; + UINT32 Reserved1 : 15; + /// + /// [Bit 30] CMCI_EN. + /// + UINT32 CMCI_EN : 1; + UINT32 Reserved2 : 1; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MC_CTL2_REGISTER; + +/** + MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER. + + Example usage + @code + MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE); + AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64); + @endcode + @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM. +**/ +#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF + +/** + MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Default Memory Type. + /// + UINT32 Type : 3; + UINT32 Reserved1 : 7; + /// + /// [Bit 10] Fixed Range MTRR Enable. + /// + UINT32 FE : 1; + /// + /// [Bit 11] MTRR Enable. + /// + UINT32 E : 1; + UINT32 Reserved2 : 20; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MTRR_DEF_TYPE_REGISTER; + +/** + Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If + CPUID.0AH: EDX[4:0] > 0. + + @param ECX MSR_IA32_FIXED_CTR0 (0x00000309) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0); + AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr); + @endcode + @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM. +**/ +#define MSR_IA32_FIXED_CTR0 0x00000309 + +/** + Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If + CPUID.0AH: EDX[4:0] > 1. + + @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1); + AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr); + @endcode + @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM. +**/ +#define MSR_IA32_FIXED_CTR1 0x0000030A + +/** + Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If + CPUID.0AH: EDX[4:0] > 2. + + @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2); + AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr); + @endcode + @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM. +**/ +#define MSR_IA32_FIXED_CTR2 0x0000030B + +/** + RO. If CPUID.01H: ECX[15] = 1. + + @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER. + + Example usage + @code + MSR_IA32_PERF_CAPABILITIES_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES); + AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM. +**/ +#define MSR_IA32_PERF_CAPABILITIES 0x00000345 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 5:0] LBR format. + /// + UINT32 LBR_FMT : 6; + /// + /// [Bit 6] PEBS Trap. + /// + UINT32 PEBS_TRAP : 1; + /// + /// [Bit 7] PEBSSaveArchRegs. + /// + UINT32 PEBS_ARCH_REG : 1; + /// + /// [Bits 11:8] PEBS Record Format. + /// + UINT32 PEBS_REC_FMT : 4; + /// + /// [Bit 12] 1: Freeze while SMM is supported. + /// + UINT32 SMM_FREEZE : 1; + /// + /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx. + /// + UINT32 FW_WRITE : 1; + UINT32 Reserved1 : 18; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_CAPABILITIES_REGISTER; + +/** + Fixed-Function Performance Counter Control (R/W) Counter increments while + the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with + the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0] + > 1. + + @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER. + + Example usage + @code + MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL); + AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64); + @endcode + @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM. +**/ +#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D + +/** + MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0. + /// + UINT32 EN0_OS : 1; + /// + /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0. + /// + UINT32 EN0_Usr : 1; + /// + /// [Bit 2] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. + /// + UINT32 AnyThread0 : 1; + /// + /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows. + /// + UINT32 EN0_PMI : 1; + /// + /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0. + /// + UINT32 EN1_OS : 1; + /// + /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0. + /// + UINT32 EN1_Usr : 1; + /// + /// [Bit 6] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. + /// + UINT32 AnyThread1 : 1; + /// + /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows. + /// + UINT32 EN1_PMI : 1; + /// + /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0. + /// + UINT32 EN2_OS : 1; + /// + /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0. + /// + UINT32 EN2_Usr : 1; + /// + /// [Bit 10] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. + /// + UINT32 AnyThread2 : 1; + /// + /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows. + /// + UINT32 EN2_PMI : 1; + UINT32 Reserved1 : 20; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_FIXED_CTR_CTRL_REGISTER; + +/** + Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0. + + @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS); + @endcode + @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH: + /// EAX[15:8] > 0. + /// + UINT32 Ovf_PMC0 : 1; + /// + /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH: + /// EAX[15:8] > 1. + /// + UINT32 Ovf_PMC1 : 1; + /// + /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH: + /// EAX[15:8] > 2. + /// + UINT32 Ovf_PMC2 : 1; + /// + /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH: + /// EAX[15:8] > 3. + /// + UINT32 Ovf_PMC3 : 1; + UINT32 Reserved1 : 28; + /// + /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If + /// CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 Ovf_FixedCtr0 : 1; + /// + /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If + /// CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 Ovf_FixedCtr1 : 1; + /// + /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If + /// CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 Ovf_FixedCtr2 : 1; + UINT32 Reserved2 : 20; + /// + /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory + /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) + /// && IA32_RTIT_CTL.ToPA = 1. + /// + UINT32 Trace_ToPA_PMI : 1; + UINT32 Reserved3 : 2; + /// + /// [Bit 58] LBR_Frz: LBRs are frozen due to - + /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If + /// CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 LBR_Frz : 1; + /// + /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due + /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU + /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 CTR_Frz : 1; + /// + /// [Bit 60] ASCI: Data in the performance counters in the core PMU may + /// include contributions from the direct or indirect operation intel SGX + /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1. + /// + UINT32 ASCI : 1; + /// + /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH: + /// EAX[7:0] > 2. + /// + UINT32 Ovf_Uncore : 1; + /// + /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH: + /// EAX[7:0] > 0. + /// + UINT32 OvfBuf : 1; + /// + /// [Bit 63] CondChgd: status bits of this register has changed. If + /// CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 CondChgd : 1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER; + +/** + Global Performance Counter Control (R/W) Counter increments while the result + of ANDing respective enable bit in this MSR with the corresponding OS or USR + bits in the general-purpose or fixed counter control MSR is true. If + CPUID.0AH: EAX[7:0] > 0. + + @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL); + AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n. + /// Enable bitmask. Only the first n-1 bits are valid. + /// Bits n..31 are reserved. + /// + UINT32 EN_PMCn : 32; + /// + /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n. + /// Enable bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 EN_FIXED_CTRn : 32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER; + +/** + Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] > + 0 && CPUID.0AH: EAX[7:0] <= 3. + + @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL); + AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. + /// Clear bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 Ovf_PMCn : 32; + /// + /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. + /// If CPUID.0AH: EDX[4:0] > n. + /// Clear bitmask. Only the first n-1 bits are valid. + /// Bits 22:n are reserved. + /// + UINT32 Ovf_FIXED_CTRn : 23; + /// + /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, + /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1. + /// + UINT32 Trace_ToPA_PMI : 1; + UINT32 Reserved2 : 5; + /// + /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / + /// Display Model 06_2EH. + /// + UINT32 Ovf_Uncore : 1; + /// + /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 OvfBuf : 1; + /// + /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 CondChgd : 1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER; + +/** + Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH: + EAX[7:0] > 3. + + @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET); + AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. + /// Clear bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 Ovf_PMCn : 32; + /// + /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. + /// If CPUID.0AH: EDX[4:0] > n. + /// Clear bitmask. Only the first n-1 bits are valid. + /// Bits 22:n are reserved. + /// + UINT32 Ovf_FIXED_CTRn : 23; + /// + /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, + /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1. + /// + UINT32 Trace_ToPA_PMI : 1; + UINT32 Reserved2 : 2; + /// + /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 LBR_Frz : 1; + /// + /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 CTR_Frz : 1; + /// + /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 ASCI : 1; + /// + /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / + /// Display Model 06_2EH. + /// + UINT32 Ovf_Uncore : 1; + /// + /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 OvfBuf : 1; + /// + /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 CondChgd : 1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER; + +/** + Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH: + EAX[7:0] > 3. + + @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET); + AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n. + /// Set bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 Ovf_PMCn : 32; + /// + /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1. + /// If CPUID.0AH: EAX[7:0] > n. + /// Set bitmask. Only the first n-1 bits are valid. + /// Bits 22:n are reserved. + /// + UINT32 Ovf_FIXED_CTRn : 23; + /// + /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 Trace_ToPA_PMI : 1; + UINT32 Reserved2 : 2; + /// + /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 LBR_Frz : 1; + /// + /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 CTR_Frz : 1; + /// + /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 ASCI : 1; + /// + /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 Ovf_Uncore : 1; + /// + /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 OvfBuf : 1; + UINT32 Reserved3 : 1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER; + +/** + Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] > + 3. + + @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE); + @endcode + @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n. + /// Status bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 IA32_PERFEVTSELn : 32; + /// + /// [Bits 62:32] IA32_FIXED_CTRn in use. + /// If CPUID.0AH: EAX[7:0] > n. + /// Status bitmask. Only the first n-1 bits are valid. + /// Bits 30:n are reserved. + /// + UINT32 IA32_FIXED_CTRn : 31; + /// + /// [Bit 63] PMI in use. + /// + UINT32 PMI : 1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER; + +/** + PEBS Control (R/W). + + @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PEBS_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PEBS_ENABLE_REGISTER. + + Example usage + @code + MSR_IA32_PEBS_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE); + AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64); + @endcode + @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM. +**/ +#define MSR_IA32_PEBS_ENABLE 0x000003F1 + +/** + MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family / + /// Display Model 06_0FH. + /// + UINT32 Enable : 1; + /// + /// [Bits 3:1] Reserved or Model specific. + /// + UINT32 Reserved1 : 3; + UINT32 Reserved2 : 28; + /// + /// [Bits 35:32] Reserved or Model specific. + /// + UINT32 Reserved3 : 4; + UINT32 Reserved4 : 28; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PEBS_ENABLE_REGISTER; + +/** + MCn_CTL. If IA32_MCG_CAP.CNT > n. + + @param ECX MSR_IA32_MCn_CTL + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL); + AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr); + @endcode + @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. + MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. + MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. + MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. + MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. + MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. + MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. + MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. + MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. + MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. + MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. + MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. + MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. + MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. + MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. + MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. + MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. + MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. + MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. + MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. + MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. + MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. + MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. + MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. + MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. + MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. + MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. + MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. + MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM. + @{ +**/ +#define MSR_IA32_MC0_CTL 0x00000400 +#define MSR_IA32_MC1_CTL 0x00000404 +#define MSR_IA32_MC2_CTL 0x00000408 +#define MSR_IA32_MC3_CTL 0x0000040C +#define MSR_IA32_MC4_CTL 0x00000410 +#define MSR_IA32_MC5_CTL 0x00000414 +#define MSR_IA32_MC6_CTL 0x00000418 +#define MSR_IA32_MC7_CTL 0x0000041C +#define MSR_IA32_MC8_CTL 0x00000420 +#define MSR_IA32_MC9_CTL 0x00000424 +#define MSR_IA32_MC10_CTL 0x00000428 +#define MSR_IA32_MC11_CTL 0x0000042C +#define MSR_IA32_MC12_CTL 0x00000430 +#define MSR_IA32_MC13_CTL 0x00000434 +#define MSR_IA32_MC14_CTL 0x00000438 +#define MSR_IA32_MC15_CTL 0x0000043C +#define MSR_IA32_MC16_CTL 0x00000440 +#define MSR_IA32_MC17_CTL 0x00000444 +#define MSR_IA32_MC18_CTL 0x00000448 +#define MSR_IA32_MC19_CTL 0x0000044C +#define MSR_IA32_MC20_CTL 0x00000450 +#define MSR_IA32_MC21_CTL 0x00000454 +#define MSR_IA32_MC22_CTL 0x00000458 +#define MSR_IA32_MC23_CTL 0x0000045C +#define MSR_IA32_MC24_CTL 0x00000460 +#define MSR_IA32_MC25_CTL 0x00000464 +#define MSR_IA32_MC26_CTL 0x00000468 +#define MSR_IA32_MC27_CTL 0x0000046C +#define MSR_IA32_MC28_CTL 0x00000470 +/// @} + +/** + MCn_STATUS. If IA32_MCG_CAP.CNT > n. + + @param ECX MSR_IA32_MCn_STATUS + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS); + AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr); + @endcode + @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. + MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. + MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. + MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. + MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. + MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. + MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. + MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. + MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. + MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. + MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. + MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. + MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. + MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. + MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. + MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. + MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. + MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. + MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. + MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. + MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. + MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. + MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. + MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. + MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. + MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. + MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. + MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. + MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM. + @{ +**/ +#define MSR_IA32_MC0_STATUS 0x00000401 +#define MSR_IA32_MC1_STATUS 0x00000405 +#define MSR_IA32_MC2_STATUS 0x00000409 +#define MSR_IA32_MC3_STATUS 0x0000040D +#define MSR_IA32_MC4_STATUS 0x00000411 +#define MSR_IA32_MC5_STATUS 0x00000415 +#define MSR_IA32_MC6_STATUS 0x00000419 +#define MSR_IA32_MC7_STATUS 0x0000041D +#define MSR_IA32_MC8_STATUS 0x00000421 +#define MSR_IA32_MC9_STATUS 0x00000425 +#define MSR_IA32_MC10_STATUS 0x00000429 +#define MSR_IA32_MC11_STATUS 0x0000042D +#define MSR_IA32_MC12_STATUS 0x00000431 +#define MSR_IA32_MC13_STATUS 0x00000435 +#define MSR_IA32_MC14_STATUS 0x00000439 +#define MSR_IA32_MC15_STATUS 0x0000043D +#define MSR_IA32_MC16_STATUS 0x00000441 +#define MSR_IA32_MC17_STATUS 0x00000445 +#define MSR_IA32_MC18_STATUS 0x00000449 +#define MSR_IA32_MC19_STATUS 0x0000044D +#define MSR_IA32_MC20_STATUS 0x00000451 +#define MSR_IA32_MC21_STATUS 0x00000455 +#define MSR_IA32_MC22_STATUS 0x00000459 +#define MSR_IA32_MC23_STATUS 0x0000045D +#define MSR_IA32_MC24_STATUS 0x00000461 +#define MSR_IA32_MC25_STATUS 0x00000465 +#define MSR_IA32_MC26_STATUS 0x00000469 +#define MSR_IA32_MC27_STATUS 0x0000046D +#define MSR_IA32_MC28_STATUS 0x00000471 +/// @} + +/** + MCn_ADDR. If IA32_MCG_CAP.CNT > n. + + @param ECX MSR_IA32_MCn_ADDR + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR); + AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr); + @endcode + @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. + MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. + MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. + MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. + MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. + MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. + MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. + MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. + MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. + MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. + MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. + MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. + MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. + MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. + MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. + MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. + MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. + MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. + MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. + MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. + MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. + MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. + MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. + MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. + MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. + MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. + MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. + MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. + MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM. + @{ +**/ +#define MSR_IA32_MC0_ADDR 0x00000402 +#define MSR_IA32_MC1_ADDR 0x00000406 +#define MSR_IA32_MC2_ADDR 0x0000040A +#define MSR_IA32_MC3_ADDR 0x0000040E +#define MSR_IA32_MC4_ADDR 0x00000412 +#define MSR_IA32_MC5_ADDR 0x00000416 +#define MSR_IA32_MC6_ADDR 0x0000041A +#define MSR_IA32_MC7_ADDR 0x0000041E +#define MSR_IA32_MC8_ADDR 0x00000422 +#define MSR_IA32_MC9_ADDR 0x00000426 +#define MSR_IA32_MC10_ADDR 0x0000042A +#define MSR_IA32_MC11_ADDR 0x0000042E +#define MSR_IA32_MC12_ADDR 0x00000432 +#define MSR_IA32_MC13_ADDR 0x00000436 +#define MSR_IA32_MC14_ADDR 0x0000043A +#define MSR_IA32_MC15_ADDR 0x0000043E +#define MSR_IA32_MC16_ADDR 0x00000442 +#define MSR_IA32_MC17_ADDR 0x00000446 +#define MSR_IA32_MC18_ADDR 0x0000044A +#define MSR_IA32_MC19_ADDR 0x0000044E +#define MSR_IA32_MC20_ADDR 0x00000452 +#define MSR_IA32_MC21_ADDR 0x00000456 +#define MSR_IA32_MC22_ADDR 0x0000045A +#define MSR_IA32_MC23_ADDR 0x0000045E +#define MSR_IA32_MC24_ADDR 0x00000462 +#define MSR_IA32_MC25_ADDR 0x00000466 +#define MSR_IA32_MC26_ADDR 0x0000046A +#define MSR_IA32_MC27_ADDR 0x0000046E +#define MSR_IA32_MC28_ADDR 0x00000472 +/// @} + +/** + MCn_MISC. If IA32_MCG_CAP.CNT > n. + + @param ECX MSR_IA32_MCn_MISC + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC); + AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr); + @endcode + @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. + MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. + MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. + MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. + MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. + MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. + MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. + MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. + MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. + MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. + MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. + MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. + MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. + MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. + MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. + MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. + MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. + MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. + MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. + MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. + MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. + MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. + MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. + MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. + MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. + MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. + MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. + MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. + MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM. + @{ +**/ +#define MSR_IA32_MC0_MISC 0x00000403 +#define MSR_IA32_MC1_MISC 0x00000407 +#define MSR_IA32_MC2_MISC 0x0000040B +#define MSR_IA32_MC3_MISC 0x0000040F +#define MSR_IA32_MC4_MISC 0x00000413 +#define MSR_IA32_MC5_MISC 0x00000417 +#define MSR_IA32_MC6_MISC 0x0000041B +#define MSR_IA32_MC7_MISC 0x0000041F +#define MSR_IA32_MC8_MISC 0x00000423 +#define MSR_IA32_MC9_MISC 0x00000427 +#define MSR_IA32_MC10_MISC 0x0000042B +#define MSR_IA32_MC11_MISC 0x0000042F +#define MSR_IA32_MC12_MISC 0x00000433 +#define MSR_IA32_MC13_MISC 0x00000437 +#define MSR_IA32_MC14_MISC 0x0000043B +#define MSR_IA32_MC15_MISC 0x0000043F +#define MSR_IA32_MC16_MISC 0x00000443 +#define MSR_IA32_MC17_MISC 0x00000447 +#define MSR_IA32_MC18_MISC 0x0000044B +#define MSR_IA32_MC19_MISC 0x0000044F +#define MSR_IA32_MC20_MISC 0x00000453 +#define MSR_IA32_MC21_MISC 0x00000457 +#define MSR_IA32_MC22_MISC 0x0000045B +#define MSR_IA32_MC23_MISC 0x0000045F +#define MSR_IA32_MC24_MISC 0x00000463 +#define MSR_IA32_MC25_MISC 0x00000467 +#define MSR_IA32_MC26_MISC 0x0000046B +#define MSR_IA32_MC27_MISC 0x0000046F +#define MSR_IA32_MC28_MISC 0x00000473 +/// @} + +/** + Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic + VMX Information.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_BASIC (0x00000480) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + MSR_IA32_VMX_BASIC_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC); + @endcode + @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM. +**/ +#define MSR_IA32_VMX_BASIC 0x00000480 + +/** + MSR information returned for MSR index #MSR_IA32_VMX_BASIC +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 30:0] VMCS revision identifier used by the processor. Processors + /// that use the same VMCS revision identifier use the same size for VMCS + /// regions (see subsequent item on bits 44:32). + /// + /// @note Earlier versions of this manual specified that the VMCS revision + /// identifier was a 32-bit field in bits 31:0 of this MSR. For all + /// processors produced prior to this change, bit 31 of this MSR was read + /// as 0. + /// + UINT32 VmcsRevisonId : 31; + UINT32 MustBeZero : 1; + /// + /// [Bit 44:32] Reports the number of bytes that software should allocate + /// for the VMXON region and any VMCS region. It is a value greater than + /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear). + /// + UINT32 VmcsSize : 13; + UINT32 Reserved1 : 3; + /// + /// [Bit 48] Indicates the width of the physical addresses that may be used + /// for the VMXON region, each VMCS, and data structures referenced by + /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX + /// transitions). If the bit is 0, these addresses are limited to the + /// processor's physical-address width. If the bit is 1, these addresses + /// are limited to 32 bits. This bit is always 0 for processors that + /// support Intel 64 architecture. + /// + /// @note On processors that support Intel 64 architecture, the pointer + /// must not set bits beyond the processor's physical address width. + /// + UINT32 VmcsAddressWidth : 1; + /// + /// [Bit 49] If bit 49 is read as 1, the logical processor supports the + /// dual-monitor treatment of system-management interrupts and + /// system-management mode. See Section 34.15 for details of this treatment. + /// + UINT32 DualMonitor : 1; + /// + /// [Bit 53:50] report the memory type that should be used for the VMCS, + /// for data structures referenced by pointers in the VMCS (I/O bitmaps, + /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG + /// header. If software needs to access these data structures (e.g., to + /// modify the contents of the MSR bitmaps), it can configure the paging + /// structures to map them into the linear-address space. If it does so, + /// it should establish mappings that use the memory type reported bits + /// 53:50 in this MSR. + /// + /// As of this writing, all processors that support VMX operation indicate + /// the write-back type. + /// + /// If software needs to access these data structures (e.g., to modify + /// the contents of the MSR bitmaps), it can configure the paging + /// structures to map them into the linear-address space. If it does so, + /// it should establish mappings that use the memory type reported in this + /// MSR. + /// + /// @note Alternatively, software may map any of these regions or + /// structures with the UC memory type. (This may be necessary for the MSEG + /// header.) Doing so is discouraged unless necessary as it will cause the + /// performance of software accesses to those structures to suffer. + /// + /// + UINT32 MemoryType : 4; + /// + /// [Bit 54] If bit 54 is read as 1, the processor reports information in + /// the VM-exit instruction-information field on VM exitsdue to execution + /// of the INS and OUTS instructions (see Section 27.2.4). This reporting + /// is done only if this bit is read as 1. + /// + UINT32 InsOutsReporting : 1; + /// + /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may + /// be cleared to 0. See Appendix A.2 for details. It also reports support + /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS, + /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and + /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2, + /// Appendix A.4, and Appendix A.5 for details. + /// + UINT32 VmxControls : 1; + UINT32 Reserved2 : 8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_VMX_BASIC_REGISTER; + +/// +/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType +/// +#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00 +#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06 +/// +/// @} +/// + +/** + Capability Reporting Register of Pinbased VM-execution Controls (R/O) See + Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS); + @endcode + @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM. +**/ +#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 + +/** + Capability Reporting Register of Primary Processor-based VM-execution + Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution + Controls.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS); + @endcode + @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM. +**/ +#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 + +/** + Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4, + "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS); + @endcode + @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM. +**/ +#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 + +/** + Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5, + "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS); + @endcode + @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM. +**/ +#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 + +/** + Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6, + "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_MISC (0x00000485) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + IA32_VMX_MISC_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC); + @endcode + @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM. +**/ +#define MSR_IA32_VMX_MISC 0x00000485 + +/** + MSR information returned for MSR index #IA32_VMX_MISC +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 4:0] Reports a value X that specifies the relationship between the + /// rate of the VMX-preemption timer and that of the timestamp counter (TSC). + /// Specifically, the VMX-preemption timer (if it is active) counts down by + /// 1 every time bit X in the TSC changes due to a TSC increment. + /// + UINT32 VmxTimerRatio : 5; + /// + /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA + /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more + /// details. This bit is read as 1 on any logical processor that supports + /// the 1-setting of the "unrestricted guest" VM-execution control. + /// + UINT32 VmExitEferLma : 1; + /// + /// [Bit 6] reports (if set) the support for activity state 1 (HLT). + /// + UINT32 HltActivityStateSupported : 1; + /// + /// [Bit 7] reports (if set) the support for activity state 2 (shutdown). + /// + UINT32 ShutdownActivityStateSupported : 1; + /// + /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI). + /// + UINT32 WaitForSipiActivityStateSupported : 1; + UINT32 Reserved1 : 5; + /// + /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used + /// in VMX operation. If the processor supports Intel PT but does not allow + /// it to be used in VMX operation, execution of VMXON clears + /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30); + /// any attempt to set that bit while in VMX operation (including VMX root + /// operation) using the WRMSR instruction causes a general-protection + /// exception. + /// + UINT32 ProcessorTraceSupported : 1; + /// + /// [Bit 15] If read as 1, the RDMSR instruction can be used in system- + /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH). + /// See Section 34.15.6.3. + /// + UINT32 SmBaseMsrSupported : 1; + /// + /// [Bits 24:16] Indicate the number of CR3-target values supported by the + /// processor. This number is a value between 0 and 256, inclusive (bit 24 + /// is set if and only if bits 23:16 are clear). + /// + UINT32 NumberOfCr3TargetValues : 9; + /// + /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum + /// number of MSRs that should appear in the VM-exit MSR-store list, the + /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if + /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the + /// recommended maximum number of MSRs to be included in each list. If the + /// limit is exceeded, undefined processor behavior may result (including a + /// machine check during the VMX transition). + /// + UINT32 MsrStoreListMaximum : 3; + /// + /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set + /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1 + /// (see Section 34.14.4). + /// + UINT32 BlockSmiSupported : 1; + /// + /// [Bit 29] read as 1, software can use VMWRITE to write to any supported + /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit + /// information fields. + /// + UINT32 VmWriteSupported : 1; + /// + /// [Bit 30] If read as 1, VM entry allows injection of a software + /// interrupt, software exception, or privileged software exception with an + /// instruction length of 0. + /// + UINT32 VmInjectSupported : 1; + UINT32 Reserved2 : 1; + /// + /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the + /// processor. + /// + UINT32 MsegRevisionIdentifier : 32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} IA32_VMX_MISC_REGISTER; + +/** + Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7, + "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0); + @endcode + @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM. +**/ +#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 + +/** + Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7, + "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1); + @endcode + @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM. +**/ +#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 + +/** + Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8, + "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488) ... 6692 lines suppressed ...

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[reactos] 03/06: [NTOS:KE/x64] Improve CPU feature detection
by Timo Kreuzer 03 Oct '23

03 Oct '23

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=70f6ed8ee35b638285f40… commit 70f6ed8ee35b638285f40ee8231c0dffa3052c0a Author: Timo Kreuzer <timo.kreuzer(a)reactos.org> AuthorDate: Sat Aug 26 16:15:38 2023 +0300 Commit: Timo Kreuzer <timo.kreuzer(a)reactos.org> CommitDate: Tue Oct 3 19:45:44 2023 +0300 [NTOS:KE/x64] Improve CPU feature detection - Use 64 bit feature flags (with a hack in the PRCB) - Improve setting up SharedUserData->ProcessorFeatures --- ntoskrnl/include/internal/amd64/ke.h | 2 +- ntoskrnl/ke/amd64/cpu.c | 4 +-- ntoskrnl/ke/amd64/kiinit.c | 59 +++++++++++++++++++++++++++--------- sdk/include/ndk/amd64/ketypes.h | 3 ++ 4 files changed, 50 insertions(+), 18 deletions(-) diff --git a/ntoskrnl/include/internal/amd64/ke.h b/ntoskrnl/include/internal/amd64/ke.h index 3287e7567c2..84246690638 100644 --- a/ntoskrnl/include/internal/amd64/ke.h +++ b/ntoskrnl/include/internal/amd64/ke.h @@ -418,7 +418,7 @@ VOID Ki386InitializeLdt(VOID); VOID Ki386SetProcessorFeatures(VOID); VOID KiGetCacheInformation(VOID); VOID KiSetProcessorType(VOID); -ULONG KiGetFeatureBits(VOID); +ULONG64 KiGetFeatureBits(VOID); VOID KiInitializeCpuFeatures(VOID); #if DBG VOID KiReportCpuFeatures(IN PKPRCB Prcb); diff --git a/ntoskrnl/ke/amd64/cpu.c b/ntoskrnl/ke/amd64/cpu.c index 075326d91ce..d5086b950d3 100644 --- a/ntoskrnl/ke/amd64/cpu.c +++ b/ntoskrnl/ke/amd64/cpu.c @@ -145,13 +145,13 @@ KiSetProcessorType(VOID) KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping; } -ULONG +ULONG64 NTAPI KiGetFeatureBits(VOID) { PKPRCB Prcb = KeGetCurrentPrcb(); ULONG Vendor; - ULONG FeatureBits = 0; + ULONG64 FeatureBits = 0; CPU_INFO CpuInfo; /* Get the Vendor ID */ diff --git a/ntoskrnl/ke/amd64/kiinit.c b/ntoskrnl/ke/amd64/kiinit.c index a0dc2c5c5b8..6d6ffbd3f2a 100644 --- a/ntoskrnl/ke/amd64/kiinit.c +++ b/ntoskrnl/ke/amd64/kiinit.c @@ -170,7 +170,7 @@ NTAPI KiInitializeCpu(PKIPCR Pcr) { ULONG64 Pat; - ULONG FeatureBits; + ULONG64 FeatureBits; /* Initialize gs */ KiInitializeSegments(); @@ -199,7 +199,8 @@ KiInitializeCpu(PKIPCR Pcr) FeatureBits |= KF_NX_ENABLED; /* Save feature bits */ - Pcr->Prcb.FeatureBits = FeatureBits; + Pcr->Prcb.FeatureBits = (ULONG)FeatureBits; + Pcr->Prcb.FeatureBitsHigh = FeatureBits >> 32; /* Enable fx save restore support */ __writecr4(__readcr4() | CR4_FXSR); @@ -283,6 +284,8 @@ KiInitializeKernelMachineDependent( IN PKPRCB Prcb, IN PLOADER_PARAMETER_BLOCK LoaderBlock) { + ULONG64 FeatureBits; + /* Set boot-level flags */ KeI386CpuType = Prcb->CpuType; KeI386CpuStep = Prcb->CpuStep; @@ -291,26 +294,52 @@ KiInitializeKernelMachineDependent( if (Prcb->CpuID) KeProcessorRevision = Prcb->CpuStep; + FeatureBits = Prcb->FeatureBits | (ULONG64)Prcb->FeatureBitsHigh << 32; + /* Set basic CPU Features that user mode can read */ + SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_PRECISION_ERRATA] = FALSE; + SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_EMULATED] = FALSE; SharedUserData->ProcessorFeatures[PF_COMPARE_EXCHANGE_DOUBLE] = TRUE; - SharedUserData->ProcessorFeatures[PF_RDTSC_INSTRUCTION_AVAILABLE] = TRUE; - SharedUserData->ProcessorFeatures[PF_PPC_MOVEMEM_64BIT_OK] = TRUE; - SharedUserData->ProcessorFeatures[PF_PAE_ENABLED] = TRUE; // ??? - SharedUserData->ProcessorFeatures[PF_NX_ENABLED] = TRUE; - SharedUserData->ProcessorFeatures[PF_FASTFAIL_AVAILABLE] = TRUE; - SharedUserData->ProcessorFeatures[PF_XSAVE_ENABLED] = TRUE; SharedUserData->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] = - (Prcb->FeatureBits & KF_MMX) ? TRUE: FALSE; + (FeatureBits & KF_MMX) ? TRUE : FALSE; SharedUserData->ProcessorFeatures[PF_XMMI_INSTRUCTIONS_AVAILABLE] = - ((Prcb->FeatureBits & KF_FXSR) && (Prcb->FeatureBits & KF_XMMI)) ? TRUE: FALSE; - SharedUserData->ProcessorFeatures[PF_XMMI64_INSTRUCTIONS_AVAILABLE] = - ((Prcb->FeatureBits & KF_FXSR) && (Prcb->FeatureBits & KF_XMMI64)) ? TRUE: FALSE; + ((FeatureBits & KF_FXSR) && (FeatureBits & KF_XMMI)) ? TRUE : FALSE; SharedUserData->ProcessorFeatures[PF_3DNOW_INSTRUCTIONS_AVAILABLE] = - (Prcb->FeatureBits & KF_3DNOW) ? TRUE: FALSE; + (FeatureBits & KF_3DNOW) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_RDTSC_INSTRUCTION_AVAILABLE] = TRUE; + SharedUserData->ProcessorFeatures[PF_PAE_ENABLED] = TRUE; // ??? + SharedUserData->ProcessorFeatures[PF_XMMI64_INSTRUCTIONS_AVAILABLE] = + ((FeatureBits & KF_FXSR) && (FeatureBits & KF_XMMI64)) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_SSE_DAZ_MODE_AVAILABLE] = FALSE; // ??? + SharedUserData->ProcessorFeatures[PF_NX_ENABLED] = TRUE; SharedUserData->ProcessorFeatures[PF_SSE3_INSTRUCTIONS_AVAILABLE] = - (Prcb->FeatureBits & KF_SSE3) ? TRUE: FALSE; + (FeatureBits & KF_SSE3) ? TRUE : FALSE; SharedUserData->ProcessorFeatures[PF_COMPARE_EXCHANGE128] = - (Prcb->FeatureBits & KF_CMPXCHG16B) ? TRUE: FALSE; + (FeatureBits & KF_CMPXCHG16B) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_COMPARE64_EXCHANGE128] = FALSE; // ??? + SharedUserData->ProcessorFeatures[PF_CHANNELS_ENABLED] = FALSE; // ??? + SharedUserData->ProcessorFeatures[PF_XSAVE_ENABLED] = FALSE; // FIXME + SharedUserData->ProcessorFeatures[PF_SECOND_LEVEL_ADDRESS_TRANSLATION] = + (FeatureBits & KF_SLAT) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_VIRT_FIRMWARE_ENABLED] = + (FeatureBits & KF_VIRT_FIRMWARE_ENABLED) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_RDWRFSGSBASE_AVAILABLE] = + (FeatureBits & KF_RDWRFSGSBASE) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_FASTFAIL_AVAILABLE] = TRUE; + SharedUserData->ProcessorFeatures[PF_RDRAND_INSTRUCTION_AVAILABLE] = + (FeatureBits & KF_RDRAND) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_RDTSCP_INSTRUCTION_AVAILABLE] = + (FeatureBits & KF_RDTSCP) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_RDPID_INSTRUCTION_AVAILABLE] = FALSE; // ??? + SharedUserData->ProcessorFeatures[PF_SSSE3_INSTRUCTIONS_AVAILABLE] = + (FeatureBits & KF_SSSE3) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_SSE4_1_INSTRUCTIONS_AVAILABLE] = + (FeatureBits & KF_SSE4_1) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_SSE4_2_INSTRUCTIONS_AVAILABLE] = + (FeatureBits & KF_SSE4_2) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_AVX_INSTRUCTIONS_AVAILABLE] = FALSE; // FIXME + SharedUserData->ProcessorFeatures[PF_AVX2_INSTRUCTIONS_AVAILABLE] = FALSE; // FIXME + SharedUserData->ProcessorFeatures[PF_AVX512F_INSTRUCTIONS_AVAILABLE] = FALSE; // FIXME /* Set the default NX policy (opt-in) */ SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_OPTIN; diff --git a/sdk/include/ndk/amd64/ketypes.h b/sdk/include/ndk/amd64/ketypes.h index 553c3bdb956..1f306de1d2c 100644 --- a/sdk/include/ndk/amd64/ketypes.h +++ b/sdk/include/ndk/amd64/ketypes.h @@ -910,6 +910,9 @@ typedef struct _KPRCB CACHE_DESCRIPTOR Cache[5]; ULONG CacheCount; #endif +#ifdef __REACTOS__ + ULONG FeatureBitsHigh; +#endif } KPRCB, *PKPRCB; //

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[reactos] 02/06: [NDK] Update kernel feature bits constants
by Timo Kreuzer 03 Oct '23

03 Oct '23

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=47c1dcd023b7f31c8b901… commit 47c1dcd023b7f31c8b9016477c2652e6ffbb8ac8 Author: Timo Kreuzer <timo.kreuzer(a)reactos.org> AuthorDate: Sat Aug 26 12:10:04 2023 +0300 Commit: Timo Kreuzer <timo.kreuzer(a)reactos.org> CommitDate: Tue Oct 3 19:45:44 2023 +0300 [NDK] Update kernel feature bits constants - Move them into architecture specific headers. - Add missing constants based on https://www.geoffchappell.com/studies/windows/km/ntoskrnl/structs/kprcb/fea… - Yes, they are 64 bits --- ntoskrnl/ke/amd64/cpu.c | 19 ++++++-------- sdk/include/ndk/amd64/ketypes.h | 56 +++++++++++++++++++++++++++++++++++++++++ sdk/include/ndk/i386/ketypes.h | 46 +++++++++++++++++++++++++++++++++ sdk/include/ndk/ketypes.h | 33 ------------------------ 4 files changed, 109 insertions(+), 45 deletions(-) diff --git a/ntoskrnl/ke/amd64/cpu.c b/ntoskrnl/ke/amd64/cpu.c index 274320c1b12..075326d91ce 100644 --- a/ntoskrnl/ke/amd64/cpu.c +++ b/ntoskrnl/ke/amd64/cpu.c @@ -151,7 +151,7 @@ KiGetFeatureBits(VOID) { PKPRCB Prcb = KeGetCurrentPrcb(); ULONG Vendor; - ULONG FeatureBits = KF_WORKING_PTE; + ULONG FeatureBits = 0; CPU_INFO CpuInfo; /* Get the Vendor ID */ @@ -167,7 +167,7 @@ KiGetFeatureBits(VOID) Prcb->InitialApicId = (UCHAR)(CpuInfo.Ebx >> 24); /* Convert all CPUID Feature bits into our format */ - if (CpuInfo.Edx & X86_FEATURE_VME) FeatureBits |= KF_V86_VIS | KF_CR4; + if (CpuInfo.Edx & X86_FEATURE_VME) FeatureBits |= KF_CR4; if (CpuInfo.Edx & X86_FEATURE_PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4; if (CpuInfo.Edx & X86_FEATURE_TSC) FeatureBits |= KF_RDTSC; if (CpuInfo.Edx & X86_FEATURE_CX8) FeatureBits |= KF_CMPXCHG8B; @@ -183,11 +183,9 @@ KiGetFeatureBits(VOID) if (CpuInfo.Edx & X86_FEATURE_SSE2) FeatureBits |= KF_XMMI64; if (CpuInfo.Ecx & X86_FEATURE_SSE3) FeatureBits |= KF_SSE3; - //if (CpuInfo.Ecx & X86_FEATURE_MONITOR) FeatureBits |= KF_MONITOR; - //if (CpuInfo.Ecx & X86_FEATURE_SSSE3) FeatureBits |= KF_SSE3SUP; + //if (CpuInfo.Ecx & X86_FEATURE_SSSE3) FeatureBits |= KF_SSSE3; if (CpuInfo.Ecx & X86_FEATURE_CX16) FeatureBits |= KF_CMPXCHG16B; - //if (CpuInfo.Ecx & X86_FEATURE_SSE41) FeatureBits |= KF_SSE41; - //if (CpuInfo.Ecx & X86_FEATURE_POPCNT) FeatureBits |= KF_POPCNT; + //if (CpuInfo.Ecx & X86_FEATURE_SSE41) FeatureBits |= KF_SSE4_1; if (CpuInfo.Ecx & X86_FEATURE_XSAVE) FeatureBits |= KF_XSTATE; /* Check if the CPU has hyper-threading */ @@ -250,7 +248,7 @@ KiReportCpuFeatures(IN PKPRCB Prcb) DPRINT1("Supported CPU features: "); #define print_kf_bit(kf_value) if (Prcb->FeatureBits & kf_value) DbgPrint(#kf_value " ") - print_kf_bit(KF_V86_VIS); + print_kf_bit(KF_SMEP); print_kf_bit(KF_RDTSC); print_kf_bit(KF_CR4); print_kf_bit(KF_CMOV); @@ -260,7 +258,6 @@ KiReportCpuFeatures(IN PKPRCB Prcb) print_kf_bit(KF_CMPXCHG8B); print_kf_bit(KF_CMPXCHG16B); print_kf_bit(KF_MMX); - print_kf_bit(KF_WORKING_PTE); print_kf_bit(KF_PAT); print_kf_bit(KF_FXSR); print_kf_bit(KF_FAST_SYSCALL); @@ -272,10 +269,8 @@ KiReportCpuFeatures(IN PKPRCB Prcb) print_kf_bit(KF_NX_DISABLED); print_kf_bit(KF_NX_ENABLED); print_kf_bit(KF_SSE3); - //print_kf_bit(KF_SSE3SUP); - //print_kf_bit(KF_SSE41); - //print_kf_bit(KF_MONITOR); - //print_kf_bit(KF_POPCNT); + print_kf_bit(KF_SSSE3); + print_kf_bit(KF_SSE4_1); print_kf_bit(KF_XSTATE); #undef print_kf_bit diff --git a/sdk/include/ndk/amd64/ketypes.h b/sdk/include/ndk/amd64/ketypes.h index e09c0a884ce..553c3bdb956 100644 --- a/sdk/include/ndk/amd64/ketypes.h +++ b/sdk/include/ndk/amd64/ketypes.h @@ -24,6 +24,62 @@ Author: // Dependencies // +// +// Kernel Feature Bits +// See https://www.geoffchappell.com/studies/windows/km/ntoskrnl/structs/kprcb/fea… +// +#define KF_SMEP 0x00000001 // Win 6.2 +#define KF_RDTSC 0x00000002 // From ks386.inc, ksamd64.inc +#define KF_CR4 0x00000004 // From ks386.inc, ksamd64.inc +#define KF_CMOV 0x00000008 +#define KF_GLOBAL_PAGE 0x00000010 // From ks386.inc, ksamd64.inc +#define KF_LARGE_PAGE 0x00000020 // From ks386.inc, ksamd64.inc +#define KF_MTRR 0x00000040 +#define KF_CMPXCHG8B 0x00000080 // From ks386.inc, ksamd64.inc +#define KF_MMX 0x00000100 +#define KF_DTS 0x00000200 // Win 5.2-6.2 +#define KF_PAT 0x00000400 +#define KF_FXSR 0x00000800 +#define KF_FAST_SYSCALL 0x00001000 // From ks386.inc, ksamd64.inc +#define KF_XMMI 0x00002000 // SSE +#define KF_3DNOW 0x00004000 +#define KF_AMDK6MTRR 0x00008000 // Win 5.0-6.1 +#define KF_XSAVEOPT 0x00008000 // From KF_XSAVEOPT_BIT +#define KF_XMMI64 0x00010000 // SSE2 +#define KF_BRANCH 0x00020000 // From ksamd64.inc, Win 6.1-6.2 +#define KF_00040000 0x00040000 // Unclear +#define KF_SSE3 0x00080000 // Win 6.0+ +#define KF_CMPXCHG16B 0x00100000 // Win 6.0-6.2 +#define KF_AUTHENTICAMD 0x00200000 // Win 6.1+ +#define KF_ACNT2 0x00400000 // Win 6.1+ +#define KF_XSTATE 0x00800000 // From ksamd64.inc, Win 6.1+ +#define KF_GENUINE_INTEL 0x01000000 // Win 6.1+ +#define KF_02000000 0x02000000 // Unclear +#define KF_SLAT 0x04000000 // Win 6.2+, Intel: EPT supported +#define KF_VIRT_FIRMWARE_ENABLED 0x08000000 // Win 6.2+ +#define KF_RDWRFSGSBASE 0x10000000 // From ksamd64.inc KF_RDWRFSGSBASE_BIT (0x1C) +#define KF_NX_BIT 0x20000000 +#define KF_NX_DISABLED 0x40000000 +#define KF_NX_ENABLED 0x80000000 +#define KF_RDRAND 0x0000000100000000ULL // Win 10.0+ +#define KF_SMAP 0x0000000200000000ULL // From ksamd64.inc +#define KF_RDTSCP 0x0000000400000000ULL // Win 10.0+ +#define KF_HUGEPAGE 0x0000002000000000ULL // Win 10.0 1607+ +#define KF_XSAVES 0x0000004000000000ULL // From ksamd64.inc KF_XSAVES_BIT (0x26) +#define KF_FPU_LEAKAGE 0x0000020000000000ULL // From ksamd64.inc KF_FPU_LEAKAGE_BIT (0x29) +#define KF_CAT 0x0000100000000000ULL // From ksamd64.inc KF_CAT_BIT (0x02C) +#define KF_CET_SS 0x0000400000000000ULL // From ksamd64.inc +#define KF_SSSE3 0x0000800000000000ULL +#define KF_SSE4_1 0x0001000000000000ULL +#define KF_SSE4_2 0x0002000000000000ULL + +#define KF_XSAVEOPT_BIT 15 // From ksamd64.inc (0x0F -> 0x8000) +#define KF_XSTATE_BIT 23 // From ksamd64.inc (0x17 -> 0x800000) +#define KF_RDWRFSGSBASE_BIT 28 // From ksamd64.inc (0x1C -> 0x10000000) +#define KF_XSAVES_BIT 38 // From ksamd64.inc (0x26 -> 0x4000000000) +#define KF_FPU_LEAKAGE_BIT 41 // From ksamd64.inc (0x29 -> 0x20000000000) +#define KF_CAT_BIT 44 // From ksamd64.inc (0x2C -> 0x100000000000) + // // KPCR Access for non-IA64 builds // diff --git a/sdk/include/ndk/i386/ketypes.h b/sdk/include/ndk/i386/ketypes.h index 8a9ea4c2ad5..6eb97d81ba0 100644 --- a/sdk/include/ndk/i386/ketypes.h +++ b/sdk/include/ndk/i386/ketypes.h @@ -23,6 +23,52 @@ Author: // Dependencies // +// +// Kernel Feature Bits +// See https://www.geoffchappell.com/studies/windows/km/ntoskrnl/structs/kprcb/fea… +// +#define KF_V86_VIS 0x00000001 // From ks386.inc +#define KF_RDTSC 0x00000002 // From ks386.inc, ksamd64.inc +#define KF_CR4 0x00000004 // From ks386.inc, ksamd64.inc +#define KF_CMOV 0x00000008 +#define KF_GLOBAL_PAGE 0x00000010 // From ks386.inc, ksamd64.inc +#define KF_LARGE_PAGE 0x00000020 // From ks386.inc, ksamd64.inc +#define KF_MTRR 0x00000040 +#define KF_CMPXCHG8B 0x00000080 // From ks386.inc, ksamd64.inc +#define KF_MMX 0x00000100 +#define KF_WORKING_PTE 0x00000200 +#define KF_PAT 0x00000400 +#define KF_FXSR 0x00000800 +#define KF_FAST_SYSCALL 0x00001000 // From ks386.inc, ksamd64.inc +#define KF_XMMI 0x00002000 // SSE +#define KF_3DNOW 0x00004000 +#define KF_AMDK6MTRR 0x00008000 // Win 5.0-6.1 +#define KF_XSAVEOPT 0x00008000 // From KF_XSAVEOPT_BIT +#define KF_XMMI64 0x00010000 // SSE2 +#define KF_DTS 0x00020000 +#define KF_CLFLUSH 0x00040000 // Win 6.0+ +#define KF_SSE3 0x00080000 // Win 6.0+ +#define KF_AUTHENTICAMD 0x00100000 // Win 6.1+ (family 5+) +#define KF_ACNT2 0x00200000 // Win 6.1+ +#define KF_XSTATE 0x00400000 // From ks386.inc, Win 6.1+ +#define KF_GENUINE_INTEL 0x00800000 // Win 6.1+ +#define KF_SMEP 0x01000000 // Win 6.2+ +#define KF_RDRAND 0x02000000 // Win 6.3+ +#define KF_SLAT 0x04000000 // Win 6.2+, Intel: EPT supported +#define KF_08000000 0x08000000 // Win 6.2+ +#define KF_NX_BIT 0x20000000 +#define KF_NX_DISABLED 0x40000000 +#define KF_NX_ENABLED 0x80000000 +#define KF_RDTSCP 0x0000000100000000ULL // Win 10.0+ +#define KF_CLFLUSHOPT 0x0000000200000000ULL // Win 10.0+ +#define KF_HDC 0x0000000400000000ULL // Win 10.0+ +#define KF_FPU_LEAKAGE 0x0000001000000000ULL // From ks386.inc KF_FPU_LEAKAGE_BIT +#define KF_SSSE3 0x0000004000000000ULL +#define KF_SSE4_1 0x0000008000000000ULL +#define KF_SSE4_2 0x0000010000000000ULL + +#define KF_FPU_LEAKAGE_BIT 36 // From ks386.inc (0x24 -> 0x1000000000) + // // KPCR Access for non-IA64 builds // diff --git a/sdk/include/ndk/ketypes.h b/sdk/include/ndk/ketypes.h index d54b9ffa131..37627fc39a4 100644 --- a/sdk/include/ndk/ketypes.h +++ b/sdk/include/ndk/ketypes.h @@ -137,39 +137,6 @@ Author: #define WAIT_QUANTUM_DECREMENT 1 #define CLOCK_QUANTUM_DECREMENT 3 -// -// Kernel Feature Bits -// -#define KF_V86_VIS 0x00000001 -#define KF_RDTSC 0x00000002 -#define KF_CR4 0x00000004 -#define KF_CMOV 0x00000008 -#define KF_GLOBAL_PAGE 0x00000010 -#define KF_LARGE_PAGE 0x00000020 -#define KF_MTRR 0x00000040 -#define KF_CMPXCHG8B 0x00000080 -#define KF_MMX 0x00000100 -#define KF_WORKING_PTE 0x00000200 -#define KF_PAT 0x00000400 -#define KF_FXSR 0x00000800 -#define KF_FAST_SYSCALL 0x00001000 -#define KF_XMMI 0x00002000 -#define KF_3DNOW 0x00004000 -#define KF_AMDK6MTRR 0x00008000 -#define KF_XMMI64 0x00010000 -#define KF_DTS 0x00020000 -#define KF_BRANCH 0x00020000 // from ksamd64.inc -#define KF_SSE3 0x00080000 -#define KF_CMPXCHG16B 0x00100000 -#define KF_XSTATE 0x00800000 // from ks386.inc, ksamd64.inc -#define KF_NX_BIT 0x20000000 -#define KF_NX_DISABLED 0x40000000 -#define KF_NX_ENABLED 0x80000000 - -#define KF_XSAVEOPT_BIT 15 -#define KF_XSTATE_BIT 23 -#define KF_RDWRFSGSBASE_BIT 28 - // // Internal Exception Codes //

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[reactos] 01/06: [XDK] Add missing PF_* processor feature definitions
by Timo Kreuzer 03 Oct '23

03 Oct '23

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=b66441d581023edd64a7e… commit b66441d581023edd64a7ee18db15d3eb74dd213a Author: Timo Kreuzer <timo.kreuzer(a)reactos.org> AuthorDate: Sat May 13 17:03:04 2023 +0300 Commit: Timo Kreuzer <timo.kreuzer(a)reactos.org> CommitDate: Tue Oct 3 19:45:44 2023 +0300 [XDK] Add missing PF_* processor feature definitions --- sdk/include/xdk/ketypes.h | 18 +++++++++++++++--- sdk/include/xdk/winnt_old.h | 34 ---------------------------------- 2 files changed, 15 insertions(+), 37 deletions(-) diff --git a/sdk/include/xdk/ketypes.h b/sdk/include/xdk/ketypes.h index fdeee0904a3..f5b3b02f8c9 100644 --- a/sdk/include/xdk/ketypes.h +++ b/sdk/include/xdk/ketypes.h @@ -120,9 +120,6 @@ typedef struct _SYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX { } DUMMYUNIONNAME; } SYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX, *PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX; -$endif(_WDMDDK_ || _WINNT_) -$if(_WDMDDK_) - /* Processor features */ #define PF_FLOATING_POINT_PRECISION_ERRATA 0 #define PF_FLOATING_POINT_EMULATED 1 @@ -156,6 +153,21 @@ $if(_WDMDDK_) #define PF_ARM_V8_INSTRUCTIONS_AVAILABLE 29 #define PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE 30 #define PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE 31 +#define PF_RDTSCP_INSTRUCTION_AVAILABLE 32 +#define PF_RDPID_INSTRUCTION_AVAILABLE 33 +#define PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE 34 +#define PF_SSSE3_INSTRUCTIONS_AVAILABLE 36 +#define PF_SSE4_1_INSTRUCTIONS_AVAILABLE 37 +#define PF_SSE4_2_INSTRUCTIONS_AVAILABLE 38 +#define PF_AVX_INSTRUCTIONS_AVAILABLE 39 +#define PF_AVX2_INSTRUCTIONS_AVAILABLE 40 +#define PF_AVX512F_INSTRUCTIONS_AVAILABLE 41 +#define PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE 43 +#define PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE 44 +#define PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE 45 + +$endif(_WDMDDK_ || _WINNT_) +$if(_WDMDDK_) #define MAXIMUM_WAIT_OBJECTS 64 diff --git a/sdk/include/xdk/winnt_old.h b/sdk/include/xdk/winnt_old.h index 15d353fc9ef..8edf6f58a59 100644 --- a/sdk/include/xdk/winnt_old.h +++ b/sdk/include/xdk/winnt_old.h @@ -457,40 +457,6 @@ #define PROCESSOR_ARCHITECTURE_AMD64 9 #define PROCESSOR_ARCHITECTURE_UNKNOWN 0xFFFF -/* Processor features */ -#define PF_FLOATING_POINT_PRECISION_ERRATA 0 -#define PF_FLOATING_POINT_EMULATED 1 -#define PF_COMPARE_EXCHANGE_DOUBLE 2 -#define PF_MMX_INSTRUCTIONS_AVAILABLE 3 -#define PF_PPC_MOVEMEM_64BIT_OK 4 -#define PF_ALPHA_BYTE_INSTRUCTIONS 5 -#define PF_XMMI_INSTRUCTIONS_AVAILABLE 6 -#define PF_3DNOW_INSTRUCTIONS_AVAILABLE 7 -#define PF_RDTSC_INSTRUCTION_AVAILABLE 8 -#define PF_PAE_ENABLED 9 -#define PF_XMMI64_INSTRUCTIONS_AVAILABLE 10 -#define PF_SSE_DAZ_MODE_AVAILABLE 11 -#define PF_NX_ENABLED 12 -#define PF_SSE3_INSTRUCTIONS_AVAILABLE 13 -#define PF_COMPARE_EXCHANGE128 14 -#define PF_COMPARE64_EXCHANGE128 15 -#define PF_CHANNELS_ENABLED 16 -#define PF_XSAVE_ENABLED 17 -#define PF_ARM_VFP_32_REGISTERS_AVAILABLE 18 -#define PF_ARM_NEON_INSTRUCTIONS_AVAILABLE 19 -#define PF_SECOND_LEVEL_ADDRESS_TRANSLATION 20 -#define PF_VIRT_FIRMWARE_ENABLED 21 -#define PF_RDWRFSGSBASE_AVAILABLE 22 -#define PF_FASTFAIL_AVAILABLE 23 -#define PF_ARM_DIVIDE_INSTRUCTION_AVAILABLE 24 -#define PF_ARM_64BIT_LOADSTORE_ATOMIC 25 -#define PF_ARM_EXTERNAL_CACHE_AVAILABLE 26 -#define PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE 27 -#define PF_RDRAND_INSTRUCTION_AVAILABLE 28 -#define PF_ARM_V8_INSTRUCTIONS_AVAILABLE 29 -#define PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE 30 -#define PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE 31 - /* also in ddk/ntifs.h */ #define FILE_ACTION_ADDED 0x00000001 #define FILE_ACTION_REMOVED 0x00000002

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[reactos] 01/01: [NTOS:CM] Use COMPUTE_HASH_CHAR to compute the conv hash key
by George Bișoc 03 Oct '23

03 Oct '23

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=50f367fa581d1d551f0f2… commit 50f367fa581d1d551f0f299fdc5850f2f3c8eb19 Author: George Bișoc <george.bisoc(a)reactos.org> AuthorDate: Tue Oct 3 11:01:21 2023 +0200 Commit: George Bișoc <george.bisoc(a)reactos.org> CommitDate: Tue Oct 3 11:01:21 2023 +0200 [NTOS:CM] Use COMPUTE_HASH_CHAR to compute the conv hash key We have a dedicated macro definition for that so just use it. --- ntoskrnl/config/cmkcbncb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ntoskrnl/config/cmkcbncb.c b/ntoskrnl/config/cmkcbncb.c index 9a69479c4b0..b7b7b0ef9cb 100644 --- a/ntoskrnl/config/cmkcbncb.c +++ b/ntoskrnl/config/cmkcbncb.c @@ -164,7 +164,7 @@ CmpGetNameControlBlock(IN PUNICODE_STRING NodeName) if (*p != OBJ_NAME_PATH_SEPARATOR) { /* Add it to the hash */ - ConvKey = 37 * ConvKey + RtlUpcaseUnicodeChar(*p); + ConvKey = COMPUTE_HASH_CHAR(ConvKey, *p); } /* Next character */ @@ -701,7 +701,7 @@ CmpCreateKeyControlBlock(IN PHHIVE Hive, if (*p != OBJ_NAME_PATH_SEPARATOR) { /* Add this key to the hash */ - ConvKey = 37 * ConvKey + RtlUpcaseUnicodeChar(*p); + ConvKey = COMPUTE_HASH_CHAR(ConvKey, *p); } /* Move on */

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[reactos] 01/01: GetDetailsOf does not support column flags (#5755)
by Whindmar Saksit 03 Oct '23

03 Oct '23

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=34066e475a12563d17c75… commit 34066e475a12563d17c75892c8c9d12754c8f8a1 Author: Whindmar Saksit <whindsaks(a)proton.me> AuthorDate: Tue Oct 3 10:43:44 2023 +0200 Commit: GitHub <noreply(a)github.com> CommitDate: Tue Oct 3 10:43:44 2023 +0200 GetDetailsOf does not support column flags (#5755) GetDetailsOf does not support the column flags used by CompareIDs. As a side effect, also fixes LPARAM to UINT truncation on 64-bit. --- dll/win32/shell32/shlfolder.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/dll/win32/shell32/shlfolder.cpp b/dll/win32/shell32/shlfolder.cpp index ee6c78b47fd..92dff6c81ef 100644 --- a/dll/win32/shell32/shlfolder.cpp +++ b/dll/win32/shell32/shlfolder.cpp @@ -241,8 +241,9 @@ HRESULT SHELL32_CompareDetails(IShellFolder2* isf, LPARAM lParam, LPCITEMIDLIST SHELLDETAILS sd; WCHAR wszItem1[MAX_PATH], wszItem2[MAX_PATH]; HRESULT hres; + UINT col = LOWORD(lParam); // Column index without SHCIDS_* flags - hres = isf->GetDetailsOf(pidl1, lParam, &sd); + hres = isf->GetDetailsOf(pidl1, col, &sd); if (FAILED(hres)) return MAKE_COMPARE_HRESULT(1); @@ -250,7 +251,7 @@ HRESULT SHELL32_CompareDetails(IShellFolder2* isf, LPARAM lParam, LPCITEMIDLIST if (FAILED(hres)) return MAKE_COMPARE_HRESULT(1); - hres = isf->GetDetailsOf(pidl2, lParam, &sd); + hres = isf->GetDetailsOf(pidl2, col, &sd); if (FAILED(hres)) return MAKE_COMPARE_HRESULT(1);

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[reactos] 01/01: [TASKMGR] de-DE.rc Update part 3
by Joachim Henze 03 Oct '23

03 Oct '23

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=6528ab8fcb41eb47ee17c… commit 6528ab8fcb41eb47ee17cf738760126e6758af94 Author: Joachim Henze <Joachim.Henze(a)reactos.org> AuthorDate: Tue Oct 3 06:31:04 2023 +0200 Commit: Joachim Henze <Joachim.Henze(a)reactos.org> CommitDate: Tue Oct 3 06:31:04 2023 +0200 [TASKMGR] de-DE.rc Update part 3 I spotted yet another flip: translation of IDS_TAB_PFDELTA and IDS_TAB_VMSIZE were flipped. I spotted that by toggling all columns off entirely in the View-Options dialog where the columns can be selected and then added only one column at a time. I did that for all options. I do recommend translators of other langs to do the same test, I was shocked about the amount of bugs I spotted for german. And it is very subtle / easy to miss, if you enable/disable multiple columns together! Let's call it a day now! --- base/applications/taskmgr/lang/de-DE.rc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/base/applications/taskmgr/lang/de-DE.rc b/base/applications/taskmgr/lang/de-DE.rc index ff22fb07bea..aea8376cf63 100644 --- a/base/applications/taskmgr/lang/de-DE.rc +++ b/base/applications/taskmgr/lang/de-DE.rc @@ -231,7 +231,7 @@ BEGIN PUSHBUTTON "CPU-Lastanzeige", IDC_CPU_USAGE_GRAPH, 12, 17, 47, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE PUSHBUTTON "Speicher-Lastanzeige", IDC_MEM_USAGE_GRAPH, 12, 75, 47, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE PUSHBUTTON "CPU-Lastverlaufsanzeige", IDC_CPU_USAGE_HISTORY_GRAPH, 81, 17, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE - PUSHBUTTON "Speicher-Lastanzeige", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE + PUSHBUTTON "Speicher-Lastverlaufsanzeige", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 @@ -289,7 +289,7 @@ BEGIN CONTROL "&CPU %", IDC_CPUUSAGE, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 7, 50, 80, 10 CONTROL "CP&U-Zeit", IDC_CPUTIME, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 7, 61, 48, 10 CONTROL "&Speicherlast", IDC_MEMORYUSAGE, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 7, 72, 90, 10 - CONTROL "Verän&derung der Speicherlast", IDC_MEMORYUSAGEDELTA, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 7, 83, 120, 10 + CONTROL "&Delta Speicherlast", IDC_MEMORYUSAGEDELTA, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 7, 83, 120, 10 CONTROL "&Maximale Speicherlast", IDC_PEAKMEMORYUSAGE, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 7, 94, 115, 10 CONTROL "S&eitenfehler", IDC_PAGEFAULTS, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 7, 105, 53, 10 CONTROL "BENUTZE&R-Objekte", IDC_USEROBJECTS, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 7, 116, 90, 10 @@ -297,8 +297,8 @@ BEGIN CONTROL "E/A-Bytes (Lesen)", IDC_IOREADBYTES, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 7, 138, 80, 10 CONTROL "S&itzungskennung", IDC_SESSIONID, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 7, 149, 70, 10 CONTROL "Benut&zername", IDC_USERNAME, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 7, 160, 70, 10 - CONTROL "Veränderung der Seiten&fehler", IDC_PAGEFAULTSDELTA, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 127, 28, 120, 10 - CONTROL "Größe des &virtuellen Speichers", IDC_VIRTUALMEMORYSIZE, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 127, 39, 120, 10 + CONTROL "Delta Seiten&fehler", IDC_PAGEFAULTSDELTA, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 127, 28, 120, 10 + CONTROL "&Virtueller Speicher", IDC_VIRTUALMEMORYSIZE, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 127, 39, 120, 10 CONTROL "&Ausgelagerter Pool", IDC_PAGEDPOOL, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 127, 50, 80, 10 CONTROL "Nicht ausgelagerter P&ool", IDC_NONPAGEDPOOL, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 127, 61, 115, 10 CONTROL "&Basispriorität", IDC_BASEPRIORITY, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 127, 72, 80, 10 @@ -390,10 +390,10 @@ BEGIN IDS_TAB_CPUTIME "CPU-Zeit" IDS_TAB_MEMUSAGE "Speicherlast" IDS_TAB_PEAKMEMUSAGE "Maximale Speicherlast" - IDS_TAB_MEMDELTA "Veränderung der Speicherlast" + IDS_TAB_MEMDELTA "Delta Speicherlast" IDS_TAB_PAGEFAULT "Seitenfehler" - IDS_TAB_PFDELTA "Maximale Seitenfehler" - IDS_TAB_VMSIZE "Virtuelle Arbeitsspeichergröße" + IDS_TAB_PFDELTA "Delta Seitenfehler" + IDS_TAB_VMSIZE "Virtueller Speicher" IDS_TAB_PAGEDPOOL "Ausgelagerter Pool" IDS_TAB_NPPOOL "Nichtausgelagerter Pool" IDS_TAB_BASEPRI "Basispriorität"

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[reactos] 01/01: [TASKMGR] *.rc Strip unused IDD_DEBUG_CHANNELS_DIALOG
by Joachim Henze 03 Oct '23

03 Oct '23

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=65ce20896afa190326128… commit 65ce20896afa19032612871506dd5d1e8eb73119 Author: Joachim Henze <Joachim.Henze(a)reactos.org> AuthorDate: Tue Oct 3 03:50:41 2023 +0200 Commit: Joachim Henze <Joachim.Henze(a)reactos.org> CommitDate: Tue Oct 3 03:50:41 2023 +0200 [TASKMGR] *.rc Strip unused IDD_DEBUG_CHANNELS_DIALOG This is an addendum to 0.4.15-dev-413-g ed7196d9645f66b49db434c509c2b7e18817dcca binary size shrinks slightly although that dlg was unused: taskmgr.exe RosBEWin2.2.2 GCC8.4.0dbg 715.264 -> 708.608 --- base/applications/taskmgr/lang/bg-BG.rc | 12 +----------- base/applications/taskmgr/lang/cs-CZ.rc | 10 ---------- base/applications/taskmgr/lang/da-DK.rc | 10 ---------- base/applications/taskmgr/lang/de-DE.rc | 10 ---------- base/applications/taskmgr/lang/el-GR.rc | 12 +----------- base/applications/taskmgr/lang/en-US.rc | 10 ---------- base/applications/taskmgr/lang/es-ES.rc | 12 +----------- base/applications/taskmgr/lang/et-EE.rc | 13 +------------ base/applications/taskmgr/lang/fr-FR.rc | 12 +----------- base/applications/taskmgr/lang/he-IL.rc | 12 +----------- base/applications/taskmgr/lang/hu-HU.rc | 12 +----------- base/applications/taskmgr/lang/id-ID.rc | 12 +----------- base/applications/taskmgr/lang/it-IT.rc | 10 ---------- base/applications/taskmgr/lang/ja-JP.rc | 10 ---------- base/applications/taskmgr/lang/ko-KR.rc | 12 +----------- base/applications/taskmgr/lang/nl-NL.rc | 10 ---------- base/applications/taskmgr/lang/no-NO.rc | 10 ---------- base/applications/taskmgr/lang/pl-PL.rc | 19 ++++--------------- base/applications/taskmgr/lang/pt-BR.rc | 10 ---------- base/applications/taskmgr/lang/pt-PT.rc | 10 ---------- base/applications/taskmgr/lang/ro-RO.rc | 15 ++------------- base/applications/taskmgr/lang/ru-RU.rc | 12 +----------- base/applications/taskmgr/lang/sk-SK.rc | 12 +----------- base/applications/taskmgr/lang/sq-AL.rc | 13 +------------ base/applications/taskmgr/lang/sv-SE.rc | 12 +----------- base/applications/taskmgr/lang/tr-TR.rc | 12 +----------- base/applications/taskmgr/lang/uk-UA.rc | 10 ---------- base/applications/taskmgr/lang/zh-CN.rc | 12 +----------- base/applications/taskmgr/lang/zh-HK.rc | 10 ---------- base/applications/taskmgr/lang/zh-TW.rc | 10 ---------- base/applications/taskmgr/resource.h | 2 -- 31 files changed, 21 insertions(+), 327 deletions(-) diff --git a/base/applications/taskmgr/lang/bg-BG.rc b/base/applications/taskmgr/lang/bg-BG.rc index 006a4abe5f7..7f523d3833c 100644 --- a/base/applications/taskmgr/lang/bg-BG.rc +++ b/base/applications/taskmgr/lang/bg-BG.rc @@ -232,16 +232,6 @@ BEGIN PUSHBUTTON "Дневник на паметта", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Обезбубяващи канали" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Затваряне", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Процесорно сродство" @@ -249,7 +239,7 @@ FONT 8, "MS Shell Dlg" BEGIN DEFPUSHBUTTON "Добре", IDOK, 120, 133, 50, 14 PUSHBUTTON "Отказ", IDCANCEL, 174, 133, 50, 14 - LTEXT "Настройката на сродството на процесора указва на кои ЦПУта е разрешено изпълнението да действието.", IDC_STATIC,5,5,220,16 + LTEXT "Настройката на сродството на процесора указва на кои ЦПУта е разрешено изпълнението да действието.", IDC_STATIC,5,5,220,16 CONTROL "ЦПУ 0", IDC_CPU0, "Button", BS_AUTOCHECKBOX | WS_TABSTOP, 11, 28, 37, 10 CONTROL "ЦПУ 1", IDC_CPU1, "Button", BS_AUTOCHECKBOX | WS_DISABLED | WS_TABSTOP, 11, 41, 37, 10 CONTROL "ЦПУ 2", IDC_CPU2, "Button", BS_AUTOCHECKBOX | WS_DISABLED | WS_TABSTOP, 11, 54, 37, 10 diff --git a/base/applications/taskmgr/lang/cs-CZ.rc b/base/applications/taskmgr/lang/cs-CZ.rc index e8e1675cc5c..423155a957b 100644 --- a/base/applications/taskmgr/lang/cs-CZ.rc +++ b/base/applications/taskmgr/lang/cs-CZ.rc @@ -232,16 +232,6 @@ BEGIN PUSHBUTTON "Historie využití paměti", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Kanály ladění" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Zavřít", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Afinita procesoru" diff --git a/base/applications/taskmgr/lang/da-DK.rc b/base/applications/taskmgr/lang/da-DK.rc index 79c0f4b580d..27ea5d0f36c 100644 --- a/base/applications/taskmgr/lang/da-DK.rc +++ b/base/applications/taskmgr/lang/da-DK.rc @@ -232,16 +232,6 @@ BEGIN PUSHBUTTON "Hukommelses Forbrug Historik", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Debug Kanaler" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Luk", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Processor Affinitet" diff --git a/base/applications/taskmgr/lang/de-DE.rc b/base/applications/taskmgr/lang/de-DE.rc index 943d9ef97ab..ff22fb07bea 100644 --- a/base/applications/taskmgr/lang/de-DE.rc +++ b/base/applications/taskmgr/lang/de-DE.rc @@ -234,16 +234,6 @@ BEGIN PUSHBUTTON "Speicher-Lastanzeige", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Debug-Kanäle" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Schließen", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Prozessorzugehörigkeit" diff --git a/base/applications/taskmgr/lang/el-GR.rc b/base/applications/taskmgr/lang/el-GR.rc index 58bfa1ebe2c..616f0de9115 100644 --- a/base/applications/taskmgr/lang/el-GR.rc +++ b/base/applications/taskmgr/lang/el-GR.rc @@ -1,4 +1,4 @@ -/* Greek (GR) resources by Dj Apal */ +/* TRANSLATOR: Dj Apal */ LANGUAGE LANG_GREEK, SUBLANG_DEFAULT @@ -234,16 +234,6 @@ BEGIN PUSHBUTTON "MEM Usage History", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Debug Channels" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Close", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Processor Affinity" diff --git a/base/applications/taskmgr/lang/en-US.rc b/base/applications/taskmgr/lang/en-US.rc index ec555f9c1f5..90b73950e6a 100644 --- a/base/applications/taskmgr/lang/en-US.rc +++ b/base/applications/taskmgr/lang/en-US.rc @@ -230,16 +230,6 @@ BEGIN PUSHBUTTON "MEM Usage History", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Debug Channels" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Close", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Processor Affinity" diff --git a/base/applications/taskmgr/lang/es-ES.rc b/base/applications/taskmgr/lang/es-ES.rc index 5c1c4e8cac0..9a99ddebc89 100644 --- a/base/applications/taskmgr/lang/es-ES.rc +++ b/base/applications/taskmgr/lang/es-ES.rc @@ -1,4 +1,4 @@ -/* Spanish (Spain) resources by Carlos Garcia Gomez, Samuel Serapión and Ismael Ferreras Morezuelas (Swyter) */ +/* TRANSLATORS: Carlos Garcia Gomez, Samuel Serapión, Ismael Ferreras Morezuelas (Swyter) */ LANGUAGE LANG_SPANISH, SUBLANG_NEUTRAL @@ -234,16 +234,6 @@ BEGIN PUSHBUTTON "Historial de uso de memoria", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Canales de depuración" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Cerrar", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Afinidad del procesador" diff --git a/base/applications/taskmgr/lang/et-EE.rc b/base/applications/taskmgr/lang/et-EE.rc index 7d015c9a13d..4aba1b254f9 100644 --- a/base/applications/taskmgr/lang/et-EE.rc +++ b/base/applications/taskmgr/lang/et-EE.rc @@ -1,9 +1,8 @@ /* * PROJECT: Task Manager for ReactOS * LICENSE: GPL-2.0+ (https://spdx.org/licenses/GPL-2.0+) - * FILE: base/applications/taskmgr/lang/et-EE.rc * PURPOSE: Estonian Language resource file - * TRANSLATOR: Joann Mõndresku (joannmondresku at gmail dot com) + * TRANSLATOR: Joann Mõndresku <joannmondresku(a)gmail.com> */ LANGUAGE LANG_ESTONIAN, SUBLANG_DEFAULT @@ -237,16 +236,6 @@ BEGIN PUSHBUTTON "Füüsilise mälu hõivatuse ajalugu", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Silumiskanalid" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Sule", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Protessori ühtivus" diff --git a/base/applications/taskmgr/lang/fr-FR.rc b/base/applications/taskmgr/lang/fr-FR.rc index d9bc6444733..204caaef666 100644 --- a/base/applications/taskmgr/lang/fr-FR.rc +++ b/base/applications/taskmgr/lang/fr-FR.rc @@ -1,4 +1,4 @@ -/* French (Fr) resources by Benoit Plante (aka cmoibenlepro) */ +/* TRANSLATOR: Benoit Plante (aka cmoibenlepro) */ LANGUAGE LANG_FRENCH, SUBLANG_NEUTRAL @@ -234,16 +234,6 @@ BEGIN PUSHBUTTON "Historique d'utilisation du fichier d'échange", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Cannaux de débogage" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Fermer", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Affinité du processeur" diff --git a/base/applications/taskmgr/lang/he-IL.rc b/base/applications/taskmgr/lang/he-IL.rc index c24c276a914..c9855c5ff30 100644 --- a/base/applications/taskmgr/lang/he-IL.rc +++ b/base/applications/taskmgr/lang/he-IL.rc @@ -1,4 +1,4 @@ -/* Hebrew translations by Baruch Rutman (peterooch) and Shy Zedaka */ +/* TRANSLATORS: Baruch Rutman (peterooch), Shy Zedaka */ LANGUAGE LANG_HEBREW, SUBLANG_DEFAULT @@ -234,16 +234,6 @@ BEGIN PUSHBUTTON "היסטורית שימוש בזיכרון", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Debug Channels" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "סגירה", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "קירבה בין מעבדים" diff --git a/base/applications/taskmgr/lang/hu-HU.rc b/base/applications/taskmgr/lang/hu-HU.rc index f4968d5432a..51fa95242a6 100644 --- a/base/applications/taskmgr/lang/hu-HU.rc +++ b/base/applications/taskmgr/lang/hu-HU.rc @@ -1,4 +1,4 @@ -/* Hungaruan (HU) translation by Robert Horvath - talley at cubeclub.hu */ +/* TRANSLATOR: Robert Horvath <talley(a)cubeclub.hu> */ LANGUAGE LANG_HUNGARIAN, SUBLANG_DEFAULT @@ -234,16 +234,6 @@ BEGIN PUSHBUTTON "Memória használata", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Hibakereső csatornák" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Bezárás", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Processzoraffinitás" diff --git a/base/applications/taskmgr/lang/id-ID.rc b/base/applications/taskmgr/lang/id-ID.rc index 8a4bbb32bf0..28427216fa3 100644 --- a/base/applications/taskmgr/lang/id-ID.rc +++ b/base/applications/taskmgr/lang/id-ID.rc @@ -1,4 +1,4 @@ -/* Indonesian resource file by Zaenal Mutaqin (ade999(a)gmail.com) and Mas Ahmad Muhammad (m.charly81(a)gmail.com) */ +/* TRANSLATORS: Zaenal Mutaqin <ade999(a)gmail.com> and Mas Ahmad Muhammad <m.charly81(a)gmail.com> */ LANGUAGE LANG_INDONESIAN, SUBLANG_DEFAULT @@ -234,16 +234,6 @@ BEGIN PUSHBUTTON "Riwayat Pemakaian MEM", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Saluran Debug" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Tutup", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Afinitas Prosesor" diff --git a/base/applications/taskmgr/lang/it-IT.rc b/base/applications/taskmgr/lang/it-IT.rc index 180b60e1d31..ff44c4e27a8 100644 --- a/base/applications/taskmgr/lang/it-IT.rc +++ b/base/applications/taskmgr/lang/it-IT.rc @@ -232,16 +232,6 @@ BEGIN PUSHBUTTON "Storico uso MEM", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Debug Channels" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Chiudi", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Processor Affinity" diff --git a/base/applications/taskmgr/lang/ja-JP.rc b/base/applications/taskmgr/lang/ja-JP.rc index c75672e3640..bec1d437eaf 100644 --- a/base/applications/taskmgr/lang/ja-JP.rc +++ b/base/applications/taskmgr/lang/ja-JP.rc @@ -232,16 +232,6 @@ BEGIN PUSHBUTTON "メモリ使用量の履歴", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "デバッグチャンネル" -FONT 9, "MS UI Gothic" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "閉じる", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "プロセッサの関係" diff --git a/base/applications/taskmgr/lang/ko-KR.rc b/base/applications/taskmgr/lang/ko-KR.rc index ab574ed209a..1dc9dcb30b3 100644 --- a/base/applications/taskmgr/lang/ko-KR.rc +++ b/base/applications/taskmgr/lang/ko-KR.rc @@ -1,4 +1,4 @@ -/* Korean translation by Seungju Kim */ +/* TRANSLATOR: Seungju Kim */ LANGUAGE LANG_KOREAN, SUBLANG_DEFAULT @@ -234,16 +234,6 @@ BEGIN PUSHBUTTON "메모리 사용 기록", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "디버그 채널" -FONT 9, "굴림" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "닫기", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "프로세서 선호도" diff --git a/base/applications/taskmgr/lang/nl-NL.rc b/base/applications/taskmgr/lang/nl-NL.rc index 431849b61e2..64f70a7d0df 100644 --- a/base/applications/taskmgr/lang/nl-NL.rc +++ b/base/applications/taskmgr/lang/nl-NL.rc @@ -232,16 +232,6 @@ BEGIN PUSHBUTTON "Geschiedenis van wisselbestandsgebruik", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Debug kanalen" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Sluit", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Processoraffiniteit" diff --git a/base/applications/taskmgr/lang/no-NO.rc b/base/applications/taskmgr/lang/no-NO.rc index b23dab747c6..86063df9bbf 100644 --- a/base/applications/taskmgr/lang/no-NO.rc +++ b/base/applications/taskmgr/lang/no-NO.rc @@ -232,16 +232,6 @@ BEGIN PUSHBUTTON "Minne bruk historie", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Debug kanaler" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Avslutt", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Prosessor slektskap" diff --git a/base/applications/taskmgr/lang/pl-PL.rc b/base/applications/taskmgr/lang/pl-PL.rc index f48b4408670..160755b4e75 100644 --- a/base/applications/taskmgr/lang/pl-PL.rc +++ b/base/applications/taskmgr/lang/pl-PL.rc @@ -1,9 +1,8 @@ /* - * Translated by xrogers - * xxrogers(a)users.sourceforge.net - * https://sourceforge.net/projects/reactospl - * UTF-8 conversion by Caemyr (May, 2011) - * Updated by Saibamen - Adam Stachowicz (saibamenppl(a)gmail.com) (August, 2014) + * TRANSLATOR: xrogers <xxrogers(a)users.sourceforge.net> + * https://sourceforge.net/projects/reactospl + * UTF-8 conversion by Caemyr (May, 2011) + * Updated by Saibamen - Adam Stachowicz <saibamenppl(a)gmail.com> (August, 2014) */ LANGUAGE LANG_POLISH, SUBLANG_DEFAULT @@ -240,16 +239,6 @@ BEGIN PUSHBUTTON "Historia zużycia pamięci", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Kanały debugowania" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Zamknij", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Koligacje procesora" diff --git a/base/applications/taskmgr/lang/pt-BR.rc b/base/applications/taskmgr/lang/pt-BR.rc index 433aa6e7571..f2581fe758d 100644 --- a/base/applications/taskmgr/lang/pt-BR.rc +++ b/base/applications/taskmgr/lang/pt-BR.rc @@ -232,16 +232,6 @@ BEGIN PUSHBUTTON "MEM Usage History", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Canais de depuração" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Fechar", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Afinidade com processador" diff --git a/base/applications/taskmgr/lang/pt-PT.rc b/base/applications/taskmgr/lang/pt-PT.rc index a5b681d2258..1d6568e2d6d 100644 --- a/base/applications/taskmgr/lang/pt-PT.rc +++ b/base/applications/taskmgr/lang/pt-PT.rc @@ -234,16 +234,6 @@ BEGIN PUSHBUTTON "Histórico de uso da memória RAM", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Canais de depuração" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Fechar", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Afinidade com processador" diff --git a/base/applications/taskmgr/lang/ro-RO.rc b/base/applications/taskmgr/lang/ro-RO.rc index c8167b73f86..1b0d7df8a74 100644 --- a/base/applications/taskmgr/lang/ro-RO.rc +++ b/base/applications/taskmgr/lang/ro-RO.rc @@ -1,9 +1,8 @@ /* - * Translators: Petru Dimitriu (petrimetri at gmail dot com) - * Ștefan Fulea (stefan dot fulea at mail dot com) + * TRANSLATORS: Petru Dimitriu <petrimetri(a)gmail.com> + * Ștefan Fulea <stefan.fulea(a)mail.com> */ - LANGUAGE LANG_ROMANIAN, SUBLANG_NEUTRAL IDR_TASKMANAGER MENU @@ -238,16 +237,6 @@ BEGIN PUSHBUTTON "Afișaj istoric încărcătură memorie", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Canale de depanare" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Î&nchide", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Afinitate procesor" diff --git a/base/applications/taskmgr/lang/ru-RU.rc b/base/applications/taskmgr/lang/ru-RU.rc index 4bf7b69756c..da28e3bc231 100644 --- a/base/applications/taskmgr/lang/ru-RU.rc +++ b/base/applications/taskmgr/lang/ru-RU.rc @@ -1,4 +1,4 @@ -/* Russian language resource file by Dmitry Chapyshev, 2007-06-10, Kudratov Olimjon (olim98(a)bk.ru) */ +/* TRANSLATORS: Dmitry Chapyshev, 2007-06-10, Kudratov Olimjon <olim98(a)bk.ru> */ LANGUAGE LANG_RUSSIAN, SUBLANG_DEFAULT @@ -234,16 +234,6 @@ BEGIN PUSHBUTTON "Хронология использования памяти", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Отладка потоков" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Закрыть", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Семейство процессоров" diff --git a/base/applications/taskmgr/lang/sk-SK.rc b/base/applications/taskmgr/lang/sk-SK.rc index 004f87b2f00..45567224455 100644 --- a/base/applications/taskmgr/lang/sk-SK.rc +++ b/base/applications/taskmgr/lang/sk-SK.rc @@ -1,4 +1,4 @@ -/* Slovak translation by Kario (kario(a)szm.sk) (09-08-2007) */ +/* TRANSLATOR: 2007 Kario <kario(a)szm.sk> */ LANGUAGE LANG_SLOVAK, SUBLANG_DEFAULT @@ -234,16 +234,6 @@ BEGIN PUSHBUTTON "História využitia pamäte", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Kanály ladenia" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Zavrieť", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 270, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Afinita procesorov" diff --git a/base/applications/taskmgr/lang/sq-AL.rc b/base/applications/taskmgr/lang/sq-AL.rc index 58fa12df27a..06c4254a6e2 100644 --- a/base/applications/taskmgr/lang/sq-AL.rc +++ b/base/applications/taskmgr/lang/sq-AL.rc @@ -1,5 +1,4 @@ -/* TRANSLATOR : Ardit Dani (Ard1t) (ardit.dani(a)gmail.com) - * DATE OF TR: 29-11-2013 +/* TRANSLATOR: 2013 Ardit Dani (Ard1t) <ardit.dani(a)gmail.com> */ LANGUAGE LANG_ALBANIAN, SUBLANG_NEUTRAL @@ -234,16 +233,6 @@ BEGIN PUSHBUTTON "Historia e perdorimit MEM", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Debug Channels" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Mbyll", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Processor Affinity" diff --git a/base/applications/taskmgr/lang/sv-SE.rc b/base/applications/taskmgr/lang/sv-SE.rc index fbf39896943..5186e05c3ff 100644 --- a/base/applications/taskmgr/lang/sv-SE.rc +++ b/base/applications/taskmgr/lang/sv-SE.rc @@ -1,4 +1,4 @@ -/* Swedish translation by David Nordenberg */ +/* TRANSLATOR: David Nordenberg */ LANGUAGE LANG_SWEDISH, SUBLANG_NEUTRAL @@ -234,16 +234,6 @@ BEGIN PUSHBUTTON "Minneshistorik", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Felsökningskanaler" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Stäng", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Processorsamhörighet" diff --git a/base/applications/taskmgr/lang/tr-TR.rc b/base/applications/taskmgr/lang/tr-TR.rc index a20a43e7efb..27a1272cd9e 100644 --- a/base/applications/taskmgr/lang/tr-TR.rc +++ b/base/applications/taskmgr/lang/tr-TR.rc @@ -1,4 +1,4 @@ -/* TRANSLATOR: 2013-2014, 2016, 2019 Erdem Ersoy (eersoy93) (erdemersoy [at] erdemersoy [dot] net) */ +/* TRANSLATOR: 2013-2019 Erdem Ersoy (eersoy93) <erdemersoy(a)erdemersoy.net> */ LANGUAGE LANG_TURKISH, SUBLANG_DEFAULT @@ -232,16 +232,6 @@ BEGIN PUSHBUTTON "Bellek Kullanım Geçmişi Grafiği", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Hata Ayıklama Kanalları" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Kapat", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "İşlemci İlişkisi" diff --git a/base/applications/taskmgr/lang/uk-UA.rc b/base/applications/taskmgr/lang/uk-UA.rc index dc6fe43e4b8..b7d630af65b 100644 --- a/base/applications/taskmgr/lang/uk-UA.rc +++ b/base/applications/taskmgr/lang/uk-UA.rc @@ -232,16 +232,6 @@ BEGIN PUSHBUTTON "Хронологія використання пам'яті", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "Налагодження каналів" -FONT 8, "MS Shell Dlg" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "Закрити", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "Відповідність процесорів" diff --git a/base/applications/taskmgr/lang/zh-CN.rc b/base/applications/taskmgr/lang/zh-CN.rc index 09c514557fe..5afc17c975f 100644 --- a/base/applications/taskmgr/lang/zh-CN.rc +++ b/base/applications/taskmgr/lang/zh-CN.rc @@ -2,7 +2,7 @@ * (Simplified Chinese resources) * (简体中文资源) * by zhangbing 2008 <e_zb(a)21cn.com, ezb(a)mail.gywb.cn> - * Improved by Wexpo Lyu <laosb at lasteam.net> + * Improved by Wexpo Lyu <laosb(a)lasteam.net> */ LANGUAGE LANG_CHINESE, SUBLANG_CHINESE_SIMPLIFIED @@ -239,16 +239,6 @@ BEGIN PUSHBUTTON "内存使用记录", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "调试频道" -FONT 9, "宋体" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "关闭", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "处理器关联" diff --git a/base/applications/taskmgr/lang/zh-HK.rc b/base/applications/taskmgr/lang/zh-HK.rc index dfb0ab3794e..d6abcc2aea5 100644 --- a/base/applications/taskmgr/lang/zh-HK.rc +++ b/base/applications/taskmgr/lang/zh-HK.rc @@ -240,16 +240,6 @@ BEGIN PUSHBUTTON "記憶體使用記錄", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "偵錯頻道" -FONT 9, "新細明體" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "關閉", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "處理器親和性" diff --git a/base/applications/taskmgr/lang/zh-TW.rc b/base/applications/taskmgr/lang/zh-TW.rc index 7e872c268a3..c83bfea34ee 100644 --- a/base/applications/taskmgr/lang/zh-TW.rc +++ b/base/applications/taskmgr/lang/zh-TW.rc @@ -240,16 +240,6 @@ BEGIN PUSHBUTTON "記憶體使用記錄", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END -IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210 -STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU -CAPTION "除錯頻道" -FONT 9, "新細明體" -BEGIN - CONTROL "List1", IDC_DEBUG_CHANNELS_LIST, "SysListView32", LVS_REPORT | LVS_SINGLESEL | - LVS_SHOWSELALWAYS | WS_BORDER | WS_TABSTOP | LVS_SORTASCENDING, 7, 7, 233, 177 - PUSHBUTTON "關閉", IDOK, 171, 189, 69, 14 -END - IDD_AFFINITY_DIALOG DIALOGEX 0, 0, 231, 154 STYLE DS_SHELLFONT | DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU CAPTION "處理器親和性" diff --git a/base/applications/taskmgr/resource.h b/base/applications/taskmgr/resource.h index bda48393a30..ebfc0ebbbaf 100644 --- a/base/applications/taskmgr/resource.h +++ b/base/applications/taskmgr/resource.h @@ -32,8 +32,6 @@ #define IDR_PROCESS_PAGE_CONTEXT 144 #define IDB_TRAYMASK 150 #define IDB_TRAYICON 153 -#define IDD_DEBUG_CHANNELS_DIALOG 155 -#define IDC_DEBUG_CHANNELS_LIST 156 #define IDC_ENDTASK 1012 #define IDC_SWITCHTO 1013

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[reactos] 01/01: [TASKMGR] de-DE.rc Update
by Joachim Henze 03 Oct '23

03 Oct '23

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=142c35fcce133ab6cbcc4… commit 142c35fcce133ab6cbcc4454d4d3ba61e434c917 Author: Joachim Henze <Joachim.Henze(a)reactos.org> AuthorDate: Tue Oct 3 02:47:10 2023 +0200 Commit: Joachim Henze <Joachim.Henze(a)reactos.org> CommitDate: Tue Oct 3 02:47:10 2023 +0200 [TASKMGR] de-DE.rc Update GRAPH == 'Anzeige'. Addendum to last commit --- base/applications/taskmgr/lang/de-DE.rc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/base/applications/taskmgr/lang/de-DE.rc b/base/applications/taskmgr/lang/de-DE.rc index 3b5e687ffd8..943d9ef97ab 100644 --- a/base/applications/taskmgr/lang/de-DE.rc +++ b/base/applications/taskmgr/lang/de-DE.rc @@ -231,7 +231,7 @@ BEGIN PUSHBUTTON "CPU-Lastanzeige", IDC_CPU_USAGE_GRAPH, 12, 17, 47, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE PUSHBUTTON "Speicher-Lastanzeige", IDC_MEM_USAGE_GRAPH, 12, 75, 47, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE PUSHBUTTON "CPU-Lastverlaufsanzeige", IDC_CPU_USAGE_HISTORY_GRAPH, 81, 17, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE - PUSHBUTTON "Speicher-Lastverlauf", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE + PUSHBUTTON "Speicher-Lastanzeige", IDC_MEM_USAGE_HISTORY_GRAPH, 81, 75, 153, 37, NOT WS_TABSTOP, WS_EX_CLIENTEDGE END IDD_DEBUG_CHANNELS_DIALOG DIALOGEX 0, 0, 247, 210

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