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[sir_richard] 45513: [NTOS]: Make system startup match x86 code as closely as possible, instead of mixing MIPS/PPC code. Only rip out parts that are obviously x86-specific. Also fix code to use new KPCR definitions. [NTOS]: Implement a DbgPrintEarly function that directly uses KDCOM to print to the serial console, instead of going through the Debug Service Interrupt.
by sir_richard＠svn.reactos.org 09 Feb '10

09 Feb '10

Author: sir_richard Date: Tue Feb 9 03:11:18 2010 New Revision: 45513 URL: http://svn.reactos.org/svn/reactos?rev=45513&view=rev Log: [NTOS]: Make system startup match x86 code as closely as possible, instead of mixing MIPS/PPC code. Only rip out parts that are obviously x86-specific. Also fix code to use new KPCR definitions. [NTOS]: Implement a DbgPrintEarly function that directly uses KDCOM to print to the serial console, instead of going through the Debug Service Interrupt. Modified: trunk/reactos/ntoskrnl/ke/arm/kiinit.c Modified: trunk/reactos/ntoskrnl/ke/arm/kiinit.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ke/arm/kiinit.c?r… ============================================================================== --- trunk/reactos/ntoskrnl/ke/arm/kiinit.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/ke/arm/kiinit.c [iso-8859-1] Tue Feb 9 03:11:18 2010 @@ -28,9 +28,7 @@ NTAPI KiInitMachineDependent(VOID) { - // - // There is nothing to do on ARM - // + /* There is nothing to do on ARM */ return; } @@ -43,169 +41,55 @@ IN CCHAR Number, IN PLOADER_PARAMETER_BLOCK LoaderBlock) { + PKIPCR Pcr = (PKIPCR)KeGetPcr(); ULONG PageDirectory[2]; - PKPCR Pcr; ULONG i; - - // - // Initialize the platform - // - HalInitializeProcessor(Number, LoaderBlock); - - // - // Save loader block - // - KeLoaderBlock = LoaderBlock; - - // - // Setup KPRCB - // - Prcb->MajorVersion = 1; - Prcb->MinorVersion = 1; - Prcb->BuildType = 0; -#ifndef CONFIG_SMP - Prcb->BuildType |= PRCB_BUILD_UNIPROCESSOR; -#endif -#if DBG - Prcb->BuildType |= PRCB_BUILD_DEBUG; -#endif - Prcb->CurrentThread = InitThread; - Prcb->NextThread = NULL; - Prcb->IdleThread = InitThread; - Prcb->Number = Number; - Prcb->SetMember = 1 << Number; - Prcb->PcrPage = LoaderBlock->u.Arm.PcrPage; - - // - // Initialize spinlocks and DPC data - // + + /* Set the default NX policy (opt-in) */ + SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_OPTIN; + + /* Initialize spinlocks and DPC data */ KiInitSpinLocks(Prcb, Number); - - // - // Set the PRCB in the processor block - // - KiProcessorBlock[(ULONG)Number] = Prcb; - Pcr = (PKPCR)KeGetPcr(); - - // - // Set processor information - // - KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_ARM; - KeFeatureBits = 0; - KeProcessorLevel = (USHORT)(Pcr->ProcessorId >> 8); - KeProcessorRevision = (USHORT)(Pcr->ProcessorId & 0xFF); - - // - // Set stack pointers - // + + /* Set stack pointers */ Pcr->InitialStack = IdleStack; - Pcr->StackLimit = (PVOID)((ULONG_PTR)IdleStack - KERNEL_STACK_SIZE); - - // - // Check if this is the Boot CPU - // + + /* Check if this is the Boot CPU */ if (!Number) { - // - // Setup the unexpected interrupt - // + /* Setup the unexpected interrupt */ KxUnexpectedInterrupt.DispatchAddress = KiUnexpectedInterrupt; for (i = 0; i < 4; i++) { - // - // Copy the template code - // + /* Copy the template code */ KxUnexpectedInterrupt.DispatchCode[i] = ((PULONG)KiInterruptTemplate)[i]; } - // - // Set DMA coherency - // + /* Set DMA coherency */ KiDmaIoCoherency = 0; - // - // Sweep D-Cache - // + /* Sweep D-Cache */ HalSweepDcache(); - } - - // - // Set all interrupt routines to unexpected interrupts as well - // - for (i = 0; i < MAXIMUM_VECTOR; i++) - { - // - // Point to the same template - // - Pcr->InterruptRoutine[i] = (PVOID)&KxUnexpectedInterrupt.DispatchCode; - } - - // - // Setup profiling - // - Pcr->ProfileCount = 0; - Pcr->ProfileInterval = 0x200000; - Pcr->StallScaleFactor = 50; - - // - // Setup software interrupts - // - Pcr->InterruptRoutine[PASSIVE_LEVEL] = KiPassiveRelease; - Pcr->InterruptRoutine[APC_LEVEL] = KiApcInterrupt; - Pcr->InterruptRoutine[DISPATCH_LEVEL] = KiDispatchInterrupt; - Pcr->ReservedVectors = (1 << PASSIVE_LEVEL) | - (1 << APC_LEVEL) | - (1 << DISPATCH_LEVEL) | - (1 << IPI_LEVEL); - - // - // Set IRQL and prcessor member/number - // - Pcr->CurrentIrql = APC_LEVEL; - Pcr->SetMember = 1 << Number; - Pcr->NotMember = -Pcr->SetMember; - Pcr->Number = Number; - - // - // Remember our parent - // - InitThread->ApcState.Process = InitProcess; - - // - // Setup the active processor numbers - // - KeActiveProcessors |= 1 << Number; - KeNumberProcessors = Number + 1; - - // - // Check if this is the boot CPU - // - if (!Number) - { - // - // Setup KD - // - KdInitSystem(0, LoaderBlock); - - // - // Check for break-in - // - if (KdPollBreakIn()) DbgBreakPointWithStatus(DBG_STATUS_CONTROL_C); - - // - // Cleanup the rest of the processor block array - // - for (i = 1; i < MAXIMUM_PROCESSORS; i++) KiProcessorBlock[i] = NULL; - - // - // Initialize portable parts of the OS - // + + /* Set boot-level flags */ + KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_ARM; + KeFeatureBits = 0; + KeProcessorLevel = (USHORT)(Pcr->ProcessorId >> 8); + KeProcessorRevision = (USHORT)(Pcr->ProcessorId & 0xFF); + + /* Set the current MP Master KPRCB to the Boot PRCB */ + Prcb->MultiThreadSetMaster = Prcb; + + /* Lower to APC_LEVEL */ + KeLowerIrql(APC_LEVEL); + + /* Initialize portable parts of the OS */ KiInitSystem(); - // - // Initialize the Idle Process and the Process Listhead - // + /* Initialize the Idle Process and the Process Listhead */ InitializeListHead(&KiProcessListHead); + PageDirectory[0] = 0; + PageDirectory[1] = 0; KeInitializeProcess(InitProcess, 0, 0xFFFFFFFF, @@ -215,15 +99,11 @@ } else { - // - // FIXME-V6: See if we want to support MP - // + /* FIXME-V6: See if we want to support MP */ DPRINT1("ARM MPCore not supported\n"); } - - // - // Setup the Idle Thread - // + + /* Setup the Idle Thread */ KeInitializeThread(InitProcess, InitThread, NULL, @@ -239,253 +119,310 @@ InitThread->WaitIrql = DISPATCH_LEVEL; InitProcess->ActiveProcessors = 1 << Number; - // - // HACK for MmUpdatePageDir - // + /* HACK for MmUpdatePageDir */ ((PETHREAD)InitThread)->ThreadsProcess = (PEPROCESS)InitProcess; - // - // Initialize the Kernel Executive - // + /* Set up the thread-related fields in the PRCB */ + Prcb->CurrentThread = InitThread; + Prcb->NextThread = NULL; + Prcb->IdleThread = InitThread; + + /* Initialize the Kernel Executive */ ExpInitializeExecutive(Number, LoaderBlock); - - // - // Only do this on the boot CPU - // + + /* Only do this on the boot CPU */ if (!Number) { - // - // Calculate the time reciprocal - // + /* Calculate the time reciprocal */ KiTimeIncrementReciprocal = - KiComputeReciprocal(KeMaximumIncrement, - &KiTimeIncrementShiftCount); - - // - // Update DPC Values in case they got updated by the executive - // + KiComputeReciprocal(KeMaximumIncrement, + &KiTimeIncrementShiftCount); + + /* Update DPC Values in case they got updated by the executive */ Prcb->MaximumDpcQueueDepth = KiMaximumDpcQueueDepth; Prcb->MinimumDpcRate = KiMinimumDpcRate; Prcb->AdjustDpcThreshold = KiAdjustDpcThreshold; } - - // - // Raise to Dispatch - // + + /* Raise to Dispatch */ KfRaiseIrql(DISPATCH_LEVEL); - - // - // Set the Idle Priority to 0. This will jump into Phase 1 - // + + /* Set the Idle Priority to 0. This will jump into Phase 1 */ KeSetPriorityThread(InitThread, 0); - - // - // If there's no thread scheduled, put this CPU in the Idle summary - // + + /* If there's no thread scheduled, put this CPU in the Idle summary */ KiAcquirePrcbLock(Prcb); if (!Prcb->NextThread) KiIdleSummary |= 1 << Number; KiReleasePrcbLock(Prcb); - - // - // Raise back to HIGH_LEVEL - // + + /* Raise back to HIGH_LEVEL and clear the PRCB for the loader block */ KfRaiseIrql(HIGH_LEVEL); -} + LoaderBlock->Prcb = 0; +} + +C_ASSERT((PKIPCR)KeGetPcr() == (PKIPCR)0xFFDFF000); +C_ASSERT((FIELD_OFFSET(KIPCR, FirstLevelDcacheSize) & 4) == 0); +C_ASSERT(sizeof(KIPCR) <= PAGE_SIZE); VOID -KiInitializeSystem(IN ULONG Magic, - IN PLOADER_PARAMETER_BLOCK LoaderBlock) -{ - ARM_PTE Pte; - PKPCR Pcr; - ARM_CONTROL_REGISTER ControlRegister; - - // - // Detect ARM version (Architecture 6 is the ARMv5TE-J, go figure!) - // - KeIsArmV6 = KeArmIdCodeRegisterGet().Architecture == 7; - - // - // Set the number of TLB entries and ASIDs - // +NTAPI +KiInitializePcr(IN ULONG ProcessorNumber, + IN PKIPCR Pcr, + IN PKTHREAD IdleThread, + IN PVOID PanicStack, + IN PVOID InterruptStack) +{ + ULONG i; + + /* Set the Current Thread */ + Pcr->PrcbData.CurrentThread = IdleThread; + + /* Set pointers to ourselves */ + Pcr->Self = (PKPCR)Pcr; + Pcr->Prcb = &Pcr->PrcbData; + + /* Set the PCR Version */ + Pcr->MajorVersion = PCR_MAJOR_VERSION; + Pcr->MinorVersion = PCR_MINOR_VERSION; + + /* Set the PCRB Version */ + Pcr->PrcbData.MajorVersion = 1; + Pcr->PrcbData.MinorVersion = 1; + + /* Set the Build Type */ + Pcr->PrcbData.BuildType = 0; +#ifndef CONFIG_SMP + Pcr->PrcbData.BuildType |= PRCB_BUILD_UNIPROCESSOR; +#endif +#if DBG + Pcr->PrcbData.BuildType |= PRCB_BUILD_DEBUG; +#endif + + /* Set the Processor Number and current Processor Mask */ + Pcr->PrcbData.Number = (UCHAR)ProcessorNumber; + Pcr->PrcbData.SetMember = 1 << ProcessorNumber; + + /* Set the PRCB for this Processor */ + KiProcessorBlock[ProcessorNumber] = Pcr->Prcb; + + /* Start us out at PASSIVE_LEVEL */ + Pcr->Irql = PASSIVE_LEVEL; + + /* Set the stacks */ + Pcr->PanicStack = PanicStack; + Pcr->InterruptStack = InterruptStack; + + /* Setup the processor set */ + Pcr->PrcbData.MultiThreadProcessorSet = Pcr->PrcbData.SetMember; + + /* Copy cache information from the loader block */ + Pcr->FirstLevelDcacheSize = KeLoaderBlock->u.Arm.FirstLevelDcacheSize; + Pcr->SecondLevelDcacheSize = KeLoaderBlock->u.Arm.SecondLevelDcacheSize; + Pcr->FirstLevelIcacheSize = KeLoaderBlock->u.Arm.FirstLevelIcacheSize; + Pcr->SecondLevelIcacheSize = KeLoaderBlock->u.Arm.SecondLevelIcacheSize; + Pcr->FirstLevelDcacheFillSize = KeLoaderBlock->u.Arm.FirstLevelDcacheFillSize; + Pcr->SecondLevelDcacheFillSize = KeLoaderBlock->u.Arm.SecondLevelDcacheFillSize; + Pcr->FirstLevelIcacheFillSize = KeLoaderBlock->u.Arm.FirstLevelIcacheFillSize; + Pcr->SecondLevelIcacheFillSize = KeLoaderBlock->u.Arm.SecondLevelIcacheFillSize; + + /* Set global d-cache fill and alignment values */ + if (!Pcr->SecondLevelDcacheSize) + { + /* Use the first level */ + Pcr->DcacheFillSize = Pcr->FirstLevelDcacheSize; + } + else + { + /* Use the second level */ + Pcr->DcacheFillSize = Pcr->SecondLevelDcacheSize; + } + + /* Set the alignment */ + Pcr->DcacheAlignment = Pcr->DcacheFillSize - 1; + + /* Set global i-cache fill and alignment values */ + if (!Pcr->SecondLevelIcacheSize) + { + /* Use the first level */ + Pcr->IcacheFillSize = Pcr->FirstLevelIcacheSize; + } + else + { + /* Use the second level */ + Pcr->IcacheFillSize = Pcr->SecondLevelIcacheSize; + } + + /* Set the alignment */ + Pcr->IcacheAlignment = Pcr->IcacheFillSize - 1; + + /* Set processor information */ + Pcr->ProcessorId = KeArmIdCodeRegisterGet().AsUlong; + + /* Set all interrupt routines to unexpected interrupts as well */ + for (i = 0; i < MAXIMUM_VECTOR; i++) + { + /* Point to the same template */ + Pcr->InterruptRoutine[i] = (PVOID)&KxUnexpectedInterrupt.DispatchCode; + } + + /* Set default stall factor */ + Pcr->StallScaleFactor = 50; + + /* Setup software interrupts */ + Pcr->InterruptRoutine[PASSIVE_LEVEL] = KiPassiveRelease; + Pcr->InterruptRoutine[APC_LEVEL] = KiApcInterrupt; + Pcr->InterruptRoutine[DISPATCH_LEVEL] = KiDispatchInterrupt; + Pcr->ReservedVectors = (1 << PASSIVE_LEVEL) | + (1 << APC_LEVEL) | + (1 << DISPATCH_LEVEL) | + (1 << IPI_LEVEL); +} + +VOID +KiInitializeMachineType(VOID) +{ + /* Detect ARM version */ + KeIsArmV6 = KeArmIdCodeRegisterGet().Architecture >= 7; + + /* Set the number of TLB entries and ASIDs */ KeNumberTbEntries = 64; if (__ARMV6__) { - // - // 256 ASIDs on v6/v7 - // + /* 256 ASIDs on v6/v7 */ KeNumberProcessIds = 256; } else { - // - // The TLB is VIVT on v4/v5 - // + /* The TLB is VIVT on v4/v5 */ KeNumberProcessIds = 0; } - - // - // Flush the TLB - // +} + +VOID +KiInitializeSystem(IN PLOADER_PARAMETER_BLOCK LoaderBlock) +{ + ULONG Cpu; + PKTHREAD InitialThread; + PKPROCESS InitialProcess; + ARM_CONTROL_REGISTER ControlRegister; + PKIPCR Pcr = (PKIPCR)KeGetPcr(); + PKTHREAD Thread; + + /* Flush the TLB */ KeFlushTb(); - // - // Build the KIPCR pte - // - Pte.L1.Section.Type = SectionPte; - Pte.L1.Section.Buffered = FALSE; - Pte.L1.Section.Cached = FALSE; - Pte.L1.Section.Reserved = 1; // ARM926EJ-S manual recommends setting to 1 - Pte.L1.Section.Domain = Domain0; - Pte.L1.Section.Access = SupervisorAccess; - Pte.L1.Section.BaseAddress = LoaderBlock->u.Arm.PcrPage; - Pte.L1.Section.Ignored = Pte.L1.Section.Ignored1 = 0; - - // - // Map it into kernel address space by locking it into the TLB - // - KeFillFixedEntryTb(Pte, (PVOID)KIPCR, PCR_ENTRY); - - // - // Now map the PCR into user address space as well (read-only) - // - Pte.L1.Section.Access = SharedAccess; - KeFillFixedEntryTb(Pte, (PVOID)USPCR, PCR_ENTRY + 1); - - // - // Now we should be able to use the PCR... - // - Pcr = (PKPCR)KeGetPcr(); - - // - // Set the cache policy (HACK) - // - Pcr->CachePolicy = 0; - Pcr->AlignedCachePolicy = 0; - - // - // Copy cache information from the loader block - // - Pcr->FirstLevelDcacheSize = LoaderBlock->u.Arm.FirstLevelDcacheSize; - Pcr->SecondLevelDcacheSize = LoaderBlock->u.Arm.SecondLevelDcacheSize; - Pcr->FirstLevelIcacheSize = LoaderBlock->u.Arm.FirstLevelIcacheSize; - Pcr->SecondLevelIcacheSize = LoaderBlock->u.Arm.SecondLevelIcacheSize; - Pcr->FirstLevelDcacheFillSize = LoaderBlock->u.Arm.FirstLevelDcacheFillSize; - Pcr->SecondLevelDcacheFillSize = LoaderBlock->u.Arm.SecondLevelDcacheFillSize; - Pcr->FirstLevelIcacheFillSize = LoaderBlock->u.Arm.FirstLevelIcacheFillSize; - Pcr->SecondLevelIcacheFillSize = LoaderBlock->u.Arm.SecondLevelIcacheFillSize; - - // - // Set global d-cache fill and alignment values - // - if (!Pcr->SecondLevelDcacheSize) - { - // - // Use the first level - // - Pcr->DcacheFillSize = Pcr->FirstLevelDcacheSize; - } - else - { - // - // Use the second level - // - Pcr->DcacheFillSize = Pcr->SecondLevelDcacheSize; - } - - // - // Set the alignment - // - Pcr->DcacheAlignment = Pcr->DcacheFillSize - 1; - - // - // Set global i-cache fill and alignment values - // - if (!Pcr->SecondLevelIcacheSize) - { - // - // Use the first level - // - Pcr->IcacheFillSize = Pcr->FirstLevelIcacheSize; - } - else - { - // - // Use the second level - // - Pcr->IcacheFillSize = Pcr->SecondLevelIcacheSize; - } - - // - // Set the alignment - // - Pcr->IcacheAlignment = Pcr->IcacheFillSize - 1; - - // - // Now sweep caches - // + /* Save the loader block and get the current CPU */ + KeLoaderBlock = LoaderBlock; + Cpu = KeNumberProcessors; + + /* Save the initial thread and process */ + InitialThread = (PKTHREAD)LoaderBlock->Thread; + InitialProcess = (PKPROCESS)LoaderBlock->Process; + + /* Clean the APC List Head */ + InitializeListHead(&InitialThread->ApcState.ApcListHead[KernelMode]); + + /* Initialize the machine type */ + KiInitializeMachineType(); + + /* Skip initial setup if this isn't the Boot CPU */ + if (Cpu) goto AppCpuInit; + + /* Initialize the PCR */ + RtlZeroMemory(Pcr, PAGE_SIZE); + KiInitializePcr(Cpu, + Pcr, + InitialThread, + (PVOID)LoaderBlock->u.Arm.PanicStack, + (PVOID)LoaderBlock->u.Arm.InterruptStack); + + /* Now sweep caches */ HalSweepIcache(); HalSweepDcache(); - // - // Set PCR version - // - Pcr->MinorVersion = PCR_MINOR_VERSION; - Pcr->MajorVersion = PCR_MAJOR_VERSION; - - // - // Set boot PRCB - // - Pcr->Prcb = (PKPRCB)LoaderBlock->Prcb; - - // - // Set the different stacks - // - Pcr->InitialStack = (PVOID)LoaderBlock->KernelStack; - Pcr->PanicStack = (PVOID)LoaderBlock->u.Arm.PanicStack; - Pcr->InterruptStack = (PVOID)LoaderBlock->u.Arm.InterruptStack; - - // - // Set the current thread - // - Pcr->CurrentThread = (PKTHREAD)LoaderBlock->Thread; - - // - // Set the current IRQL to high - // - Pcr->CurrentIrql = HIGH_LEVEL; - - // - // Set processor information - // - Pcr->ProcessorId = KeArmIdCodeRegisterGet().AsUlong; - Pcr->SystemReserved[0] = KeArmControlRegisterGet().AsUlong; - - // - // Set the exception address to high - // + /* Set us as the current process */ + InitialThread->ApcState.Process = InitialProcess; + +AppCpuInit: + /* Setup CPU-related fields */ + Pcr->Number = Cpu; + Pcr->SetMember = 1 << Cpu; + Pcr->SetMemberCopy = 1 << Cpu; + Pcr->PrcbData.SetMember = 1 << Cpu; + + /* Initialize the Processor with HAL */ + HalInitializeProcessor(Cpu, KeLoaderBlock); + + /* Set active processors */ + KeActiveProcessors |= Pcr->SetMember; + KeNumberProcessors++; + + /* Check if this is the boot CPU */ + if (!Cpu) + { + /* Initialize debugging system */ + KdInitSystem(0, KeLoaderBlock); + + /* Check for break-in */ + if (KdPollBreakIn()) DbgBreakPointWithStatus(DBG_STATUS_CONTROL_C); + } + + /* Raise to HIGH_LEVEL */ + KfRaiseIrql(HIGH_LEVEL); + + /* Set the exception address to high */ ControlRegister = KeArmControlRegisterGet(); ControlRegister.HighVectors = TRUE; KeArmControlRegisterSet(ControlRegister); - // - // Setup the exception vector table - // + /* Setup the exception vector table */ RtlCopyMemory((PVOID)0xFFFF0000, &KiArmVectorTable, 14 * sizeof(PVOID)); - // - // Initialize the rest of the kernel now - // + /* Initialize the rest of the kernel now */ KiInitializeKernel((PKPROCESS)LoaderBlock->Process, (PKTHREAD)LoaderBlock->Thread, (PVOID)LoaderBlock->KernelStack, - (PKPRCB)LoaderBlock->Prcb, + Pcr->Prcb, Pcr->Prcb->Number, - LoaderBlock); - - - // - // Jump to idle loop - // + KeLoaderBlock); + + /* Set the priority of this thread to 0 */ + Thread = KeGetCurrentThread(); + Thread->Priority = 0; + + /* Force interrupts enabled and lower IRQL back to DISPATCH_LEVEL */ + _enable(); + KfLowerIrql(DISPATCH_LEVEL); + + /* Set the right wait IRQL */ + Thread->WaitIrql = DISPATCH_LEVEL; + + /* Jump into the idle loop */ KiIdleLoop(); } + +ULONG +DbgPrintEarly(const char *fmt, ...) +{ + va_list args; + unsigned int i; + char Buffer[1024]; + PCHAR String = Buffer; + + va_start(args, fmt); + i = vsprintf(Buffer, fmt, args); + va_end(args); + + /* Output the message */ + while (*String != 0) + { + if (*String == '\n') + { + KdPortPutByteEx(NULL, '\r'); + } + KdPortPutByteEx(NULL, *String); + String++; + } + + return STATUS_SUCCESS; +}

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[sir_richard] 45512: [NTOS]: Update code to use new KPCR structure. [NTOS]: Make all trap code currently spin forever, because it has not been reviewed yet.
by sir_richard＠svn.reactos.org 09 Feb '10

09 Feb '10

Author: sir_richard Date: Tue Feb 9 03:09:34 2010 New Revision: 45512 URL: http://svn.reactos.org/svn/reactos?rev=45512&view=rev Log: [NTOS]: Update code to use new KPCR structure. [NTOS]: Make all trap code currently spin forever, because it has not been reviewed yet. Modified: trunk/reactos/ntoskrnl/ke/arm/trapc.c trunk/reactos/ntoskrnl/ke/arm/usercall.c Modified: trunk/reactos/ntoskrnl/ke/arm/trapc.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ke/arm/trapc.c?re… ============================================================================== --- trunk/reactos/ntoskrnl/ke/arm/trapc.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/ke/arm/trapc.c [iso-8859-1] Tue Feb 9 03:09:34 2010 @@ -25,6 +25,9 @@ // // Loop forever... that's why this is an idle loop // + DPRINT1("[IDLE LOOP]\n"); + while (TRUE); + while (TRUE) { // @@ -117,9 +120,12 @@ KiSwapContextInternal(IN PKTHREAD OldThread, IN PKTHREAD NewThread) { - PKPCR Pcr = (PKPCR)KeGetPcr(); + PKIPCR Pcr = (PKIPCR)KeGetPcr(); PKPRCB Prcb = Pcr->Prcb; PKPROCESS OldProcess, NewProcess; + + DPRINT1("SWAP\n"); + while (TRUE); // // Increase context switch count @@ -163,7 +169,7 @@ // Increase thread context switches // NewThread->ContextSwitches++; - +#if 0 // I don't buy this // // Set us as the current thread // NOTE: On RISC Platforms, there is both a KPCR CurrentThread, and a @@ -175,7 +181,7 @@ // there as well. // Pcr->CurrentThread = NewThread; - +#endif // // DPCs shouldn't be active // @@ -221,7 +227,9 @@ KPROCESSOR_MODE PreviousMode; KEXCEPTION_FRAME ExceptionFrame; PKTRAP_FRAME TrapFrame = KeGetCurrentThread()->TrapFrame; - //DPRINT1("[APC]\n"); + + DPRINT1("[APC TRAP]\n"); + while (TRUE); // // Isolate previous mode @@ -257,14 +265,17 @@ VOID KiDispatchInterrupt(VOID) { - PKPCR Pcr; + PKIPCR Pcr; PKPRCB Prcb; PKTHREAD NewThread, OldThread; + DPRINT1("[DPC TRAP]\n"); + while (TRUE); + // // Get the PCR and disable interrupts // - Pcr = (PKPCR)KeGetPcr(); + Pcr = (PKIPCR)KeGetPcr(); Prcb = Pcr->Prcb; _disable(); @@ -339,14 +350,14 @@ { KIRQL OldIrql, Irql; ULONG InterruptCause, InterruptMask; - PKPCR Pcr; + PKIPCR Pcr; PKTRAP_FRAME OldTrapFrame; ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00); // // Increment interrupt count // - Pcr = (PKPCR)KeGetPcr(); + Pcr = (PKIPCR)KeGetPcr(); Pcr->Prcb->InterruptCount++; // @@ -359,7 +370,7 @@ // Get the interrupt source // InterruptCause = HalGetInterruptSource(); -// DPRINT1("[INT] (%x) @ %p %p\n", InterruptCause, TrapFrame->SvcLr, TrapFrame->Pc); + //DPRINT1("[INT] (%x) @ %p %p\n", InterruptCause, TrapFrame->SvcLr, TrapFrame->Pc); // // Get the new IRQL and Interrupt Mask @@ -421,6 +432,10 @@ ULONG DebugType, Parameter0; EXCEPTION_RECORD ExceptionRecord; + DPRINT1("[PREFETCH ABORT] (%x) @ %p/%p/%p\n", + KeArmInstructionFaultStatusRegisterGet(), Address, TrapFrame->SvcLr, TrapFrame->Pc); + while (TRUE); + // // What we *SHOULD* do is look at the instruction fault status register // and see if it's equal to 2 (debug trap). Unfortunately QEMU doesn't seem @@ -483,8 +498,6 @@ // // Unhandled // - DPRINT1("[PREFETCH ABORT] (%x) @ %p/%p/%p\n", - KeArmInstructionFaultStatusRegisterGet(), Address, TrapFrame->SvcLr, TrapFrame->Pc); UNIMPLEMENTED; ASSERT(FALSE); return STATUS_SUCCESS; @@ -497,6 +510,10 @@ PVOID Address = (PVOID)KeArmFaultAddressRegisterGet(); ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00); + DPRINT1("[ABORT] (%x) @ %p/%p/%p\n", + KeArmFaultStatusRegisterGet(), Address, TrapFrame->SvcLr, TrapFrame->Pc); + while (TRUE); + // // Check if this is a page fault // @@ -512,8 +529,6 @@ // // Unhandled // - DPRINT1("[ABORT] (%x) @ %p/%p/%p\n", - KeArmFaultStatusRegisterGet(), Address, TrapFrame->SvcLr, TrapFrame->Pc); UNIMPLEMENTED; ASSERT(FALSE); return STATUS_SUCCESS; @@ -527,6 +542,9 @@ ULONG Instruction; ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00); + DPRINT1("[SWI] @ %p/%p\n", TrapFrame->SvcLr, TrapFrame->Pc); + while (TRUE); + // // Get the current thread // Modified: trunk/reactos/ntoskrnl/ke/arm/usercall.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ke/arm/usercall.c… ============================================================================== --- trunk/reactos/ntoskrnl/ke/arm/usercall.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/ke/arm/usercall.c [iso-8859-1] Tue Feb 9 03:09:34 2010 @@ -226,7 +226,7 @@ // // Forcibly put us in a sane state // - KeGetPcr()->CurrentIrql = 0; + KeGetPcr()->Irql = 0; _disable(); //

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[sir_richard] 45511: [ARMDDK]: Use the same KPCR structure on ARM as on x86. [ARMDDK]: Use the same addresses for KPCR and KUSER_SHARED_DATA on ARM as on x86. On ARM however, since there are no "segments", the KPCR is also mapped in user-mode, read-only, to have a static structure that can point to the current TEB.
by sir_richard＠svn.reactos.org 09 Feb '10

09 Feb '10

Author: sir_richard Date: Tue Feb 9 03:08:24 2010 New Revision: 45511 URL: http://svn.reactos.org/svn/reactos?rev=45511&view=rev Log: [ARMDDK]: Use the same KPCR structure on ARM as on x86. [ARMDDK]: Use the same addresses for KPCR and KUSER_SHARED_DATA on ARM as on x86. On ARM however, since there are no "segments", the KPCR is also mapped in user-mode, read-only, to have a static structure that can point to the current TEB. Modified: trunk/reactos/include/reactos/arm/armddk.h Modified: trunk/reactos/include/reactos/arm/armddk.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/reactos/arm/armddk… ============================================================================== --- trunk/reactos/include/reactos/arm/armddk.h [iso-8859-1] (original) +++ trunk/reactos/include/reactos/arm/armddk.h [iso-8859-1] Tue Feb 9 03:08:24 2010 @@ -28,10 +28,10 @@ // // FIXME: mmtypes.h? // -#define KIPCR 0xFFFFF000 -#define KI_USER_SHARED_DATA 0xFFFFE000 +#define KIP0PCRADDRESS 0xFFDFF000 +#define KI_USER_SHARED_DATA 0xFFDF0000 #define USPCR 0x7FFF0000 -#define PCR ((volatile KPCR * const)KIPCR) +#define PCR ((KPCR * const)KIP0PCRADDRESS) #define USERPCR ((volatile KPCR * const)USPCR) #define KeGetPcr() PCR #ifndef _WINNT_H @@ -47,24 +47,12 @@ #define MM_SYSTEM_RANGE_START MmSystemRangeStart #define MM_USER_PROBE_ADDRESS MmUserProbeAddress #define MM_LOWEST_USER_ADDRESS (PVOID)0x10000 -#define MM_LOWEST_SYSTEM_ADDRESS (PVOID)0xC1400000 +#define MM_LOWEST_SYSTEM_ADDRESS (PVOID)0xC0800000 // // Maximum IRQs // #define MAXIMUM_VECTOR 16 - -// -// Just read it from the PCR -// -#define KeGetCurrentProcessorNumber() (int)PCR->Number -#define KeGetCurrentIrql() PCR->CurrentIrql -#define _KeGetCurrentThread() PCR->CurrentThread -#define _KeGetPreviousMode() PCR->CurrentThread->PreviousMode -#define _KeIsExecutingDpc() (PCR->DpcRoutineActive != 0) -#define KeGetCurrentThread() _KeGetCurrentThread() -#define KeGetPreviousMode() _KeGetPreviousMode() -#define KeGetDcacheFillSize() PCR->DcacheFillSize // @@ -132,7 +120,6 @@ // // Processor Control Region -// On ARM, it's actually readable from user-mode, much like KUSER_SHARED_DATA // #ifdef _WINNT_H typedef @@ -141,60 +128,36 @@ #endif typedef struct _KPCR { - ULONG MinorVersion; - ULONG MajorVersion; - PKINTERRUPT_ROUTINE InterruptRoutine[32]; - PVOID XcodeDispatch; - ULONG FirstLevelDcacheSize; - ULONG FirstLevelDcacheFillSize; - ULONG FirstLevelIcacheSize; - ULONG FirstLevelIcacheFillSize; - ULONG SecondLevelDcacheSize; - ULONG SecondLevelDcacheFillSize; - ULONG SecondLevelIcacheSize; - ULONG SecondLevelIcacheFillSize; + union + { + NT_TIB NtTib; + struct + { + struct _EXCEPTION_REGISTRATION_RECORD *Used_ExceptionList; // Unused + PVOID Used_StackBase; // Unused + PVOID PerfGlobalGroupMask; + PVOID TssCopy; // Unused + ULONG ContextSwitches; + KAFFINITY SetMemberCopy; // Unused + PVOID Used_Self; + }; + }; + struct _KPCR *Self; struct _KPRCB *Prcb; - struct _TEB *Teb; - PVOID TlsArray; - ULONG DcacheFillSize; - ULONG IcacheAlignment; - ULONG IcacheFillSize; - ULONG ProcessorId; - ULONG ProfileInterval; - ULONG ProfileCount; - ULONG StallExecutionCount; + KIRQL Irql; + ULONG IRR; // Unused + ULONG IrrActive; // Unused + ULONG IDR; // Unused + PVOID KdVersionBlock; + PVOID IDT; // Unused + PVOID GDT; // Unused + PVOID TSS; // Unused + USHORT MajorVersion; + USHORT MinorVersion; + KAFFINITY SetMember; ULONG StallScaleFactor; - CCHAR Number; - PVOID DataBusError; - PVOID InstructionBusError; - ULONG CachePolicy; - ULONG AlignedCachePolicy; - UCHAR IrqlMask[32]; - ULONG IrqlTable[32]; - UCHAR CurrentIrql; - KAFFINITY SetMember; - struct _KTHREAD *CurrentThread; - ULONG ReservedVectors; - KAFFINITY NotMember; - ULONG SystemReserved[6]; - ULONG DcacheAlignment; - ULONG HalReserved[64]; - BOOLEAN FirstLevelActive; - BOOLEAN DpcRoutineActive; - ULONG CurrentPid; - BOOLEAN OnInterruptStack; - PVOID SavedInitialStack; - PVOID SavedStackLimit; - PVOID SystemServiceDispatchStart; - PVOID SystemServiceDispatchEnd; - PVOID InterruptStack; - PVOID PanicStack; - PVOID BadVaddr; - PVOID InitialStack; - PVOID StackLimit; - ULONG QuantumEnd; - PVOID PerfGlobalGroupMask; - ULONG ContextSwitches; + UCHAR SpareUnused; + UCHAR Number; } KPCR, *PKPCR; // @@ -203,7 +166,7 @@ FORCEINLINE struct _TEB* NtCurrentTeb(VOID) { - return (struct _TEB*)USERPCR->Teb; + return (struct _TEB*)USERPCR->Used_Self; } #ifndef _WINNT_H

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[sir_richard] 45510: [ARM DDK]: Use the closest possible approximation to the x86 KPCR/KPRCB (in fact, the public KPCR is identical, just the KIPCR is different, internally), instead of a mashup of PPC and MIPS structures.
by sir_richard＠svn.reactos.org 09 Feb '10

09 Feb '10

Author: sir_richard Date: Tue Feb 9 03:06:29 2010 New Revision: 45510 URL: http://svn.reactos.org/svn/reactos?rev=45510&view=rev Log: [ARM DDK]: Use the closest possible approximation to the x86 KPCR/KPRCB (in fact, the public KPCR is identical, just the KIPCR is different, internally), instead of a mashup of PPC and MIPS structures. Modified: trunk/reactos/include/ndk/arm/ketypes.h Modified: trunk/reactos/include/ndk/arm/ketypes.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/ndk/arm/ketypes.h?… ============================================================================== --- trunk/reactos/include/ndk/arm/ketypes.h [iso-8859-1] (original) +++ trunk/reactos/include/ndk/arm/ketypes.h [iso-8859-1] Tue Feb 9 03:06:29 2010 @@ -316,9 +316,13 @@ UCHAR Reserved; USHORT BuildType; KAFFINITY SetMember; + UCHAR CpuType; + UCHAR CpuID; + USHORT CpuStep; KPROCESSOR_STATE ProcessorState; ULONG KernelReserved[16]; ULONG HalReserved[16]; + UCHAR PrcbPad0[92]; KSPIN_LOCK_QUEUE LockQueue[LockQueueMaximumLock]; struct _KTHREAD *NpxThread; ULONG InterruptCount; @@ -334,7 +338,6 @@ UCHAR NodeColor; UCHAR Spare1; ULONG NodeShiftedColor; - ULONG PcrPage; struct _KNODE *ParentNode; ULONG MultiThreadProcessorSet; struct _KPRCB *MultiThreadSetMaster; @@ -361,19 +364,22 @@ LARGE_INTEGER IoReadTransferCount; LARGE_INTEGER IoWriteTransferCount; LARGE_INTEGER IoOtherTransferCount; - ULONG KeContextSwitches; + ULONG SpareCounter1[8]; PP_LOOKASIDE_LIST PPLookasideList[16]; PP_LOOKASIDE_LIST PPNPagedLookasideList[32]; PP_LOOKASIDE_LIST PPPagedLookasideList[32]; volatile ULONG PacketBarrier; volatile ULONG ReverseStall; PVOID IpiFrame; + UCHAR PrcbPad2[52]; volatile PVOID CurrentPacket[3]; volatile ULONG TargetSet; volatile PKIPI_WORKER WorkerRoutine; volatile ULONG IpiFrozen; + UCHAR PrcbPad3[40]; volatile ULONG RequestSummary; volatile struct _KPRCB *SignalDone; + UCHAR PrcbPad4[56]; struct _KDPC_DATA DpcData[2]; PVOID DpcStack; ULONG MaximumDpcQueueDepth; @@ -391,15 +397,19 @@ KEVENT DpcEvent; UCHAR ThreadDpcEnable; volatile BOOLEAN QuantumEnd; + UCHAR PrcbPad50; volatile UCHAR IdleSchedule; LONG DpcSetEventRequest; + UCHAR PrcbPad5[18]; LONG TickOffset; KDPC CallDpc; + ULONG PrcbPad7[8]; LIST_ENTRY WaitListHead; ULONG ReadySummary; ULONG QueueIndex; LIST_ENTRY DispatcherReadyListHead[32]; SINGLE_LIST_ENTRY DeferredReadyListHead; + ULONG PrcbPad72[11]; PVOID ChainedInterruptList; LONG LookasideIrpFloat; volatile LONG MmPageFaultCount; @@ -415,12 +425,78 @@ volatile LONG MmDirtyWriteIoCount; volatile LONG MmMappedPagesWriteCount; volatile LONG MmMappedWriteIoCount; + ULONG SpareFields0[1]; CHAR VendorString[13]; + UCHAR InitialApicId; + UCHAR LogicalProcessorsPerPhysicalProcessor; ULONG MHz; ULONG FeatureBits; + LARGE_INTEGER UpdateSignature; volatile LARGE_INTEGER IsrTime; + LARGE_INTEGER SpareField1; + //FX_SAVE_AREA NpxSaveArea; PROCESSOR_POWER_STATE PowerState; } KPRCB, *PKPRCB; + +// +// Processor Control Region +// +typedef struct _KIPCR +{ + union + { + NT_TIB NtTib; + struct + { + struct _EXCEPTION_REGISTRATION_RECORD *Used_ExceptionList; // Unused + PVOID Used_StackBase; // Unused + PVOID PerfGlobalGroupMask; + PVOID TssCopy; // Unused + ULONG ContextSwitches; + KAFFINITY SetMemberCopy; // Unused + PVOID Used_Self; + }; + }; + struct _KPCR *Self; + struct _KPRCB *Prcb; + KIRQL Irql; + ULONG IRR; // Unused + ULONG IrrActive; // Unused + ULONG IDR; // Unused + PVOID KdVersionBlock; + PVOID IDT; // Unused + PVOID GDT; // Unused + PVOID TSS; // Unused + USHORT MajorVersion; + USHORT MinorVersion; + KAFFINITY SetMember; + ULONG StallScaleFactor; + UCHAR SpareUnused; + UCHAR Number; + // arm part + UCHAR Spare0[2]; + UCHAR IrqlMask[32]; + ULONG IrqlTable[32]; + PKINTERRUPT_ROUTINE InterruptRoutine[32]; + ULONG ReservedVectors; + ULONG FirstLevelDcacheSize; + ULONG FirstLevelDcacheFillSize; + ULONG FirstLevelIcacheSize; + ULONG FirstLevelIcacheFillSize; + ULONG SecondLevelDcacheSize; + ULONG SecondLevelDcacheFillSize; + ULONG SecondLevelIcacheSize; + ULONG SecondLevelIcacheFillSize; + ULONG DcacheFillSize; + ULONG DcacheAlignment; + ULONG IcacheAlignment; + ULONG IcacheFillSize; + ULONG ProcessorId; + PVOID InterruptStack; + PVOID PanicStack; + PVOID InitialStack; + KPRCB PrcbData; +} KIPCR, *PKIPCR; // // Macro to get current KPRCB @@ -432,5 +508,17 @@ return PCR->Prcb; } +// +// Just read it from the PCR +// +#define KeGetCurrentProcessorNumber() (int)PCR->Number +#define KeGetCurrentIrql() PCR->Irql +#define _KeGetCurrentThread() KeGetCurrentPrcb()->CurrentThread +#define _KeGetPreviousMode() KeGetCurrentPrcb()->CurrentThread->PreviousMode +#define _KeIsExecutingDpc() (KeGetCurrentPrcb()->DpcRoutineActive != 0) +#define KeGetCurrentThread() _KeGetCurrentThread() +#define KeGetPreviousMode() _KeGetPreviousMode() +#define KeGetDcacheFillSize() PCR->DcacheFillSize + #endif #endif

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[sir_richard] 45509: [NTOS]: Sync up KiDispatchException with x86 code (and going back to C comment formatting).
by sir_richard＠svn.reactos.org 09 Feb '10

09 Feb '10

Author: sir_richard Date: Tue Feb 9 03:00:52 2010 New Revision: 45509 URL: http://svn.reactos.org/svn/reactos?rev=45509&view=rev Log: [NTOS]: Sync up KiDispatchException with x86 code (and going back to C comment formatting). Modified: trunk/reactos/ntoskrnl/ke/arm/exp.c Modified: trunk/reactos/ntoskrnl/ke/arm/exp.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ke/arm/exp.c?rev=… ============================================================================== --- trunk/reactos/ntoskrnl/ke/arm/exp.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/ke/arm/exp.c [iso-8859-1] Tue Feb 9 03:00:52 2010 @@ -176,67 +176,51 @@ IN BOOLEAN FirstChance) { CONTEXT Context; - - // - // Increase number of Exception Dispatches - // + + /* Increase number of Exception Dispatches */ KeGetCurrentPrcb()->KeExceptionDispatchCount++; - - // - // Set the context flags - // + + /* Set the context flags */ Context.ContextFlags = CONTEXT_FULL; - // - // FIXME-V6: VFP Support - // - - // - // Get a Context - // + /* Check if User Mode or if the kernel debugger is enabled */ + if ((PreviousMode == UserMode) || (KeGetPcr()->KdVersionBlock)) + { + /* FIXME-V6: VFP Support */ + } + + /* Get a Context */ KeTrapFrameToContext(TrapFrame, ExceptionFrame, &Context); - - // - // Look at our exception code - // + + /* Look at our exception code */ switch (ExceptionRecord->ExceptionCode) { - // - // Breakpoint - // + /* Breakpoint */ case STATUS_BREAKPOINT: - - // - // We want the instruction right before the int 3 - // + + /* Decrement PC by four */ Context.Pc -= sizeof(ULONG); break; - - // - // Internal exception - // + + /* Internal exception */ case KI_EXCEPTION_ACCESS_VIOLATION: - - // - // Set correct code - // + + /* Set correct code */ ExceptionRecord->ExceptionCode = STATUS_ACCESS_VIOLATION; + if (PreviousMode == UserMode) + { + /* FIXME: Handle no execute */ + } break; } - - // - // Handle kernel-mode first, it's simpler - // + + /* Handle kernel-mode first, it's simpler */ if (PreviousMode == KernelMode) { - // - // Check if this is a first-chance exception - // + /* Check if this is a first-chance exception */ if (FirstChance == TRUE) { - // - // Break into the debugger for the first time - // + /* Break into the debugger for the first time */ if (KiDebugRoutine(TrapFrame, ExceptionFrame, ExceptionRecord, @@ -244,21 +228,15 @@ PreviousMode, FALSE)) { - // - // Exception was handled - // + /* Exception was handled */ goto Handled; } - - // - // If the Debugger couldn't handle it, dispatch the exception - // + + /* If the Debugger couldn't handle it, dispatch the exception */ if (RtlDispatchException(ExceptionRecord, &Context)) goto Handled; } - - // - // This is a second-chance exception, only for the debugger - // + + /* This is a second-chance exception, only for the debugger */ if (KiDebugRoutine(TrapFrame, ExceptionFrame, ExceptionRecord, @@ -266,15 +244,11 @@ PreviousMode, TRUE)) { - // - // Exception was handled - // + /* Exception was handled */ goto Handled; } - - // - // Third strike; you're out - // + + /* Third strike; you're out */ KeBugCheckEx(KMODE_EXCEPTION_NOT_HANDLED, ExceptionRecord->ExceptionCode, (ULONG_PTR)ExceptionRecord->ExceptionAddress, @@ -283,19 +257,27 @@ } else { - // - // FIXME-USER: Do user-mode exception handling - // - ASSERT(FALSE); - } - + /* FIXME: TODO */ + /* 3rd strike, kill the process */ + DPRINT1("Kill %.16s, ExceptionCode: %lx, ExceptionAddress: %lx\n", + PsGetCurrentProcess()->ImageFileName, + ExceptionRecord->ExceptionCode, + ExceptionRecord->ExceptionAddress); + + ZwTerminateProcess(NtCurrentProcess(), ExceptionRecord->ExceptionCode); + KeBugCheckEx(KMODE_EXCEPTION_NOT_HANDLED, + ExceptionRecord->ExceptionCode, + (ULONG_PTR)ExceptionRecord->ExceptionAddress, + (ULONG_PTR)TrapFrame, + 0); + } + Handled: - // - // Convert the context back into Trap/Exception Frames - // + /* Convert the context back into Trap/Exception Frames */ KeContextToTrapFrame(&Context, ExceptionFrame, TrapFrame, Context.ContextFlags, PreviousMode); + return; }

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[sir_richard] 45508: [NTOS]: Get rid of fixed TLB entries on ARM, I don't think that idea makes sense (unlike IA64 or MIPS where they are lot more flexible), since they only allow 1MB sections, not pages.
by sir_richard＠svn.reactos.org 09 Feb '10

09 Feb '10

Author: sir_richard Date: Tue Feb 9 03:00:15 2010 New Revision: 45508 URL: http://svn.reactos.org/svn/reactos?rev=45508&view=rev Log: [NTOS]: Get rid of fixed TLB entries on ARM, I don't think that idea makes sense (unlike IA64 or MIPS where they are lot more flexible), since they only allow 1MB sections, not pages. Modified: trunk/reactos/ntoskrnl/ke/arm/cpu.c Modified: trunk/reactos/ntoskrnl/ke/arm/cpu.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ke/arm/cpu.c?rev=… ============================================================================== --- trunk/reactos/ntoskrnl/ke/arm/cpu.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/ke/arm/cpu.c [iso-8859-1] Tue Feb 9 03:00:15 2010 @@ -24,7 +24,7 @@ ULONG KeProcessorLevel; ULONG KeProcessorRevision; ULONG KeFeatureBits; -ULONG KeLargestCacheLine = 32; // FIXME: It depends +ULONG KeLargestCacheLine = 64; // FIXME: It depends /* FUNCTIONS ******************************************************************/ @@ -36,83 +36,6 @@ // Just invalidate it // KeArmInvalidateTlbEntry(Virtual); -} - -VOID -KeFillFixedEntryTb(IN ARM_PTE Pte, - IN PVOID Virtual, - IN ULONG Index) -{ - ARM_LOCKDOWN_REGISTER LockdownRegister; - ULONG OldVictimCount; - volatile unsigned long Temp; - PARM_TRANSLATION_TABLE TranslationTable; - - // - // Fixed TB entries must be section entries - // - Virtual = (PVOID)((ULONG)Virtual & 0xFFF00000); - - // - // On ARM, we can't set the index ourselves, so make sure that we are not - // locking down more than 8 entries. - // - UNREFERENCED_PARAMETER(Index); - KeFixedTbEntries++; - ASSERT(KeFixedTbEntries <= 8); - - // - // Flush the address - // - KiFlushSingleTb(TRUE, Virtual); - - // - // Read lockdown register and set the preserve bit - // - LockdownRegister = KeArmLockdownRegisterGet(); - LockdownRegister.Preserve = TRUE; - OldVictimCount = LockdownRegister.Victim; - KeArmLockdownRegisterSet(LockdownRegister); - - // - // Map the PTE for this virtual address - // - TranslationTable = (PVOID)KeArmTranslationTableRegisterGet().AsUlong; - TranslationTable->Pte[(ULONG)Virtual >> PDE_SHIFT] = Pte; - - // - // Now force a miss - // - Temp = *(PULONG)Virtual; - - // - // Read lockdown register - // - LockdownRegister = KeArmLockdownRegisterGet(); - if (LockdownRegister.Victim == 0) - { - // - // This can only happen on QEMU or broken CPUs since there *has* - // to have been at least a miss since the system started. For example, - // QEMU doesn't support TLB lockdown. - // - // On these systems, we'll just keep the PTE mapped - // - } - else - { - // - // Clear the preserve bits - // - LockdownRegister.Preserve = FALSE; - ASSERT(LockdownRegister.Victim == OldVictimCount + 1); - KeArmLockdownRegisterSet(LockdownRegister); - - // - // Clear the PTE - // - TranslationTable->Pte[(ULONG)Virtual >> PDE_SHIFT].AsUlong = 0; - } } VOID

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[sir_richard] 45507: [NTOS]: Forgot to setup an IRQ stack, the kernel was working by magic since in previous incarnations of the ARM port, 0xFFFFyyyy was mapped, so a stack of 0 worked (going downwards). [NTOS]: Now FreeLDR just calls the KiSystemStartup routine correctly, without any "magic", so fix the code to use a1 instead of a2 (argument 1/2).
by sir_richard＠svn.reactos.org 09 Feb '10

09 Feb '10

Author: sir_richard Date: Tue Feb 9 02:54:14 2010 New Revision: 45507 URL: http://svn.reactos.org/svn/reactos?rev=45507&view=rev Log: [NTOS]: Forgot to setup an IRQ stack, the kernel was working by magic since in previous incarnations of the ARM port, 0xFFFFyyyy was mapped, so a stack of 0 worked (going downwards). [NTOS]: Now FreeLDR just calls the KiSystemStartup routine correctly, without any "magic", so fix the code to use a1 instead of a2 (argument 1/2). Modified: trunk/reactos/ntoskrnl/ke/arm/boot.s Modified: trunk/reactos/ntoskrnl/ke/arm/boot.s URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ke/arm/boot.s?rev… ============================================================================== --- trunk/reactos/ntoskrnl/ke/arm/boot.s [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/ke/arm/boot.s [iso-8859-1] Tue Feb 9 02:54:14 2010 @@ -14,61 +14,53 @@ NESTED_ENTRY KiSystemStartup PROLOG_END KiSystemStartup - // - // Put us in FIQ mode - // - b . + /* Put us in FIQ mode */ mrs r3, cpsr orr r3, r1, #CPSR_FIQ_MODE msr cpsr, r3 - // - // Set FIQ stack and registers - // - ldr sp, [a2, #LpbInterruptStack] + /* Set FIQ stack and registers */ + ldr sp, [a1, #LpbInterruptStack] mov r8, #0 mov r9, #0 mov r10, #0 - // - // Put us in ABORT mode - // + /* Repeat for IRQ mode */ + mrs r3, cpsr + orr r3, r1, #CPSR_IRQ_MODE + msr cpsr, r3 + ldr sp, [a1, #LpbInterruptStack] + mov r8, #0 + mov r9, #0 + mov r10, #0 + + /* Put us in ABORT mode */ mrs r3, cpsr orr r3, r1, #CPSR_ABORT_MODE msr cpsr, r3 - // - // Set panic stack - // - ldr sp, [a2, #LpbPanicStack] + /* Set panic stack */ + ldr sp, [a1, #LpbPanicStack] - // - // Put us in UND (Undefined) mode - // + /* Put us in UND (Undefined) mode */ mrs r3, cpsr orr r3, r1, #CPSR_UND_MODE msr cpsr, r3 - // - // Set panic stack - // - ldr sp, [a2, #LpbPanicStack] + /* Set panic stack */ + ldr sp, [a1, #LpbPanicStack] - // - // Put us into SVC (Supervisor) mode - // + /* Put us into SVC (Supervisor) mode */ mrs r3, cpsr orr r3, r1, #CPSR_SVC_MODE msr cpsr, r3 - // - // Switch to boot kernel stack - // - ldr sp, [a2, #LpbKernelStack] + /* Switch to boot kernel stack */ + ldr sp, [a1, #LpbKernelStack] - // - // Go to C code - // + /* Go to C code */ b KiInitializeSystem ENTRY_END KiSystemStartup + +/* EOF */

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[sir_richard] 45506: [ARM SDK]: Use real Versatile base addresses instead of the old hacked FreeLDR base addresses.
by sir_richard＠svn.reactos.org 09 Feb '10

09 Feb '10

Author: sir_richard Date: Tue Feb 9 02:47:54 2010 New Revision: 45506 URL: http://svn.reactos.org/svn/reactos?rev=45506&view=rev Log: [ARM SDK]: Use real Versatile base addresses instead of the old hacked FreeLDR base addresses. Modified: trunk/reactos/include/reactos/arm/peripherals/pl011.h trunk/reactos/include/reactos/arm/peripherals/pl190.h trunk/reactos/include/reactos/arm/peripherals/sp804.h Modified: trunk/reactos/include/reactos/arm/peripherals/pl011.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/reactos/arm/periph… ============================================================================== --- trunk/reactos/include/reactos/arm/peripherals/pl011.h [iso-8859-1] (original) +++ trunk/reactos/include/reactos/arm/peripherals/pl011.h [iso-8859-1] Tue Feb 9 02:47:54 2010 @@ -11,7 +11,7 @@ // // UART Registers // -#define UART_BASE (ULONG_PTR)0xE00F1000 /* HACK: freeldr mapped it here */ +#define UART_BASE (ULONG_PTR)0x101F1000 #define UART_PL01x_DR (UART_BASE + 0x00) #define UART_PL01x_RSR (UART_BASE + 0x04) Modified: trunk/reactos/include/reactos/arm/peripherals/pl190.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/reactos/arm/periph… ============================================================================== --- trunk/reactos/include/reactos/arm/peripherals/pl190.h [iso-8859-1] (original) +++ trunk/reactos/include/reactos/arm/peripherals/pl190.h [iso-8859-1] Tue Feb 9 02:47:54 2010 @@ -11,10 +11,10 @@ // // VIC Registers // -#define VIC_BASE (ULONG_PTR)0xE0040000 /* HACK: freeldr mapped it here */ +#define VIC_BASE (ULONG_PTR)0x10140000 -#define VIC_INT_STATUS (VIC_BASE + 0x00) -#define VIC_INT_ENABLE (VIC_BASE + 0x10) -#define VIC_INT_CLEAR (VIC_BASE + 0x14) -#define VIC_SOFT_INT (VIC_BASE + 0x18) -#define VIC_SOFT_INT_CLEAR (VIC_BASE + 0x1C) +#define VIC_INT_STATUS (PULONG)(VIC_BASE + 0x00) +#define VIC_INT_ENABLE (PULONG)(VIC_BASE + 0x10) +#define VIC_INT_CLEAR (PULONG)(VIC_BASE + 0x14) +#define VIC_SOFT_INT (PULONG)(VIC_BASE + 0x18) +#define VIC_SOFT_INT_CLEAR (PULONG)(VIC_BASE + 0x1C) Modified: trunk/reactos/include/reactos/arm/peripherals/sp804.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/reactos/arm/periph… ============================================================================== --- trunk/reactos/include/reactos/arm/peripherals/sp804.h [iso-8859-1] (original) +++ trunk/reactos/include/reactos/arm/peripherals/sp804.h [iso-8859-1] Tue Feb 9 02:47:54 2010 @@ -11,7 +11,7 @@ // // Timer Registers // -#define TIMER_BASE(x) (ULONG_PTR)(0xE00E2000 + (x * 0x1000)) /* HACK: freeldr mapped it here */ +#define TIMER_BASE(x) (ULONG_PTR)(0x101E2000 + (x * 0x1000)) #define TIMER0_LOAD TIMER_BASE(0) + 0x00 #define TIMER0_VALUE TIMER_BASE(0) + 0x04 #define TIMER0_CONTROL TIMER_BASE(0) + 0x08

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[sir_richard] 45505: [ARMLLB]: PutChar should be a UCHAR routine, this way we can print characters above 127 (extended ASCII). This is needed for the progress bar, for example.
by sir_richard＠svn.reactos.org 09 Feb '10

09 Feb '10

Author: sir_richard Date: Tue Feb 9 02:46:01 2010 New Revision: 45505 URL: http://svn.reactos.org/svn/reactos?rev=45505&view=rev Log: [ARMLLB]: PutChar should be a UCHAR routine, this way we can print characters above 127 (extended ASCII). This is needed for the progress bar, for example. Modified: trunk/reactos/boot/armllb/hw/video.c trunk/reactos/boot/armllb/inc/video.h Modified: trunk/reactos/boot/armllb/hw/video.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/armllb/hw/video.c?rev… ============================================================================== --- trunk/reactos/boot/armllb/hw/video.c [iso-8859-1] (original) +++ trunk/reactos/boot/armllb/hw/video.c [iso-8859-1] Tue Feb 9 02:46:01 2010 @@ -274,7 +274,7 @@ VOID NTAPI -LlbVideoDrawChar(IN CHAR c, +LlbVideoDrawChar(IN UCHAR c, IN PUSHORT Buffer, IN USHORT Color, IN USHORT BackColor) @@ -342,7 +342,7 @@ VOID NTAPI -LlbVideoPutChar(IN CHAR c) +LlbVideoPutChar(IN UCHAR c) { ULONG cx, cy, CharsPerLine, BackColor, ScreenWidth; Modified: trunk/reactos/boot/armllb/inc/video.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/armllb/inc/video.h?re… ============================================================================== --- trunk/reactos/boot/armllb/inc/video.h [iso-8859-1] (original) +++ trunk/reactos/boot/armllb/inc/video.h [iso-8859-1] Tue Feb 9 02:46:01 2010 @@ -15,13 +15,13 @@ VOID NTAPI LlbVideoPutChar( - IN CHAR c + IN UCHAR c ); VOID NTAPI LlbVideoDrawChar( - IN CHAR c, + IN UCHAR c, IN PUSHORT Buffer, IN USHORT Color, IN USHORT BackColor

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[sir_richard] 45504: [ARMLLB]: Fix typo.
by sir_richard＠svn.reactos.org 09 Feb '10

09 Feb '10

Author: sir_richard Date: Tue Feb 9 02:44:26 2010 New Revision: 45504 URL: http://svn.reactos.org/svn/reactos?rev=45504&view=rev Log: [ARMLLB]: Fix typo. Modified: trunk/reactos/boot/armllb/hw/versatile/hwclcd.c Modified: trunk/reactos/boot/armllb/hw/versatile/hwclcd.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/armllb/hw/versatile/h… ============================================================================== --- trunk/reactos/boot/armllb/hw/versatile/hwclcd.c [iso-8859-1] (original) +++ trunk/reactos/boot/armllb/hw/versatile/hwclcd.c [iso-8859-1] Tue Feb 9 02:44:26 2010 @@ -32,7 +32,7 @@ WRITE_REGISTER_ULONG(PL110_LCDUPBASE, (ULONG)LlbHwGetFrameBuffer()); WRITE_REGISTER_ULONG(PL110_LCDLPBASE, (ULONG)LlbHwGetFrameBuffer()); - /* Initialize timings to 1024x720 */ + /* Initialize timings to 720x400 */ WRITE_REGISTER_ULONG(PL110_LCDTIMING0, LCDTIMING0_PPL(LlbHwGetScreenWidth())); WRITE_REGISTER_ULONG(PL110_LCDTIMING1, LCDTIMING1_LPP(LlbHwGetScreenHeight()));

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