[ros-diffs] [reactos] 01/01: [NTOS:MM] Make the definitions and macros for x86 more human-readable. (#2487)

[Vadim Galyant]

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=ac843d7b82623feffc4e2…

commit ac843d7b82623feffc4e20f353925bec0c300466
Author:     Vadim Galyant <vgal(a)rambler.ru>
AuthorDate: Sat Apr 4 15:26:15 2020 +0300
Commit:     GitHub <noreply(a)github.com>
CommitDate: Sat Apr 4 14:26:15 2020 +0200

    [NTOS:MM] Make the definitions and macros for x86 more human-readable. (#2487)
    
    - Move also PDE_MAPPED_VA definition from common miarm.h to ..arch/mm.h.
    - Add assert "PAE not yet implemented".
---
 ntoskrnl/include/internal/amd64/mm.h |  3 ++
 ntoskrnl/include/internal/i386/mm.h  | 83 ++++++++++++++++++++++++++----------
 ntoskrnl/mm/ARM3/miarm.h             |  3 --
 3 files changed, 63 insertions(+), 26 deletions(-)

diff --git a/ntoskrnl/include/internal/amd64/mm.h b/ntoskrnl/include/internal/amd64/mm.h
index d4f0287acc3..0131817d4cf 100644
--- a/ntoskrnl/include/internal/amd64/mm.h
+++ b/ntoskrnl/include/internal/amd64/mm.h
@@ -35,6 +35,9 @@
 #define MM_HIGHEST_USER_ADDRESS_WOW64   0x7FFEFFFF
 #define MM_SYSTEM_RANGE_START_WOW64     0x80000000
 
+/* The size of the virtual memory area that is mapped using a single PDE */
+#define PDE_MAPPED_VA (PTE_PER_PAGE * PAGE_SIZE)
+
 /* Misc address definitions */
 //#define MI_NON_PAGED_SYSTEM_START_MIN   MM_SYSTEM_SPACE_START // FIXME
 //#define MI_SYSTEM_PTE_START             MM_SYSTEM_SPACE_START
diff --git a/ntoskrnl/include/internal/i386/mm.h b/ntoskrnl/include/internal/i386/mm.h
index 0784f6709ba..f0622f685de 100644
--- a/ntoskrnl/include/internal/i386/mm.h
+++ b/ntoskrnl/include/internal/i386/mm.h
@@ -28,18 +28,7 @@
 #define MI_DEBUG_MAPPING                        (PVOID)0xFFBFF000
 #define MI_HIGHEST_SYSTEM_ADDRESS               (PVOID)0xFFFFFFFF
 
-/* FIXME: These are different for PAE */
-#define PTE_BASE    0xC0000000
-#define PDE_BASE    0xC0300000
-#define PDE_TOP     0xC0300FFF
-#define PTE_TOP     0xC03FFFFF
-
-#define PTE_PER_PAGE 0x400
-#define PDE_PER_PAGE 0x400
-#define PPE_PER_PAGE 1
-
 /* Misc address definitions */
-#define MI_SYSTEM_PTE_BASE                      (PVOID)MiAddressToPte(NULL)
 #define MM_HIGHEST_VAD_ADDRESS \
     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
 #define MI_MAPPING_RANGE_START              (ULONG)HYPER_SPACE
@@ -128,21 +117,69 @@
 /* On x86, these two are the same */
 #define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
 
-/* Convert an address to a corresponding PTE */
-#define MiAddressToPte(x) \
-    ((PMMPTE)(((((ULONG)(x)) >> 12) << 2) + PTE_BASE))
+/*  Translating virtual addresses to physical addresses
+        (See: "Intel� 64 and IA-32 Architectures Software Developer�s Manual
+              Volume 3A: System Programming Guide, Part 1, CHAPTER 4 PAGING")
+    Page directory (PD) and Page table (PT) definitions
+    Page directory entry (PDE) and Page table entry (PTE) definitions
+*/
+
+/* Maximum number of page directories pages */
+#ifndef _X86PAE_
+#define PD_COUNT 1        /* Only one page directory page */
+#else
+#define PD_COUNT (1 << 2) /* The two most significant bits in the VA */
+#endif
+
+/* PAE not yet implemented. */
+C_ASSERT(PD_COUNT == 1);
+
+/* The number of PTEs on one page of the PT */
+#define PTE_PER_PAGE (PAGE_SIZE / sizeof(MMPTE))
+
+/* The number of PDEs on one page of the PD */
+#define PDE_PER_PAGE (PAGE_SIZE / sizeof(MMPDE))
+
+/* Maximum number of PDEs */
+#define PDE_PER_SYSTEM (PD_COUNT * PDE_PER_PAGE)
+
+/* TODO: It seems this constant is not needed for x86 */
+#define PPE_PER_PAGE 1
+
+/* Maximum number of pages for 4 GB of virtual space */
+#define MI_MAX_PAGES ((1ull << 32) / PAGE_SIZE)
+
+/* Base addresses for page tables */
+#define PTE_BASE (ULONG_PTR)0xC0000000
+#define PTE_TOP  (ULONG_PTR)(PTE_BASE + (MI_MAX_PAGES * sizeof(MMPTE)) - 1)
+#define PTE_MASK (PTE_TOP - PTE_BASE)
+
+#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(NULL)
+
+/* Base addreses for page directories */
+#define PDE_BASE (ULONG_PTR)MiPteToPde(PTE_BASE)
+#define PDE_TOP  (ULONG_PTR)(PDE_BASE + (PDE_PER_SYSTEM * sizeof(MMPDE)) - 1)
+#define PDE_MASK (PDE_TOP - PDE_BASE)
+
+/* The size of the virtual memory area that is mapped using a single PDE */
+#define PDE_MAPPED_VA (PTE_PER_PAGE * PAGE_SIZE)
+
+/* Maps the virtual address to the corresponding PTE */
+#define MiAddressToPte(Va) \
+    ((PMMPTE)(PTE_BASE + ((((ULONG_PTR)(Va)) / PAGE_SIZE) * sizeof(MMPTE))))
+
+/* Maps the virtual address to the corresponding PDE */
+#define MiAddressToPde(Va) \
+    ((PMMPDE)(PDE_BASE + ((MiAddressToPdeOffset(Va)) * sizeof(MMPDE))))
 
-/* Convert an address to a corresponding PDE */
-#define MiAddressToPde(x) \
-    ((PMMPDE)(((((ULONG)(x)) >> 22) << 2) + PDE_BASE))
+/* Takes the PTE index (for one PD page) from the virtual address */
+#define MiAddressToPteOffset(Va) \
+    ((((ULONG_PTR)(Va)) & (PDE_MAPPED_VA - 1)) / PAGE_SIZE)
 
-/* Convert an address to a corresponding PTE offset/index */
-#define MiAddressToPteOffset(x) \
-    ((((ULONG)(x)) << 10) >> 22)
+/* Takes the PDE offset (within all PDs pages) from the virtual address */
+#define MiAddressToPdeOffset(Va) (((ULONG_PTR)(Va)) / PDE_MAPPED_VA)
 
-/* Convert an address to a corresponding PDE offset/index */
-#define MiAddressToPdeOffset(x) \
-    (((ULONG)(x)) / (1024 * PAGE_SIZE))
+/* TODO: Free this variable (for offset from the pointer to the PDE) */
 #define MiGetPdeOffset MiAddressToPdeOffset
 
 /* Convert a PTE/PDE into a corresponding address */
diff --git a/ntoskrnl/mm/ARM3/miarm.h b/ntoskrnl/mm/ARM3/miarm.h
index 15c17ab462a..c242b795af6 100644
--- a/ntoskrnl/mm/ARM3/miarm.h
+++ b/ntoskrnl/mm/ARM3/miarm.h
@@ -18,9 +18,6 @@
 /* Everyone loves 64K */
 #define _64K (64 * _1KB)
 
-/* Area mapped by a PDE */
-#define PDE_MAPPED_VA  (PTE_PER_PAGE * PAGE_SIZE)
-
 /* Size of a page table */
 #define PT_SIZE  (PTE_PER_PAGE * sizeof(MMPTE))