[ros-diffs] [fireball] 29558: - Fixed a typo in the line which lead to actual zeroing of mxcsr, instead of zeroing only reserved bits (spotted by Kamil Hornicek aka "Pigglesworth"). - Improved the fix by actually applying the mask prepared earlier during kernel init (this is a more proper way to clear reserved bits of mxcsr). - SSE/SSE2/etc is not broken anymore. See issue #2748 for more details.