[ros-diffs] [rgampa] 75327: [USBXHCI] - type cast issues solved for runtimebas and doorbellbase - controller check function written to test teh event ring and command ring functionality. - Finally inetrrupt is...

Author: rgampa
Date: Thu Jul 13 06:53:28 2017
New Revision: 75327

URL: http://svn.reactos.org/svn/reactos?rev=75327&view=rev
Log:
[USBXHCI]
- type cast issues solved for runtimebas and doorbellbase
- controller check function written to test teh event ring and command ring
functionality.
- Finally inetrrupt is being generated upon connecting a pen drive. Interrupt service
function is being called
CORE-13344

Modified:
    branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/hardware.h
    branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.c
    branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.h

Modified: branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/hardware.h
URL:
http://svn.reactos.org/svn/reactos/branches/GSoC_2017/usbxhci/reactos/drive…
==============================================================================
--- branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/hardware.h	[iso-8859-1]
(original)
+++ branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/hardware.h	[iso-8859-1] Thu Jul
13 06:53:28 2017
@@ -1,5 +1,5 @@
 /* XHCI hardware registers */
-
+// base io addr register offsets
 #define XHCI_HCSP1            1
 #define XHCI_HCSP2            2
 #define XHCI_HCSP3            3
@@ -7,7 +7,7 @@
 #define XHCI_DBOFF            5
 #define XHCI_RTSOFF           6
 #define XHCI_HCCP2            7
-
+// operational register offsets
 #define XHCI_USBCMD           0
 #define XHCI_USBSTS           1
 #define XHCI_DNCTRL           5
@@ -15,16 +15,24 @@
 #define XHCI_DCBAAP           12
 #define XHCI_CONFIG           14
 #define XHCI_PORTSC           100
-
-#define XHCI_IMAN             0
-#define XHCI_IMOD             1
-#define XHCI_ERSTSZ           2
-#define XHCI_ERSTBA           4
-#define XHCI_ERSTDP           6
-
-
-
-typedef union _XHCI_HC_STRUCTURAL_PARAMS_1 {
+// runtime register offsets
+#define XHCI_IMAN             8
+#define XHCI_IMOD             9
+#define XHCI_ERSTSZ           10
+#define XHCI_ERSTBA           12
+#define XHCI_ERSTDP           14
+
+
+typedef volatile union _XHCI_CAPLENGHT_INTERFACE_VERSION {
+  struct {
+    ULONG CapabilityRegistersLength                         : 8; 
+    ULONG Rsvd                                              : 8; 
+    ULONG HostControllerInterfaceVersion                    : 16;
+  };
+  ULONG AsULONG;
+} XHCI_CAPLENGHT_INTERFACE_VERSION;
+
+typedef volatile union _XHCI_HC_STRUCTURAL_PARAMS_1 {
   struct {
     ULONG NumberOfDeviceSlots     : 8; // MAXSLOTS
     ULONG NumberOfInterrupters    : 11; // MAXINTRS
@@ -34,7 +42,7 @@
   ULONG AsULONG;
 } XHCI_HC_STRUCTURAL_PARAMS_1;
 
-typedef union _XHCI_HC_STRUCTURAL_PARAMS_2 {
+typedef volatile union _XHCI_HC_STRUCTURAL_PARAMS_2 {
   struct {
     ULONG Ist               : 4; // Isochronous Scheduling Treshold 
     ULONG ERSTMax           : 4; //Even ring segment table max
@@ -46,7 +54,7 @@
   ULONG AsULONG;
 } XHCI_HC_STRUCTURAL_PARAMS_2;
 
-typedef union _XHCI_HC_STRUCTURAL_PARAMS_3 {
+typedef volatile union _XHCI_HC_STRUCTURAL_PARAMS_3 {
   struct {
     ULONG U1DeviceExitLatecy : 8;
     ULONG Rsvd               : 8;
@@ -55,7 +63,7 @@
   ULONG AsULONG;
 } XHCI_HC_STRUCTURAL_PARAMS_3;
 
-typedef union _XHCI_HC_CAPABILITY_PARAMS_1 {  // need to comment full forms, pg 291 in
xHCI documentation 
+typedef volatile union _XHCI_HC_CAPABILITY_PARAMS_1 {  // need to comment full forms, pg
291 in xHCI documentation 
   struct {
     ULONG AC64               : 1;
     ULONG BNC                : 1;
@@ -75,7 +83,7 @@
   ULONG AsULONG;
 } XHCI_HC_CAPABILITY_PARAMS_1;
 
-typedef union _XHCI_DOORBELL_OFFSET {
+typedef volatile union _XHCI_DOORBELL_OFFSET {
   struct {
     ULONG Rsvd               : 2;
     ULONG DBArrayOffset      : 30;
@@ -83,7 +91,7 @@
   ULONG AsULONG;
 } XHCI_DOORBELL_OFFSET;
 
-typedef union _XHCI_RT_REGISTER_SPACE_OFFSET { //RUNTIME REGISTER SPACE OFFSET
+typedef volatile union _XHCI_RT_REGISTER_SPACE_OFFSET { //RUNTIME REGISTER SPACE OFFSET
   struct {
     ULONG Rsvd               : 5;
     ULONG RTSOffset          : 27;
@@ -91,7 +99,7 @@
   ULONG AsULONG;
 } XHCI_RT_REGISTER_SPACE_OFFSET;
 
-typedef union _XHCI_HC_CAPABILITY_PARAMS_2 {
+typedef volatile union _XHCI_HC_CAPABILITY_PARAMS_2 {
   struct {
     ULONG U3C                : 1;
     ULONG CMC                : 1;
@@ -104,7 +112,7 @@
   ULONG AsULONG;
 } XHCI_HC_CAPABILITY_PARAMS_2;
 
-typedef union _XHCI_USB_COMMAND {
+typedef volatile union _XHCI_USB_COMMAND {
   struct {
     ULONG RunStop                    : 1;
     ULONG HCReset                    : 1;
@@ -123,7 +131,7 @@
   ULONG AsULONG;
 } XHCI_USB_COMMAND;
 
-typedef union _XHCI_USB_STATUS {
+typedef volatile union _XHCI_USB_STATUS {
   struct {
     ULONG HCHalted               : 1;
     ULONG RsvdZ1                 : 1;
@@ -141,7 +149,7 @@
   ULONG AsULONG;
 } XHCI_USB_STATUS;
 
-typedef union _XHCI_PAGE_SIZE { 
+typedef volatile union _XHCI_PAGE_SIZE { 
   struct {
     ULONG PageSize           : 16;
     ULONG Rsvd               : 16;
@@ -149,7 +157,7 @@
   ULONG AsULONG;
 } XHCI_PAGE_SIZE;
 
-typedef union _XHCI_DEVICE_NOTIFICATION_CONTROL { 
+typedef volatile union _XHCI_DEVICE_NOTIFICATION_CONTROL { 
   struct {
     ULONG NotificationEnable : 16;
     ULONG Rsvd               : 16;
@@ -157,7 +165,7 @@
   ULONG AsULONG;
 } XHCI_DEVICE_NOTIFICATION_CONTROL;
 
-typedef union _XHCI_COMMAND_RING_CONTROL { 
+typedef volatile union _XHCI_COMMAND_RING_CONTROL { 
   struct {
     ULONGLONG RingCycleState           : 1;
     ULONGLONG CommandStop              : 1;
@@ -170,7 +178,7 @@
   ULONGLONG AsULONGLONG;
 } XHCI_COMMAND_RING_CONTROL;
 
-typedef union _XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY_POINTER { 
+typedef volatile union _XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY_POINTER { 
   struct {
     ULONGLONG RsvdZ                       : 6;
     ULONGLONG DCBAAPointerLo              : 26;
@@ -179,7 +187,7 @@
   ULONGLONG AsULONGLONG;
 } XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY_POINTER;
 
-typedef union _XHCI_CONFIGURE { 
+typedef volatile union _XHCI_CONFIGURE { 
   struct {
     ULONG MaxDeviceSlotsEnabled        : 8;
     ULONG U3EntryEnable                : 1;
@@ -189,7 +197,7 @@
   ULONG AsULONG;
 } XHCI_CONFIGURE;
 
-typedef union _XHCI_PORT_STATUS_CONTROL {
+typedef volatile union _XHCI_PORT_STATUS_CONTROL {
   struct {
     ULONG CCS                : 1;
     ULONG PED                : 1;
@@ -220,7 +228,7 @@
 } XHCI_PORT_STATUS_CONTROL;
 
 // Interrupt Register Set
-typedef union _XHCI_INTERRUPTER_MANAGEMENT {
+typedef volatile union _XHCI_INTERRUPTER_MANAGEMENT {
     struct {
         ULONG InterruptPending  : 1;
         ULONG InterruptEnable   : 1;
@@ -229,7 +237,7 @@
     ULONG AsULONG;
 } XHCI_INTERRUPTER_MANAGEMENT;
 
-typedef union _XHCI_INTERRUPTER_MODERATION {
+typedef volatile union _XHCI_INTERRUPTER_MODERATION {
     struct {
         ULONG InterruptModIterval  : 16;
         ULONG InterruptModCounter  : 16;
@@ -237,7 +245,7 @@
     ULONG AsULONG;
 } XHCI_INTERRUPTER_MODERATION;
 
-typedef union _XHCI_EVENT_RING_TABLE_SIZE {
+typedef volatile union _XHCI_EVENT_RING_TABLE_SIZE {
     struct {
         ULONG EventRingSegTableSize  : 16;
         ULONG RsvdP                  : 16;
@@ -245,7 +253,7 @@
     ULONG AsULONG;
 } XHCI_EVENT_RING_TABLE_SIZE;
 
-typedef union _XHCI_EVENT_RING_TABLE_BASE_ADDR { 
+typedef volatile union _XHCI_EVENT_RING_TABLE_BASE_ADDR { 
   struct {
     ULONGLONG RsvdP                       : 6;
     ULONGLONG EventRingSegTableBaseAddr   : 58;
@@ -253,7 +261,7 @@
   ULONGLONG AsULONGLONG;
 } XHCI_EVENT_RING_TABLE_BASE_ADDR;
 
-typedef union _XHCI_EVENT_RING_DEQUEUE_POINTER { 
+typedef volatile union _XHCI_EVENT_RING_DEQUEUE_POINTER { 
   struct {
     ULONGLONG DequeueERSTIndex            : 3;
     ULONGLONG EventHandlerBusy            : 1;
@@ -261,3 +269,13 @@
   };
   ULONGLONG AsULONGLONG;
 } XHCI_EVENT_RING_DEQUEUE_POINTER;
+
+// Doorbell register
+typedef volatile union _XHCI_DOORBELL {
+  struct {
+    ULONG DoorBellTarget        : 8;
+    ULONG RsvdZ                 : 8;
+    ULONG DoorbellStreamID      : 16;
+  };
+  ULONG AsULONG;
+} XHCI_DOORBELL;

Modified: branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.c
URL:
http://svn.reactos.org/svn/reactos/branches/GSoC_2017/usbxhci/reactos/drive…
==============================================================================
--- branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.c	[iso-8859-1]
(original)
+++ branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.c	[iso-8859-1] Thu Jul
13 06:53:28 2017
@@ -45,7 +45,103 @@
 {
     DPRINT1("XHCI_CloseEndpoint: UNIMPLEMENTED. FIXME\n");
 }
-
+MPSTATUS
+NTAPI
+XHCI_ControllerWorkTest(IN PXHCI_EXTENSION XhciExtension,
+                        IN PXHCI_HC_RESOURCES HcResourcesVA,
+                        IN PVOID resourcesStartPA)
+{
+    DPRINT1("XHCI_ControllerWorkTest: Initiated.\n");
+    PULONG DoorBellRegisterBase;
+    XHCI_DOORBELL Doorbell_0;
+    LARGE_INTEGER CurrentTime = {{0, 0}};
+    LARGE_INTEGER LastTime = {{0, 0}};
+    XHCI_USB_STATUS Status;
+    PHYSICAL_ADDRESS HcResourcesPA;
+    //PULONG erstba,erstdp;
+    //XHCI_EVENT_RING_SEGMENT_TABLE EventRingSegTable;
+   
+    XHCI_COMMAND_RING_CONTROL CommandRingControlRegister;
+    ULONGLONG CommandRingAddr;
+    ULONGLONG EventRingAddr;
+    XHCI_EVENT_RING_TABLE_SIZE erstz;
+    XHCI_EVENT_RING_TABLE_BASE_ADDR erstba;
+    XHCI_EVENT_RING_DEQUEUE_POINTER erstdp;
+    XHCI_EVENT_RING_SEGMENT_TABLE EventRingSegTable;
+    // place a no op command trb on the command ring
+    XHCI_TRB trb;
+    XHCI_TRB eventtrb;
+    trb.CommandTRB.NoOperation.RsvdZ1 = 0;
+    trb.CommandTRB.NoOperation.RsvdZ2 = 0;
+    trb.CommandTRB.NoOperation.RsvdZ3 = 0;
+    trb.CommandTRB.NoOperation.CycleBit = 0;
+    trb.CommandTRB.NoOperation.RsvdZ4 = 0;
+    trb.CommandTRB.NoOperation.TRBType = 8;
+    trb.CommandTRB.NoOperation.RsvdZ5 = 0;
+    
+    HcResourcesVA -> CommandRing.XhciTrb[0] = trb;
+    // ring the commmand ring door bell register
+    DoorBellRegisterBase = XhciExtension->DoorBellRegisterBase;
+    Doorbell_0.DoorBellTarget = 0;
+    Doorbell_0.RsvdZ = 0;
+    Doorbell_0.AsULONG = 0;
+    WRITE_REGISTER_ULONG(DoorBellRegisterBase, Doorbell_0.AsULONG);
+    // wait for some time.
+    KeQuerySystemTime(&CurrentTime);
+    CurrentTime.QuadPart += 100 * 100; // 100 msec
+    while(TRUE)
+    {
+        KeQuerySystemTime(&LastTime);
+        if (LastTime.QuadPart >= CurrentTime.QuadPart)
+        {
+            break;
+        }
+    }
+    // check for event completion trb
+    eventtrb =  HcResourcesVA -> EventRing.XhciTrb[0];
+    DPRINT("XHCI_ControllerWorkTest: eventtrb word0    - %p\n",
eventtrb.EventTRB.Word0);
+    DPRINT("XHCI_ControllerWorkTest: eventtrb word1    - %p\n",
eventtrb.EventTRB.Word1);
+    DPRINT("XHCI_ControllerWorkTest: eventtrb word2    - %p\n",
eventtrb.EventTRB.Word2);
+    DPRINT("XHCI_ControllerWorkTest: eventtrb word3    - %p\n",
eventtrb.EventTRB.Word3);
+    // status check code
+    Status.AsULONG = READ_REGISTER_ULONG(XhciExtension->OperationalRegs +
XHCI_USBSTS);
+    DPRINT("XHCI_ControllerWorkTest: Status HCHalted    - %p\n",
Status.HCHalted);
+    DPRINT("XHCI_ControllerWorkTest: Status HostSystemError    - %p\n",
Status.HostSystemError);
+    DPRINT("XHCI_ControllerWorkTest: Status EventInterrupt    - %p\n",
Status.EventInterrupt);
+    DPRINT("XHCI_ControllerWorkTest: Status PortChangeDetect    - %p\n",
Status.PortChangeDetect);
+    DPRINT("XHCI_ControllerWorkTest: Status ControllerNotReady    - %p\n",
Status.ControllerNotReady);
+    DPRINT("XHCI_ControllerWorkTest: Status HCError    - %p\n",
Status.HCError);
+    DPRINT("XHCI_ControllerWorkTest: Status     - %p\n", Status.AsULONG);
+    // command ring check
+    HcResourcesPA.QuadPart = (ULONG_PTR)resourcesStartPA;
+    CommandRingAddr = HcResourcesPA.QuadPart + FIELD_OFFSET(XHCI_HC_RESOURCES,
CommandRing.XhciTrb[0]);
+    DPRINT("XHCI_ControllerWorkTest: CommandRingAddr     - %x\n",
CommandRingAddr);
+    CommandRingControlRegister.AsULONGLONG =
READ_REGISTER_ULONG(XhciExtension->OperationalRegs + XHCI_CRCR+1) |
READ_REGISTER_ULONG(XhciExtension->OperationalRegs + XHCI_CRCR );
+    DPRINT("XHCI_ControllerWorkTest: CommandRingControlRegister     - %x\n",
CommandRingControlRegister.AsULONGLONG);
+        DPRINT("XHCI_ControllerWorkTest: CommandRingControlRegister1     -
%p\n", READ_REGISTER_ULONG(XhciExtension->OperationalRegs + XHCI_CRCR ));
+        DPRINT("XHCI_ControllerWorkTest: CommandRingControlRegister2     -
%p\n", READ_REGISTER_ULONG(XhciExtension->OperationalRegs + XHCI_CRCR + 1 ));
+    // event ring dprints
+    EventRingAddr = HcResourcesPA.QuadPart + FIELD_OFFSET(XHCI_HC_RESOURCES,
EventRing.XhciTrb[0]);
+    DPRINT("XHCI_ControllerWorkTest: EventRingSegTable.RingSegmentBaseAddr     -
%x\n", HcResourcesVA -> EventRingSegTable.RingSegmentBaseAddr);
+    DPRINT("XHCI_ControllerWorkTest: EventRingSegTable.RingSegmentSize     -
%i\n", HcResourcesVA -> EventRingSegTable.RingSegmentSize);
+    DPRINT("XHCI_ControllerWorkTest: event ring addr     - %x\n",
EventRingAddr);
+    //RunTimeRegisterBase + XHCI_ERSTSZ
+    erstz.AsULONG = READ_REGISTER_ULONG(XhciExtension->RunTimeRegisterBase +
XHCI_ERSTSZ) ;
+    DPRINT("XHCI_ControllerWorkTest: erstz     - %p\n", erstz.AsULONG);
+    
+    erstba.AsULONGLONG = HcResourcesPA.QuadPart + FIELD_OFFSET(XHCI_HC_RESOURCES,
EventRingSegTable);
+    DPRINT("XHCI_ControllerWorkTest: erstba addr     - %x\n",
erstba.AsULONGLONG);
+    erstba.AsULONGLONG = READ_REGISTER_ULONG(XhciExtension->RunTimeRegisterBase +
XHCI_ERSTBA+1) | READ_REGISTER_ULONG(XhciExtension->RunTimeRegisterBase + XHCI_ERSTBA
);
+    DPRINT("XHCI_ControllerWorkTest: erstba reg read     - %x\n",
erstba.AsULONGLONG);
+    
+    DPRINT("XHCI_ControllerWorkTest: pointer crcr     - %p %p\n",
XhciExtension->OperationalRegs + XHCI_CRCR+1 , XhciExtension->OperationalRegs +
XHCI_CRCR);
+    DPRINT("XHCI_ControllerWorkTest: pointer erstz     - %p\n",
XhciExtension->RunTimeRegisterBase + XHCI_ERSTSZ);
+    DPRINT("XHCI_ControllerWorkTest: pointer erstba     - %p %p\n",
XhciExtension->RunTimeRegisterBase + XHCI_ERSTBA+1 ,
XhciExtension->RunTimeRegisterBase + XHCI_ERSTBA);
+    
+    
+    DbgBreakPoint();
+    return MP_STATUS_SUCCESS;
+}
 MPSTATUS
 NTAPI
 XHCI_InitializeResources(IN PXHCI_EXTENSION XhciExtension,
@@ -53,6 +149,7 @@
                         IN PVOID resourcesStartPA)
 {
     DPRINT1("XHCI_InitializeResources: function initiated\n");
+    
     PXHCI_HC_RESOURCES HcResourcesVA;
     PHYSICAL_ADDRESS HcResourcesPA;
     PULONG BaseIoAdress;
@@ -67,7 +164,7 @@
     XHCI_EVENT_RING_DEQUEUE_POINTER erstdp;
     XHCI_EVENT_RING_SEGMENT_TABLE EventRingSegTable;
     
-    XHCI_COMMAND_RING_CONTROL CommandRingControlRegister;
+    XHCI_COMMAND_RING_CONTROL CommandRingControlRegister,
CommandRingControlRegister_temp;
     
     XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY_POINTER DCBAAPointer;
     unsigned long X, Y;
@@ -78,12 +175,12 @@
                 
     HcResourcesVA = (PXHCI_HC_RESOURCES)resourcesStartVA;
     HcResourcesPA.QuadPart = (ULONG_PTR)resourcesStartPA;
-    
+    BaseIoAdress = XhciExtension->BaseIoAdress;
+    OperationalRegs = XhciExtension->OperationalRegs;
     //DCBAA init
     DCBAAPointer.AsULONGLONG =  HcResourcesPA.QuadPart + FIELD_OFFSET(XHCI_HC_RESOURCES,
DCBAA);
     
-    BaseIoAdress = XhciExtension->BaseIoAdress;
-    OperationalRegs = XhciExtension->OperationalRegs;
+    
     
     WRITE_REGISTER_ULONG(OperationalRegs + XHCI_DCBAAP, DCBAAPointer.DCBAAPointerLo |
DCBAAPointer.RsvdZ );
     WRITE_REGISTER_ULONG(OperationalRegs + XHCI_DCBAAP + 1,
DCBAAPointer.DCBAAPointerHi);
@@ -94,7 +191,7 @@
     ASSERT(DCBAAPointer.RsvdZ == 0);
     
     // command ring intialisation.
-    
+    /*
     HcResourcesVA->CommandRing.Segment[0].Link[0].AsULONG = 0;
     HcResourcesVA->CommandRing.Segment[0].Link[1].AsULONG = 0;
     HcResourcesVA->CommandRing.Segment[0].Link[2].AsULONG = 0;
@@ -112,31 +209,62 @@
     
     WRITE_REGISTER_ULONG(OperationalRegs + XHCI_CRCR,
CommandRingControlRegister.AsULONGLONG);
     WRITE_REGISTER_ULONG(OperationalRegs + XHCI_CRCR + 1,
CommandRingControlRegister.CommandRingPointerHi);
+    */
     // end of command ring init
-    
+    // command ring intialisation.
+    for(int i=0; i<16; i++){
+        HcResourcesVA->CommandRing.XhciTrb[i].CommandTRB.GenericTRB.Word0=0;
+        HcResourcesVA->CommandRing.XhciTrb[i].CommandTRB.GenericTRB.Word1=0;
+        HcResourcesVA->CommandRing.XhciTrb[i].CommandTRB.GenericTRB.Word2=0;
+        HcResourcesVA->CommandRing.XhciTrb[i].CommandTRB.GenericTRB.Word3=0;
+    }
+    CommandRingControlRegister.AsULONGLONG = HcResourcesPA.QuadPart +
FIELD_OFFSET(XHCI_HC_RESOURCES, CommandRing.XhciTrb[0]);
+    ASSERT(CommandRingControlRegister.RingCycleState == 0);
+    ASSERT(CommandRingControlRegister.CommandStop == 0);
+    ASSERT(CommandRingControlRegister.CommandAbort == 0);
+    ASSERT(CommandRingControlRegister.CommandRingRunning == 0);
+    //ASSERT(CommandRingControlRegister.RsvdP == 0);
+    CommandRingControlRegister_temp.AsULONGLONG = READ_REGISTER_ULONG(OperationalRegs +
XHCI_CRCR + 1) |  READ_REGISTER_ULONG(OperationalRegs + XHCI_CRCR);
+    
+    CommandRingControlRegister.RsvdP = CommandRingControlRegister_temp.RsvdP;
+    DPRINT1("XHCI_InitializeResources  : CommandRingControlRegister  
%p\n",CommandRingControlRegister.AsULONGLONG );
+    WRITE_REGISTER_ULONG(OperationalRegs + XHCI_CRCR,
CommandRingControlRegister.AsULONGLONG);
+    WRITE_REGISTER_ULONG(OperationalRegs + XHCI_CRCR + 1,
CommandRingControlRegister.AsULONGLONG >> 32);
+    // end of command ring init
     //Primary Interrupter init
     RunTimeRegisterBase =  XhciExtension -> RunTimeRegisterBase;
     
-    Iman.InterruptEnable = 1;
-    WRITE_REGISTER_ULONG (RunTimeRegisterBase + XHCI_IMAN , Iman.AsULONG);
-    
     // dont change imod now
+    erstz.AsULONG = READ_REGISTER_ULONG(RunTimeRegisterBase + XHCI_ERSTSZ) ;
     erstz.EventRingSegTableSize = 1;
+    DPRINT1("XHCI_InitializeResources  : erstz.AsULONG   %p\n",erstz.AsULONG
);
     WRITE_REGISTER_ULONG (RunTimeRegisterBase + XHCI_ERSTSZ , erstz.AsULONG);
+    // event ring dequeue pointer.
+    erstdp.AsULONGLONG = HcResourcesPA.QuadPart + FIELD_OFFSET(XHCI_HC_RESOURCES,
EventRing);
+    erstdp.DequeueERSTIndex =0;
+    DPRINT1("XHCI_InitializeResources  : erstdp.AsULONGLONG  
%p\n",erstdp.AsULONGLONG );
+    WRITE_REGISTER_ULONG (RunTimeRegisterBase + XHCI_ERSTDP, erstdp.AsULONGLONG);
+    WRITE_REGISTER_ULONG (RunTimeRegisterBase + XHCI_ERSTDP + 1, erstdp.AsULONGLONG
>> 32);
+    // event ring segment table base address array
     
     erstba.AsULONGLONG = HcResourcesPA.QuadPart + FIELD_OFFSET(XHCI_HC_RESOURCES,
EventRingSegTable);
-    
-    EventRingSegTable.RingSegmentBaseAddr = HcResourcesPA.QuadPart +
FIELD_OFFSET(XHCI_HC_RESOURCES, EventRing);
+    EventRingSegTable.RingSegmentBaseAddr = (ULONGLONG)HcResourcesPA.QuadPart +
FIELD_OFFSET(XHCI_HC_RESOURCES, EventRing.XhciTrb[0]);
+    //EventRingSegTable.RingSegmentBaseAddr = &(HcResourcesVA ->
EventRing.XhciTrb[0]);
     EventRingSegTable.RingSegmentSize = 16;
+    EventRingSegTable.RsvdZ = 0;
     HcResourcesVA->EventRingSegTable = EventRingSegTable;
-    
+    DPRINT1("XHCI_InitializeResources  : erstba.AsULONGLONG  
%p\n",erstba.AsULONGLONG );
     WRITE_REGISTER_ULONG (RunTimeRegisterBase + XHCI_ERSTBA, erstba.AsULONGLONG);
     WRITE_REGISTER_ULONG (RunTimeRegisterBase + XHCI_ERSTBA + 1, erstba.AsULONGLONG
>> 32);
     // intially enque and deque are equal. 
-    erstdp.AsULONGLONG = HcResourcesPA.QuadPart + FIELD_OFFSET(XHCI_HC_RESOURCES,
EventRing);
-    erstdp.DequeueERSTIndex =0;
-    WRITE_REGISTER_ULONG (RunTimeRegisterBase + XHCI_ERSTDP, erstdp.AsULONGLONG);
-    WRITE_REGISTER_ULONG (RunTimeRegisterBase + XHCI_ERSTDP + 1, erstdp.AsULONGLONG
>> 32);
+    
+    
+    for(int i=0; i<16; i++){
+        HcResourcesVA->EventRing.XhciTrb[i].EventTRB.Word0=0;
+        HcResourcesVA->EventRing.XhciTrb[i].EventTRB.Word1=0;
+        HcResourcesVA->EventRing.XhciTrb[i].EventTRB.Word2=0;
+        HcResourcesVA->EventRing.XhciTrb[i].EventTRB.Word3=0;
+    }
     
     //DbgBreakPoint();
     return MP_STATUS_SUCCESS;
@@ -218,8 +346,11 @@
     PXHCI_EXTENSION XhciExtension;
     PULONG BaseIoAdress;
     PULONG OperationalRegs;
-    PULONG  RunTimeRegisterBase;
-    
+    PULONG RunTimeRegisterBase;
+    PULONG DoorBellRegisterBase;
+    XHCI_CAPLENGHT_INTERFACE_VERSION CapLenReg;
+    
+    XHCI_DOORBELL_OFFSET DoorBellOffsetRegister;
     MPSTATUS MPStatus;
     XHCI_USB_COMMAND Command;
     XHCI_RT_REGISTER_SPACE_OFFSET RTSOffsetRegister;
@@ -241,17 +372,25 @@
     BaseIoAdress = (PULONG)Resources->ResourceBase;
     XhciExtension->BaseIoAdress = BaseIoAdress;
 
-    CapabilityRegLength = (UCHAR)READ_REGISTER_ULONG(BaseIoAdress);
+    CapLenReg.AsULONG = READ_REGISTER_ULONG(BaseIoAdress);
+    CapLenReg.Rsvd=0;
+    CapLenReg.HostControllerInterfaceVersion=0;
+    CapabilityRegLength= (UCHAR)CapLenReg.CapabilityRegistersLength ;
     OperationalRegs = (PULONG)((ULONG_PTR)BaseIoAdress + CapabilityRegLength);
     XhciExtension->OperationalRegs = OperationalRegs;
-     
+    
+    DoorBellOffsetRegister.AsULONG = READ_REGISTER_ULONG(BaseIoAdress + XHCI_DBOFF);
+    DoorBellRegisterBase = (PULONG)((PBYTE)BaseIoAdress + DoorBellOffsetRegister.AsULONG
);
+    XhciExtension->DoorBellRegisterBase = DoorBellRegisterBase;
+    
     RTSOffsetRegister.AsULONG = READ_REGISTER_ULONG(BaseIoAdress + XHCI_RTSOFF);
-    RunTimeRegisterBase = BaseIoAdress + RTSOffsetRegister.AsULONG ;
-
-    XhciExtension->RunTimeRegisterBase = RunTimeRegisterBase;
+    RunTimeRegisterBase = (PULONG)((PBYTE)BaseIoAdress + RTSOffsetRegister.AsULONG );
+    XhciExtension->RunTimeRegisterBase = RunTimeRegisterBase ;
     
     DPRINT("XHCI_StartController: BaseIoAdress    - %p\n", BaseIoAdress);
     DPRINT("XHCI_StartController: OperationalRegs - %p\n", OperationalRegs);
+    DPRINT("XHCI_StartController: DoorBellRegisterBase - %p\n",
DoorBellRegisterBase);
+    DPRINT("XHCI_StartController: RunTimeRegisterBase - %p\n",
RunTimeRegisterBase);
     
     RegPacket.UsbPortReadWriteConfigSpace(XhciExtension,
                                           1,
@@ -279,11 +418,15 @@
         return MPStatus;
     }
     
+    Command.AsULONG = READ_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD);
     Command.RunStop =1;
     WRITE_REGISTER_ULONG (OperationalRegs + XHCI_USBCMD, Command.AsULONG );
+    
+    MPStatus = XHCI_ControllerWorkTest(XhciExtension,Resources->StartVA,
Resources->StartPA );
     //DPRINT1("XHCI_StartController: UNIMPLEMENTED. FIXME\n");
     return MP_STATUS_SUCCESS;
 }
+
 
 VOID
 NTAPI
@@ -474,15 +617,22 @@
     DPRINT1("XHCI_EnableInterrupts: function initiated\n");
     PXHCI_EXTENSION XhciExtension;
     PULONG OperationalRegs;
+    PULONG  RunTimeRegisterBase;
+    XHCI_INTERRUPTER_MANAGEMENT Iman;
     XHCI_USB_COMMAND usbCommand;
-   
+    
+    
     XhciExtension = (PXHCI_EXTENSION)xhciExtension;
     OperationalRegs = XhciExtension->OperationalRegs;
-    usbCommand.AsULONG =READ_REGISTER_ULONG (OperationalRegs + XHCI_USBCMD);
+    //usbCommand.AsULONG =READ_REGISTER_ULONG (OperationalRegs + XHCI_USBCMD);
+    RunTimeRegisterBase =  XhciExtension -> RunTimeRegisterBase;
+    Iman.AsULONG = READ_REGISTER_ULONG(RunTimeRegisterBase + XHCI_IMAN) ;
+    Iman.InterruptEnable = 1;
+    WRITE_REGISTER_ULONG (RunTimeRegisterBase + XHCI_IMAN , Iman.AsULONG);
+    
+    //usbCommand.InterrupterEnable = 1;
    
-    usbCommand.InterrupterEnable = 1;
-   
-    WRITE_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD,usbCommand.AsULONG );
+    //WRITE_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD,usbCommand.AsULONG );
      DPRINT1("XHCI_EnableInterrupts: Interrupts enabled\n");
 }
 

Modified: branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.h
URL:
http://svn.reactos.org/svn/reactos/branches/GSoC_2017/usbxhci/reactos/drive…
==============================================================================
--- branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.h	[iso-8859-1]
(original)
+++ branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.h	[iso-8859-1] Thu Jul
13 06:53:28 2017
@@ -42,29 +42,30 @@
     };
     ULONG AsULONG;
 } XHCI_LINK_TRB;
+//----------------------------------------generic
trb----------------------------------------------------------------
+typedef struct _XHCI_GENERIC_TRB {
+    ULONG Word0;
+    ULONG Word1;
+    ULONG Word2;
+    ULONG Word3;
+}XHCI_GENERIC_TRB, *PXHCI_GENERIC_TRB;
 //----------------------------------------Command
TRBs----------------------------------------------------------------
-typedef union _XHCI_COMMAND_NO_OP_TRB {
-    struct {
-        ULONG RsvdZ1                     : 5;
-    };
-    struct {
-        ULONG RsvdZ2                     : 5;
-    };
-    struct {
-        ULONG RsvdZ3                     : 5;
-    };
-    struct {
-        ULONG CycleBit                  : 1;
-        ULONG RsvdZ4                    : 4;
-        ULONG TRBType                   : 6;
-        ULONG RsvdZ5                    : 14;
-    };
-    ULONG AsULONG;
+typedef struct _XHCI_COMMAND_NO_OP_TRB {
+        ULONG RsvdZ1;
+        ULONG RsvdZ2;
+        ULONG RsvdZ3;
+        struct{
+            ULONG CycleBit                  : 1;
+            ULONG RsvdZ4                    : 4;
+            ULONG TRBType                   : 6;
+            ULONG RsvdZ5                    : 14;
+        };
 } XHCI_COMMAND_NO_OP_TRB;
 
 typedef union _XHCI_COMMAND_TRB {
-    XHCI_COMMAND_NO_OP_TRB NoOperation[4];
+    XHCI_COMMAND_NO_OP_TRB NoOperation;
     XHCI_LINK_TRB Link[4];
+    XHCI_GENERIC_TRB GenericTRB;
 }XHCI_COMMAND_TRB, *PXHCI_COMMAND_TRB;
 
 typedef struct _XHCI_COMMAND_RING {
@@ -170,8 +171,11 @@
 
 typedef struct _XHCI_EVENT_RING_SEGMENT_TABLE{
     ULONGLONG RingSegmentBaseAddr;
-    ULONGLONG RingSegmentSize : 16;
-    ULONGLONG RsvdZ           :  48;
+    struct {
+        ULONGLONG RingSegmentSize : 16;
+        ULONGLONG RsvdZ           :  48;
+    };
+    
     
 } XHCI_EVENT_RING_SEGMENT_TABLE;
 //------------------------------------main structs-----------------------
@@ -184,7 +188,7 @@
 } XHCI_TRB, *PXHCI_TRB;
 
 typedef struct _XHCI_RING {
-    XHCI_TRB ring[16];
+    XHCI_TRB XhciTrb[16];
     //PXHCI_TRB dequeue_pointer;
 }XHCI_RING , *PXHCI_RING;
 
@@ -194,6 +198,7 @@
   PULONG BaseIoAdress;
   PULONG OperationalRegs;
   PULONG RunTimeRegisterBase;
+  PULONG DoorBellRegisterBase;
   UCHAR FrameLengthAdjustment;
   BOOLEAN IsStarted;
   USHORT HcSystemErrors;
@@ -205,8 +210,9 @@
 
 typedef struct _XHCI_HC_RESOURCES {
   XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY DCBAA;
-  XHCI_COMMAND_RING CommandRing;
+  //XHCI_COMMAND_RING CommandRing;
   XHCI_RING         EventRing;
+  XHCI_RING         CommandRing;
   XHCI_EVENT_RING_SEGMENT_TABLE EventRingSegTable;
 } XHCI_HC_RESOURCES, *PXHCI_HC_RESOURCES;