[ros-diffs] [aandrejevic] 59269: [NTVDM] Make sure bit 2 in the ISR of the master PIC is set when an IRQ in the slave PIC occurs.

Author: aandrejevic
Date: Thu Jun 20 19:43:29 2013
New Revision: 59269

URL: http://svn.reactos.org/svn/reactos?rev=59269&view=rev
Log:
[NTVDM]
Make sure bit 2 in the ISR of the master PIC is set when an IRQ in the slave PIC occurs.


Modified:
    branches/ntvdm/subsystems/ntvdm/hardware.c

Modified: branches/ntvdm/subsystems/ntvdm/hardware.c
URL:
http://svn.reactos.org/svn/reactos/branches/ntvdm/subsystems/ntvdm/hardware…
==============================================================================
--- branches/ntvdm/subsystems/ntvdm/hardware.c	[iso-8859-1] (original)
+++ branches/ntvdm/subsystems/ntvdm/hardware.c	[iso-8859-1] Thu Jun 20 19:43:29 2013
@@ -188,6 +188,12 @@
         {
             return;
         }
+
+        /* Check the if the slave PIC is busy */
+        if (MasterPic.InServiceRegister & (1 << 2)) return;
+
+        /* Set the IRQ 2 bit in the master ISR */
+        MasterPic.InServiceRegister |= 1 << 2;
         
         /* Check if the interrupt is busy or in a cascade */
         if (SlavePic.CascadeRegister & (1 << Number)