[ros-diffs] [reactos] 02/02: [FREELDR][HALXBOX] Initialize PCI bridge secondary & subordinate bus values

[Stanislav Motylkov]

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=dcc1506af5c90bbdfdc35…

commit dcc1506af5c90bbdfdc35b0726c54fcb96fb951b
Author:     Stanislav Motylkov <x86corez(a)gmail.com>
AuthorDate: Mon May 24 18:06:17 2021 +0300
Commit:     Stanislav Motylkov <x86corez(a)gmail.com>
CommitDate: Mon May 24 18:12:02 2021 +0300

    [FREELDR][HALXBOX] Initialize PCI bridge secondary & subordinate bus values
    
    This fixes the recursion when pci.sys attempts to get PCI bridge children
    devices, which in fact are non-existing.
    
    Note that the problem in pci.sys itself also deserves a separate fix.
    
    CORE-16319 CORE-16216
---
 boot/freeldr/freeldr/arch/i386/xbox/xboxmem.c | 36 +++++++++++++++++++++++++++
 hal/halx86/legacy/bus/pcibus.c                |  7 ------
 2 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/boot/freeldr/freeldr/arch/i386/xbox/xboxmem.c
b/boot/freeldr/freeldr/arch/i386/xbox/xboxmem.c
index 2f59f04278b..eb7ce22c232 100644
--- a/boot/freeldr/freeldr/arch/i386/xbox/xboxmem.c
+++ b/boot/freeldr/freeldr/arch/i386/xbox/xboxmem.c
@@ -54,6 +54,40 @@ extern ULONG
 PcMemFinalizeMemoryMap(
     PFREELDR_MEMORY_DESCRIPTOR MemoryMap);
 
+static
+VOID
+XboxInitializePCI(VOID)
+{
+    PCI_TYPE1_CFG_BITS PciCfg1;
+    ULONG PciData;
+
+    /* Select PCI to PCI bridge */
+    PciCfg1.u.bits.Enable = 1;
+    PciCfg1.u.bits.BusNumber = 0;
+    PciCfg1.u.bits.DeviceNumber = 8;
+    PciCfg1.u.bits.FunctionNumber = 0;
+    /* Select register VendorID & DeviceID */
+    PciCfg1.u.bits.RegisterNumber = 0x00;
+    PciCfg1.u.bits.Reserved = 0;
+
+    WRITE_PORT_ULONG(PCI_TYPE1_ADDRESS_PORT, PciCfg1.u.AsULONG);
+    PciData = READ_PORT_ULONG((PULONG)PCI_TYPE1_DATA_PORT);
+
+    if (PciData == 0x01B810DE)
+    {
+        /* Select register PrimaryBus/SecondaryBus/SubordinateBus/SecondaryLatency */
+        PciCfg1.u.bits.RegisterNumber = 0x18;
+        WRITE_PORT_ULONG(PCI_TYPE1_ADDRESS_PORT, PciCfg1.u.AsULONG);
+
+        /* Link uninitialized PCI bridge to the empty PCI bus 2,
+         * it's not supposed to have any devices attached anyway */
+        PciData = READ_PORT_ULONG((PULONG)PCI_TYPE1_DATA_PORT);
+        PciData &= 0xFF0000FF;
+        PciData |= 0x00020200;
+        WRITE_PORT_ULONG((PULONG)PCI_TYPE1_DATA_PORT, PciData);
+    }
+}
+
 VOID
 XboxMemInit(VOID)
 {
@@ -108,6 +142,8 @@ XboxMemInit(VOID)
     WRITE_PORT_ULONG((PULONG)PCI_TYPE1_DATA_PORT, InstalledMemoryMb * 1024 * 1024 - 1);
 
     AvailableMemoryMb = InstalledMemoryMb;
+
+    XboxInitializePCI();
 }
 
 memory_map_t *
diff --git a/hal/halx86/legacy/bus/pcibus.c b/hal/halx86/legacy/bus/pcibus.c
index ee5ff34a28c..b4c0bd070df 100644
--- a/hal/halx86/legacy/bus/pcibus.c
+++ b/hal/halx86/legacy/bus/pcibus.c
@@ -322,13 +322,6 @@ HalpXboxBlacklistedPCISlot(IN PBUS_HANDLER BusHandler,
         return TRUE;
     }
 
-    /* Temporary hack to avoid stack overflow in kernel, see CORE-16319 */
-    if (BusHandler->BusNumber == 0 && Slot.u.bits.DeviceNumber == 8 &&
Slot.u.bits.FunctionNumber == 0)
-    {
-        DPRINT("Blacklisted PCI-to-PCI bridge (00:08.0 - PCI\\VEN_10DE&DEV_01B8,
see CORE-16319)\n");
-        return TRUE;
-    }
-
     return FALSE;
 }
 #endif