[ros-diffs] [tkreuzer] 44067: [MM] - Fix MiAddressToP*e macros - move miarm constants - set MmPfnDatabase address - fix PageCount for pfn database mapping (round up)

Author: tkreuzer
Date: Tue Nov 10 01:54:46 2009
New Revision: 44067

URL: http://svn.reactos.org/svn/reactos?rev=44067&view=rev
Log:
[MM]
- Fix MiAddressToP*e macros
- move miarm constants
- set MmPfnDatabase address
- fix PageCount for pfn database mapping (round up)

Modified:
    branches/ros-amd64-bringup/reactos/ntoskrnl/include/internal/amd64/mm.h
    branches/ros-amd64-bringup/reactos/ntoskrnl/mm/ARM3/miarm.h
    branches/ros-amd64-bringup/reactos/ntoskrnl/mm/amd64/init.c

Modified: branches/ros-amd64-bringup/reactos/ntoskrnl/include/internal/amd64/mm.h
URL:
http://svn.reactos.org/svn/reactos/branches/ros-amd64-bringup/reactos/ntosk…
==============================================================================
--- branches/ros-amd64-bringup/reactos/ntoskrnl/include/internal/amd64/mm.h [iso-8859-1]
(original)
+++ branches/ros-amd64-bringup/reactos/ntoskrnl/include/internal/amd64/mm.h [iso-8859-1]
Tue Nov 10 01:54:46 2009
@@ -26,13 +26,13 @@
 
 /* Converting address to a corresponding PDE or PTE entry */
 #define MiAddressToPxe(x) \
-    ((PMMPTE)(((((ULONG64)(x)) >> PXI_SHIFT) << 3) + PXE_BASE))
+    ((PMMPTE)((((((ULONG64)(x)) >> PXI_SHIFT) & PXI_MASK) << 3) +
PXE_BASE))
 #define MiAddressToPpe(x) \
-    ((PMMPTE)(((((ULONG64)(x)) >> PPI_SHIFT) << 3) + PPE_BASE))
+    ((PMMPTE)((((((ULONG64)(x)) >> PPI_SHIFT) & PPI_MASK) << 3) +
PPE_BASE))
 #define MiAddressToPde(x) \
-    ((PMMPTE)(((((ULONG64)(x)) >> PDI_SHIFT) << 3) + PDE_BASE))
+    ((PMMPTE)((((((ULONG64)(x)) >> PDI_SHIFT) & PDI_MASK_AMD64) << 3) +
PDE_BASE))
 #define MiAddressToPte(x) \
-    ((PMMPTE)(((((ULONG64)(x)) >> PTI_SHIFT) << 3) + PTE_BASE))
+    ((PMMPTE)((((((ULONG64)(x)) >> PTI_SHIFT) & PTI_MASK_AMD64) << 3) +
PTE_BASE))
 
 /* Convert a PTE into a corresponding address */
 #define MiPteToAddress(PTE) ((PVOID)((ULONG64)(PTE) << 9))
@@ -46,6 +46,7 @@
 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
 #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
 
+/// MIARM.H 
 
 /* Easy accessing PFN in PTE */
 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
@@ -62,4 +63,39 @@
 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Write = 1)
 
+
+#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
+#define MI_MIN_PAGES_FOR_SYSPTE_TUNING         ((19*1024*1024) >> PAGE_SHIFT)
+#define MI_MIN_PAGES_FOR_SYSPTE_BOOST          ((32*1024*1024) >> PAGE_SHIFT)
+#define MI_MAX_INIT_NONPAGED_POOL_SIZE         (128 * 1024 * 1024)
+#define MI_MAX_NONPAGED_POOL_SIZE              (128 * 1024 * 1024)
+#define MI_MAX_FREE_PAGE_LISTS                 4
+
+#define MI_MIN_INIT_PAGED_POOLSIZE             (32 * 1024 * 1024)
+
+#define MI_SESSION_VIEW_SIZE                   (20 * 1024 * 1024)
+#define MI_SESSION_POOL_SIZE                   (16 * 1024 * 1024)
+#define MI_SESSION_IMAGE_SIZE                  (8 * 1024 * 1024)
+#define MI_SESSION_WORKING_SET_SIZE            (4 * 1024 * 1024)
+#define MI_SESSION_SIZE                        (MI_SESSION_VIEW_SIZE + \
+                                                MI_SESSION_POOL_SIZE + \
+                                                MI_SESSION_IMAGE_SIZE + \
+                                                MI_SESSION_WORKING_SET_SIZE)
+
+#define MI_SYSTEM_VIEW_SIZE                    (16 * 1024 * 1024)
+
+#define MI_PAGED_POOL_START                    (PVOID)0xFFFFFA8000000000ULL
+#define MI_NONPAGED_POOL_END                   (PVOID)0xFFFFFAE000000000ULL
+
+#define MM_HIGHEST_VAD_ADDRESS \
+    (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
+
+
+//
+// FIXFIX: These should go in ex.h after the pool merge
+//
+#define POOL_LISTS_PER_PAGE (PAGE_SIZE / sizeof(LIST_ENTRY))
+#define BASE_POOL_TYPE_MASK 1
+#define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + sizeof(LIST_ENTRY)))
+
 #endif /* __NTOSKRNL_INCLUDE_INTERNAL_AMD64_MM_H */

Modified: branches/ros-amd64-bringup/reactos/ntoskrnl/mm/ARM3/miarm.h
URL:
http://svn.reactos.org/svn/reactos/branches/ros-amd64-bringup/reactos/ntosk…
==============================================================================
--- branches/ros-amd64-bringup/reactos/ntoskrnl/mm/ARM3/miarm.h [iso-8859-1] (original)
+++ branches/ros-amd64-bringup/reactos/ntoskrnl/mm/ARM3/miarm.h [iso-8859-1] Tue Nov 10
01:54:46 2009
@@ -6,43 +6,7 @@
  * PROGRAMMERS:     ReactOS Portable Systems Group
  */
 
-#ifdef _M_AMD64
-
-#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
-#define MI_MIN_PAGES_FOR_SYSPTE_TUNING         ((19*1024*1024) >> PAGE_SHIFT)
-#define MI_MIN_PAGES_FOR_SYSPTE_BOOST          ((32*1024*1024) >> PAGE_SHIFT)
-#define MI_MAX_INIT_NONPAGED_POOL_SIZE         (128 * 1024 * 1024)
-#define MI_MAX_NONPAGED_POOL_SIZE              (128 * 1024 * 1024)
-#define MI_MAX_FREE_PAGE_LISTS                 4
-
-#define MI_MIN_INIT_PAGED_POOLSIZE             (32 * 1024 * 1024)
-
-#define MI_SESSION_VIEW_SIZE                   (20 * 1024 * 1024)
-#define MI_SESSION_POOL_SIZE                   (16 * 1024 * 1024)
-#define MI_SESSION_IMAGE_SIZE                  (8 * 1024 * 1024)
-#define MI_SESSION_WORKING_SET_SIZE            (4 * 1024 * 1024)
-#define MI_SESSION_SIZE                        (MI_SESSION_VIEW_SIZE + \
-                                                MI_SESSION_POOL_SIZE + \
-                                                MI_SESSION_IMAGE_SIZE + \
-                                                MI_SESSION_WORKING_SET_SIZE)
-
-#define MI_SYSTEM_VIEW_SIZE                    (16 * 1024 * 1024)
-
-#define MI_PAGED_POOL_START                    (PVOID)0xFFFFFA8000000000ULL
-#define MI_NONPAGED_POOL_END                   (PVOID)0xFFFFFAE000000000ULL
-
-#define MM_HIGHEST_VAD_ADDRESS \
-    (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
-
-
-//
-// FIXFIX: These should go in ex.h after the pool merge
-//
-#define POOL_LISTS_PER_PAGE (PAGE_SIZE / sizeof(LIST_ENTRY))
-#define BASE_POOL_TYPE_MASK 1
-#define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + sizeof(LIST_ENTRY)))
-
-#else
+#ifndef _M_AMD64
 
 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING         ((19*1024*1024) >> PAGE_SHIFT)

Modified: branches/ros-amd64-bringup/reactos/ntoskrnl/mm/amd64/init.c
URL:
http://svn.reactos.org/svn/reactos/branches/ros-amd64-bringup/reactos/ntosk…
==============================================================================
--- branches/ros-amd64-bringup/reactos/ntoskrnl/mm/amd64/init.c [iso-8859-1] (original)
+++ branches/ros-amd64-bringup/reactos/ntoskrnl/mm/amd64/init.c [iso-8859-1] Tue Nov 10
01:54:46 2009
@@ -238,6 +238,9 @@
     /* Use the default */
     MmNumberOfSystemPtes = 22000;
 
+    /* FIXME: should start below paged pool */
+    MmPfnDatabase = (PVOID)0xFFFFFD5FC0000000ULL;
+
 }
 
 VOID
@@ -307,9 +310,10 @@
             /* Update the highest page */
             MmHighestPhysicalPage = LastPage;
         }
-
+DPRINT1("BasePage = %ld, LastPage = %ld\n", BasePage, LastPage);
+__debugbreak();
         /* Map pages for the PFN database */
-        PageCount = (MdBlock->PageCount * sizeof(MMPFN)) / PAGE_SIZE;
+        PageCount = PAGE_ROUND_UP(MdBlock->PageCount * sizeof(MMPFN)) / PAGE_SIZE;
         MxMapPageRange(&MmPfnDatabase[BasePage], PageCount);
 
         /* Zero out the pages */
@@ -444,14 +448,11 @@
 
         /* Initialize the memory layout */
         MiArmIninializeMemoryLayout(LoaderBlock);
-        DPRINT1("MmArmInitSystem 3\n");
 
         /* Loop descriptors and prepare PFN database */
         MiArmEvaluateMemoryDescriptors(LoaderBlock);
-        DPRINT1("MmArmInitSystem 4\n");
 
         MiArmInitializePageTable();
-        DPRINT1("MmArmInitSystem 5\n");
 
         /* Configure size of the non paged pool */
         MiArmPrepareNonPagedPool();