[ros-diffs] [reactos] 01/01: [HAL] HalpDebugPciDumpBus: Print details about PCI bridges

[Stanislav Motylkov]

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=b232efe12a41615c59232…

commit b232efe12a41615c59232aa14d2d3484ad1c2b04
Author:     Stanislav Motylkov <x86corez(a)gmail.com>
AuthorDate: Sun May 23 15:48:21 2021 +0300
Commit:     Stanislav Motylkov <x86corez(a)gmail.com>
CommitDate: Sun May 23 15:48:21 2021 +0300

    [HAL] HalpDebugPciDumpBus: Print details about PCI bridges
    
    CORE-16319 CORE-16216
---
 hal/halx86/legacy/bussupp.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/hal/halx86/legacy/bussupp.c b/hal/halx86/legacy/bussupp.c
index 65a9e5c8e1c..4b855ec596e 100644
--- a/hal/halx86/legacy/bussupp.c
+++ b/hal/halx86/legacy/bussupp.c
@@ -929,6 +929,17 @@ HalpDebugPciDumpBus(IN ULONG i,
     else if (PciData->u.type0.InterruptPin != 0) DbgPrint(", IRQ assignment
required");
     DbgPrint("\n");
 
+    if ((PciData->HeaderType & ~PCI_MULTIFUNCTION) == PCI_BRIDGE_TYPE &&
+        PciData->BaseClass == PCI_CLASS_BRIDGE_DEV)
+    {
+        DbgPrint("\tBridge:");
+        DbgPrint(" primary bus %d,", PciData->u.type1.PrimaryBus);
+        DbgPrint(" secondary bus %d,", PciData->u.type1.SecondaryBus);
+        DbgPrint(" subordinate bus %d,", PciData->u.type1.SubordinateBus);
+        DbgPrint(" secondary latency %d",
PciData->u.type1.SecondaryLatency);
+        DbgPrint("\n");
+    }
+
     /* Scan addresses */
     Size = 0;
     for (b = 0; b < PCI_TYPE0_ADDRESSES; b++)