Author: rgampa Date: Mon Jun 26 06:14:59 2017 New Revision: 75200
URL: http://svn.reactos.org/svn/reactos?rev=75200&view=rev Log: [USBXHCI] -defined TRBs for command and control -allocated resources to the driver. -intiated command ring -intiated DCBAA -changed XHCI_InitializeSchedule function to XHCI_InitializeResources. CORE-13344
Modified: branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/hardware.h branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.c branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.h
Modified: branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/hardware.h URL: http://svn.reactos.org/svn/reactos/branches/GSoC_2017/usbxhci/reactos/driver... ============================================================================== --- branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/hardware.h [iso-8859-1] (original) +++ branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/hardware.h [iso-8859-1] Mon Jun 26 06:14:59 2017 @@ -14,12 +14,14 @@ #define XHCI_DCBAAP 12 #define XHCI_CONFIG 14
+typedef unsigned long long ULONGULONG ; + typedef union _XHCI_HC_STRUCTURAL_PARAMS_1 { struct { - ULONG NumberOfDeviceSlots : 8; - ULONG NumberOfInterrupters : 11; + ULONG NumberOfDeviceSlots : 8; // MAXSLOTS + ULONG NumberOfInterrupters : 11; // MAXINTRS ULONG Rsvd : 5; - ULONG NumberOfPorts : 8; + ULONG NumberOfPorts : 8; //MAXPORTS }; ULONG AsULONG; } XHCI_HC_STRUCTURAL_PARAMS_1; @@ -149,10 +151,10 @@
typedef union _XHCI_CONFIGURE { struct { - ULONG MaxDeviceSlot : 8; - ULONG U3E : 1; - ULONG CIE : 1; - ULONG Rsvd : 21; + ULONG MaxDeviceSlotsEnabled : 8; + ULONG U3EntryEnable : 1; + ULONG ConfigurationInfoEnable : 1; + ULONG Rsvd : 21; }; ULONG AsULONG; } XHCI_CONFIGURE; @@ -187,25 +189,25 @@ ULONG AsULONG; } XHCI_PORT_STATUS_CONTROL;
-typedef union _XHCI_COMMAND_RING_CONTROL { //typedef ulongulong for better readability - struct { - unsigned long long RCS : 1; - unsigned long long CS : 1; - unsigned long long CA : 1; - unsigned long long CRR : 1; - unsigned long long Rsvd : 2; - unsigned long long CommandRingPointerLo : 26; - unsigned long long CommandRingPointerHi : 32; - }; - unsigned long long AsULONGULONG; +typedef union _XHCI_COMMAND_RING_CONTROL { + struct { + ULONGULONG RingCycleState : 1; + ULONGULONG CommandStop : 1; + ULONGULONG CommandAbort : 1; + ULONGULONG CommandRingRunning : 1; + ULONGULONG RsvdP : 2; + ULONGULONG CommandRingPointerLo : 26; + ULONGULONG CommandRingPointerHi : 32; + }; + ULONGULONG AsULONGULONG; } XHCI_COMMAND_RING_CONTROL;
-typedef union _XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY { - struct { - unsigned long long Rsvd : 6; - unsigned long long DCBAALo : 26; - unsigned long long DCBAAHi : 32; - }; - unsigned long long AsULONGULONG; -} XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY; - +typedef union _XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY_POINTER { + struct { + ULONGULONG RsvdZ : 6; + ULONGULONG DCBAAPointerLo : 26; + ULONGULONG DCBAAPointerHi : 32; + }; + ULONGULONG AsULONGULONG; +} XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY_POINTER; +
Modified: branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.c URL: http://svn.reactos.org/svn/reactos/branches/GSoC_2017/usbxhci/reactos/driver... ============================================================================== --- branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.c [iso-8859-1] (original) +++ branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.c [iso-8859-1] Mon Jun 26 06:14:59 2017 @@ -46,10 +46,59 @@
MPSTATUS NTAPI -XHCI_InitializeSchedule(IN PXHCI_EXTENSION XhciExtension, +XHCI_InitializeResources(IN PXHCI_EXTENSION XhciExtension, IN PVOID resourcesStartVA, IN PVOID resourcesStartPA) { + PXHCI_HC_RESOURCES HcResourcesVA; + PHYSICAL_ADDRESS HcResourcesPA; + + XHCI_COMMAND_RING_CONTROL CommandRingControlRegister; + + XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY_POINTER DCBAAPointer; + PULONG OperationalRegs; + unsigned long X, Y; + + DPRINT_XHCI("XHCI_InitializeResources: BaseVA - %p, BasePA - %p\n", + resourcesStartVA, + resourcesStartPA); + + HcResourcesVA = (PXHCI_HC_RESOURCES)resourcesStartVA; + HcResourcesPA.QuadPart = (ULONG_PTR)resourcesStartPA; + + DCBAAPointer.AsULONGULONG = HcResourcesPA.QuadPart + FIELD_OFFSET(XHCI_HC_RESOURCES, DCBAA); + + OperationalRegs = XhciExtension->OperationalRegs; + //DCBAAPointer.RsvdZ =0; + WRITE_REGISTER_ULONG(OperationalRegs + XHCI_DCBAAP, DCBAAPointer.DCBAAPointerLo | DCBAAPointer.RsvdZ ); + WRITE_REGISTER_ULONG(OperationalRegs + XHCI_DCBAAP + 1, DCBAAPointer.DCBAAPointerHi); + + X = READ_REGISTER_ULONG(OperationalRegs + XHCI_DCBAAP) ; + Y = READ_REGISTER_ULONG(OperationalRegs + XHCI_DCBAAP + 1) ; + DCBAAPointer.AsULONGULONG = Y|X ; + ASSERT(DCBAAPointer.RsvdZ == 0); + + // command ring intialisation. + + HcResourcesVA->CommandRing.Segment[0].Link[0].AsULONG = 0; + HcResourcesVA->CommandRing.Segment[0].Link[1].AsULONG = 0; + HcResourcesVA->CommandRing.Segment[0].Link[2].AsULONG = 0; + HcResourcesVA->CommandRing.Segment[0].Link[3].AsULONG = 0; + + HcResourcesVA->CommandRing.CREnquePointer= &HcResourcesVA->CommandRing.Segment[0]; + HcResourcesVA->CommandRing.CRDequePointer= HcResourcesVA->CommandRing.CREnquePointer; + + CommandRingControlRegister.AsULONGULONG = HcResourcesPA.QuadPart + FIELD_OFFSET(XHCI_HC_RESOURCES, CommandRing.Segment); + ASSERT(CommandRingControlRegister.RingCycleState == 0); + ASSERT(CommandRingControlRegister.CommandStop == 0); + ASSERT(CommandRingControlRegister.CommandAbort == 0); + ASSERT(CommandRingControlRegister.CommandRingRunning == 0); + ASSERT(CommandRingControlRegister.RsvdP == 0); + + WRITE_REGISTER_ULONG(OperationalRegs + XHCI_CRCR, CommandRingControlRegister.AsULONGULONG); + WRITE_REGISTER_ULONG(OperationalRegs + XHCI_CRCR + 1, CommandRingControlRegister.CommandRingPointerHi); + + DbgBreakPoint(); return MP_STATUS_SUCCESS; }
@@ -64,8 +113,9 @@ LARGE_INTEGER CurrentTime = {{0, 0}}; LARGE_INTEGER LastTime = {{0, 0}}; XHCI_HC_STRUCTURAL_PARAMS_1 StructuralParams_1; - - DPRINT1("EHCI_InitializeHardware: ... \n"); + XHCI_CONFIGURE Config; + + DPRINT1("XHCI_InitializeHardware: ... \n");
OperationalRegs = XhciExtension->OperationalRegs; BaseIoAdress = XhciExtension->BaseIoAdress; @@ -79,6 +129,7 @@
Command.AsULONG = READ_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD); Command.HCReset = 1; + WRITE_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD, Command.AsULONG); while(TRUE) { KeQuerySystemTime(&LastTime); @@ -94,19 +145,27 @@ { if (Command.HCReset == 1) { - DPRINT1("EHCI_InitializeHardware: Software Reset failed!\n"); + DPRINT1("XHCI_InitializeHardware: Software Reset failed!\n"); return 7; }
break; } } - DPRINT("EHCI_InitializeHardware: Reset - OK\n"); + DPRINT("XHCI_InitializeHardware: Reset - OK\n");
StructuralParams_1.AsULONG = READ_REGISTER_ULONG(BaseIoAdress + XHCI_HCSP1); // HCSPARAMS1 register
XhciExtension->NumberOfPorts = StructuralParams_1.NumberOfPorts; - //EhciExtension->PortPowerControl = StructuralParams.PortPowerControl; + + Command.AsULONG = READ_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD); + Config.AsULONG = READ_REGISTER_ULONG(OperationalRegs + XHCI_CONFIG); + ASSERT(Command.RunStop==0); //required before setting max device slots enabled. + Config.MaxDeviceSlotsEnabled = 1; // max possible value is number of slots HCSPARAMS1 + WRITE_REGISTER_ULONG(OperationalRegs + XHCI_CONFIG, Config.AsULONG); + // Device Context base aaddress array to be defined + // Commnad ring deque pointer to be defined in CRCR + DbgBreakPoint(); return MP_STATUS_SUCCESS; } @@ -162,7 +221,7 @@ return MPStatus; }
- MPStatus = XHCI_InitializeSchedule(XhciExtension, + MPStatus = XHCI_InitializeResources(XhciExtension, Resources->StartVA, Resources->StartPA);
Modified: branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.h URL: http://svn.reactos.org/svn/reactos/branches/GSoC_2017/usbxhci/reactos/driver... ============================================================================== --- branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.h [iso-8859-1] (original) +++ branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.h [iso-8859-1] Mon Jun 26 06:14:59 2017 @@ -13,6 +13,156 @@
extern USBPORT_REGISTRATION_PACKET RegPacket;
+ +//Data structures +typedef struct _XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY { + PHYSICAL_ADDRESS ContextBaseAddr [256]; +} XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY, *PXHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY; +//----------------------------------------LINK TRB-------------------------------------------------------------------- +typedef union _XHCI_LINK_TRB{ + struct { + ULONG RsvdZ1 : 4; + ULONG RingSegmentPointerLo : 28; + }; + struct { + ULONG RingSegmentPointerHi : 32; + }; + struct { + ULONG RsvdZ2 : 22; + ULONG InterrupterTarget : 10; + }; + struct { + ULONG CycleBit : 1; + ULONG ToggleCycle : 1; + ULONG RsvdZ3 : 2; + ULONG ChainBit : 1; + ULONG InterruptOnCompletion : 1; + ULONG RsvdZ4 : 4; + ULONG TRBType : 6; + ULONG RsvdZ5 : 16; + }; + ULONG AsULONG; +} XHCI_LINK_TRB; +//----------------------------------------Command TRBs---------------------------------------------------------------- +typedef union _XHCI_COMMAND_NO_OP_TRB { + struct { + ULONG RsvdZ1 : 5; + }; + struct { + ULONG RsvdZ2 : 5; + }; + struct { + ULONG RsvdZ3 : 5; + }; + struct { + ULONG CycleBit : 1; + ULONG RsvdZ4 : 4; + ULONG TRBType : 6; + ULONG RsvdZ5 : 14; + }; + ULONG AsULONG; +} XHCI_COMMAND_NO_OP_TRB; + +typedef union _XHCI_COMMAND_TRB { + XHCI_COMMAND_NO_OP_TRB NoOperation[4]; + XHCI_LINK_TRB Link[4]; +}XHCI_COMMAND_TRB, *PXHCI_COMMAND_TRB; + +typedef struct _XHCI_COMMAND_RING { + XHCI_COMMAND_TRB Segment[4]; + PXHCI_COMMAND_TRB CREnquePointer; + PXHCI_COMMAND_TRB CRDequePointer; +} XHCI_COMMAND_RING; +//----------------------------------------CONTROL TRANSFER DATA STRUCTUERS-------------------------------------------- + +typedef union _XHCI_CONTROL_SETUP_TRB { + struct { + ULONG bmRequestType : 8; + ULONG bRequest : 8; + ULONG wValue : 16; + }; + struct { + ULONG wIndex : 16; + ULONG wLength : 16; + }; + struct { + ULONG TRBTransferLength : 17; + ULONG RsvdZ : 5; + ULONG InterrupterTarget : 10; + }; + struct { + ULONG CycleBit : 1; + ULONG RsvdZ1 : 4; + ULONG InterruptOnCompletion : 1; + ULONG ImmediateData : 1; + ULONG RsvdZ2 : 3; + ULONG TRBType : 6; + ULONG TransferType : 2; + ULONG RsvdZ3 : 14; + }; + ULONG AsULONG; +} XHCI_CONTROL_SETUP_TRB; + +typedef union _XHCI_CONTROL_DATA_TRB { + struct { + ULONG DataBufferPointerLo : 32; + }; + struct { + ULONG DataBufferPointerHi : 32; + }; + struct { + ULONG TRBTransferLength : 17; + ULONG TDSize : 5; + ULONG InterrupterTarget : 10; + }; + struct { + ULONG CycleBit : 1; + ULONG EvaluateNextTRB : 1; + ULONG InterruptOnShortPacket : 1; + ULONG NoSnoop : 1; + ULONG ChainBit : 1; + ULONG InterruptOnCompletion : 1; + ULONG ImmediateData : 1; + ULONG RsvdZ1 : 2; + ULONG TRBType : 6; + ULONG Direction : 1; + ULONG RsvdZ2 : 15; + }; + ULONG AsULONG; +} XHCI_CONTROL_DATA_TRB; + +typedef union _XHCI_CONTROL_STATUS_TRB { + struct { + ULONG RsvdZ1 : 32; + }; + struct { + ULONG RsvdZ2 : 32; + }; + struct { + ULONG RsvdZ : 22; + ULONG InterrupterTarget : 10; + }; + struct { + ULONG CycleBit : 1; + ULONG EvaluateNextTRB : 1; + ULONG ChainBit : 2; + ULONG InterruptOnCompletion : 1; + ULONG RsvdZ3 : 4; + ULONG TRBType : 6; + ULONG Direction : 1; + ULONG RsvdZ4 : 15; + }; + ULONG AsULONG; +} XHCI_CONTROL_STATUS_TRB; + +typedef union _XHCI_CONTROL_TRB { + XHCI_CONTROL_SETUP_TRB SetupTRB[4]; + XHCI_CONTROL_DATA_TRB DataTRB[4]; + XHCI_CONTROL_STATUS_TRB StatusTRB[4]; +} XHCI_CONTROL_TRB, *PXHCI_CONTROL_TRB; + + +//------------------------------------main structs----------------------- typedef struct _XHCI_EXTENSION { ULONG Reserved; ULONG Flags; @@ -28,7 +178,8 @@ } XHCI_EXTENSION, *PXHCI_EXTENSION;
typedef struct _XHCI_HC_RESOURCES { - ULONG Reserved; + XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY DCBAA; + XHCI_COMMAND_RING CommandRing; } XHCI_HC_RESOURCES, *PXHCI_HC_RESOURCES;
typedef struct _XHCI_ENDPOINT { @@ -39,7 +190,6 @@ ULONG Reserved; } XHCI_TRANSFER, *PXHCI_TRANSFER;
- //roothub functions VOID NTAPI