- Implemented the interrupt handling for smp machines. - Enabled interrupts (irqs) on all processors. Modified: trunk/reactos/hal/halx86/mp/mpsirql.c Modified: trunk/reactos/hal/halx86/mp/processor_mp.c _____
Modified: trunk/reactos/hal/halx86/mp/mpsirql.c --- trunk/reactos/hal/halx86/mp/mpsirql.c 2005-01-01 11:28:46 UTC (rev 12690) +++ trunk/reactos/hal/halx86/mp/mpsirql.c 2005-01-01 11:31:43 UTC (rev 12691) @@ -375,6 +375,8 @@
return FALSE; }
+ /* FIXME: We must check if the requested and the assigned interrupt mode is the same */ + irq = VECTOR2IRQ (Vector); IOAPICUnmaskIrq (irq);
_____
Modified: trunk/reactos/hal/halx86/mp/processor_mp.c --- trunk/reactos/hal/halx86/mp/processor_mp.c 2005-01-01 11:28:46 UTC (rev 12690) +++ trunk/reactos/hal/halx86/mp/processor_mp.c 2005-01-01 11:31:43 UTC (rev 12691) @@ -1,4 +1,4 @@
-/* $Id: processor_mp.c,v 1.2 2004/12/25 11:21:48 navaraf Exp $ +/* $Id$ * * COPYRIGHT: See COPYING in the top level directory * PROJECT: ReactOS kernel @@ -186,10 +186,15 @@ IOAPIC_ROUTE_ENTRY Entry; ULONG Apic = IrqApicMap[Irq];
- - *((PULONG)&Entry) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq); - Entry.mask = 1; - IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq, *((PULONG)&Entry)); + *(((PULONG)&Entry)+0) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq); + *(((PULONG)&Entry)+1) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq+1); + Entry.dest.logical.logical_dest &= ~(1 << KeGetCurrentProcessorNumber()); + if (Entry.dest.logical.logical_dest == 0) + { + Entry.mask = 1; + } + IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq+1, *(((PULONG)&Entry)+1)); + IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq, *(((PULONG)&Entry)+0)); }
@@ -199,9 +204,12 @@ IOAPIC_ROUTE_ENTRY Entry; ULONG Apic = IrqApicMap[Irq];
- *((PULONG)&Entry) = IOAPICRead(Apic, IOAPIC_REDTBL+2*IrqPinMap[Irq]); + *(((PULONG)&Entry)+0) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq); + *(((PULONG)&Entry)+1) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq+1); + Entry.dest.logical.logical_dest |= 1 << KeGetCurrentProcessorNumber(); Entry.mask = 0; - IOAPICWrite(Apic, IOAPIC_REDTBL+2*IrqPinMap[Irq], *((PULONG)&Entry)); + IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq+1, *(((PULONG)&Entry)+1)); + IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq, *(((PULONG)&Entry)+0)); }
static VOID @@ -619,15 +627,8 @@ entry.delivery_mode = (APIC_DM_LOWEST >> 8); entry.dest_mode = 1; /* logical delivery */ entry.mask = 1; /* disable IRQ */ -#if 0 - /* - * FIXME: - * Some drivers are not able to deal with more than one cpu. - */ - entry.dest.logical.logical_dest = OnlineCPUs; -#else - entry.dest.logical.logical_dest = 1 << 0; -#endif + entry.dest.logical.logical_dest = 0; + idx = IOAPICGetIrqEntry(apic,pin,INT_VECTORED); if (idx == -1) { @@ -650,11 +651,7 @@ { entry.trigger = 1; entry.mask = 1; // disable -#if 0 - entry.dest.logical.logical_dest = OnlineCPUs; -#else - entry.dest.logical.logical_dest = 1 << 0; -#endif + entry.dest.logical.logical_dest = 0; }
irq = Pin2Irq(idx, apic, pin);