Author: sir_richard
Date: Thu Jan 21 14:36:30 2010
New Revision: 45182
URL:
http://svn.reactos.org/svn/reactos?rev=45182&view=rev
Log:
[HAL]: The HAL is a mess. Fix build.
Modified:
trunk/reactos/hal/halx86/mp/halinit_mp.c
trunk/reactos/hal/halx86/mp/ioapic.c
Modified: trunk/reactos/hal/halx86/mp/halinit_mp.c
URL:
http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/mp/halinit_mp.c…
==============================================================================
--- trunk/reactos/hal/halx86/mp/halinit_mp.c [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/mp/halinit_mp.c [iso-8859-1] Thu Jan 21 14:36:30 2010
@@ -22,7 +22,7 @@
/***************************************************************************/
-VOID NTAPI HalpInitPICs(VOID)
+VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts)
{
UNIMPLEMENTED;
}
Modified: trunk/reactos/hal/halx86/mp/ioapic.c
URL:
http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/mp/ioapic.c?rev…
==============================================================================
--- trunk/reactos/hal/halx86/mp/ioapic.c [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/mp/ioapic.c [iso-8859-1] Thu Jan 21 14:36:30 2010
@@ -32,7 +32,7 @@
* EISA conforming in the MP table, that means its trigger type must
* be read in from the ELCR */
-#define default_EISA_trigger(idx) (EISA_ELCR(IRQMap[idx].SrcBusIrq))
+#define default_EISA_trigger(idx) (EISA_ELCR_Read(IRQMap[idx].SrcBusIrq))
#define default_EISA_polarity(idx) (0)
/* ISA interrupts are always polarity zero edge triggered,
@@ -64,7 +64,7 @@
/*
* EISA Edge/Level control register, ELCR
*/
-static ULONG EISA_ELCR(ULONG irq)
+static ULONG EISA_ELCR_Read(ULONG irq)
{
if (irq < 16)
{