Author: tkreuzer Date: Wed Sep 7 21:41:50 2011 New Revision: 53631
URL: http://svn.reactos.org/svn/reactos?rev=53631&view=rev Log: [HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build
Modified: trunk/reactos/hal/halx86/apic/apic.c trunk/reactos/hal/halx86/apic/apic.h trunk/reactos/hal/halx86/apic/apictrap.S trunk/reactos/hal/halx86/apic/halinit_apic.c trunk/reactos/hal/halx86/apic/rtctimer.c trunk/reactos/hal/halx86/apic/tsc.h trunk/reactos/hal/halx86/apic/tsccal.S
Modified: trunk/reactos/hal/halx86/apic/apic.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/apic/apic.c?rev=... ============================================================================== --- trunk/reactos/hal/halx86/apic/apic.c [iso-8859-1] (original) +++ trunk/reactos/hal/halx86/apic/apic.c [iso-8859-1] Wed Sep 7 21:41:50 2011 @@ -220,8 +220,8 @@ __outbyte(PIC2_DATA_PORT, 0xFF); }
- -VOID +VOID +NTAPI ApicInitializeLocalApic(ULONG Cpu) { APIC_BASE_ADRESS_REGISTER BaseRegister; @@ -233,9 +233,6 @@ BaseRegister.Enable = 1; BaseRegister.BootStrapCPUCore = (Cpu == 0); __writemsr(MSR_APIC_BASE, BaseRegister.Long); - - DPRINT1("ApicBase for Cpu %u PhysicalAddress = %p\n", Cpu, BaseRegister.BaseAddress); - DPRINT1("ApicVersion = 0x%lx\n", ApicRead(0x30));
/* Set spurious vector and SoftwareEnable to 1 */ SpIntRegister.Long = ApicRead(APIC_SIVR); @@ -283,24 +280,10 @@ LvtEntry.MessageType = APIC_MT_Fixed; ApicWrite(APIC_ERRLVTR, LvtEntry.Long);
- DPRINT1("Error code = 0x%lx\n", ApicRead(0x280)); -} - -VOID -NTAPI -ApicInitializeProcessor( - IN ULONG ProcessorNumber, - IN PLOADER_PARAMETER_BLOCK LoaderBlock) -{ - DPRINT1("ApicInitializeProcessor(%ld)\n", ProcessorNumber); - - /* Initialize the local APIC for this cpu */ - ApicInitializeLocalApic(ProcessorNumber); - - /* Initialize the timer */ - ApicInitializeTimer(ProcessorNumber); - -} + /* Set the IRQL from the PCR */ + ApicSetCurrentIrql(KeGetPcr()->Irql); +} +
VOID FORCEINLINE @@ -443,9 +426,6 @@ EFlags = __readeflags(); _disable();
- /* Initialize the local APIC for this cpu */ - ApicInitializeLocalApic(0); - /* Initialize and mask the PIC */ HalpInitializeLegacyPIC();
@@ -455,21 +435,10 @@
/* Register interrupt handlers */ KeRegisterInterruptHandler(APIC_CLOCK_VECTOR, HalpClockInterrupt); +#ifndef _M_AMD64 KeRegisterInterruptHandler(APC_VECTOR, HalpApcInterrupt); KeRegisterInterruptHandler(DPC_VECTOR, HalpDispatchInterrupt); - - // HACK, since we messed with the value, should init the local apic in - // HalInitializeProcessor instead - ApicSetCurrentIrql(APC_LEVEL); - ASSERT(ApicGetProcessorIrql() <= APC_LEVEL); - -__debugbreak(); - -HalpInitializeClock(); -//HalpCalibrateStallExecution(); -_enable(); -for (;;); - +#endif
/* Restore interrupt state */ if (EnableInterrupts) EFlags |= EFLAGS_INTERRUPT_MASK; @@ -488,6 +457,7 @@ ASSERT(FALSE); }
+#ifndef _M_AMD64 VOID DECLSPEC_NORETURN FASTCALL @@ -512,7 +482,7 @@ /* Exit the interrupt */ KiEoiHelper(TrapFrame); } - +#endif
/* PUBLIC FUNCTIONS ***********************************************************/
@@ -592,6 +562,7 @@ IOApicWrite(IOAPIC_REDTBL + 2 * Irql, ReDirReg.Long0); }
+#ifndef _M_AMD64 BOOLEAN NTAPI HalBeginSystemInterrupt( @@ -625,7 +596,6 @@ ApicWrite(APIC_EOI, 0); }
-#ifndef _M_AMD64
KIRQL NTAPI @@ -659,7 +629,7 @@ { KIRQL OldIrql;
- /* Read the current TPR and convert it to an IRQL */ + /* Read the current IRQL */ OldIrql = ApicGetCurrentIrql(); #if DBG /* Validate correct raise */ @@ -672,6 +642,7 @@ /* Convert the new IRQL to a TPR value and write the register */ ApicSetCurrentIrql(NewIrql);
+ /* Return old IRQL */ return OldIrql; }
Modified: trunk/reactos/hal/halx86/apic/apic.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/apic/apic.h?rev=... ============================================================================== --- trunk/reactos/hal/halx86/apic/apic.h [iso-8859-1] (original) +++ trunk/reactos/hal/halx86/apic/apic.h [iso-8859-1] Wed Sep 7 21:41:50 2011 @@ -1,6 +1,7 @@
#ifdef _M_AMD64 -#define APIC_BASE 0xfffffffffee00000ULL; +#define APIC_BASE 0xFFFFFFFFFEE00000ULL +#define IOAPIC_BASE 0xFFFFFFFFFEE01000ULL // checkme #define ZERO_VECTOR 0x00 // IRQL 00 #define APC_VECTOR 0x3D // IRQL 01 #define APIC_SPURIOUS_VECTOR 0x3f @@ -18,7 +19,6 @@ #else #define APIC_BASE 0xFFFE0000 #define IOAPIC_BASE 0xFFFE1000 // checkme -#define IOAPIC_PHYS_BASE 0xFEC00000 #define ZERO_VECTOR 0x00 // IRQL 00 #define APIC_SPURIOUS_VECTOR 0x1f #define APC_VECTOR 0x3D // IRQL 01 @@ -36,6 +36,7 @@ #endif
#define MSR_APIC_BASE 0x0000001B +#define IOAPIC_PHYS_BASE 0xFEC00000 #define APIC_CLOCK_INDEX 8
Modified: trunk/reactos/hal/halx86/apic/apictrap.S URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/apic/apictrap.S?... ============================================================================== --- trunk/reactos/hal/halx86/apic/apictrap.S [iso-8859-1] (original) +++ trunk/reactos/hal/halx86/apic/apictrap.S [iso-8859-1] Wed Sep 7 21:41:50 2011 @@ -9,25 +9,32 @@ /* INCLUDES ******************************************************************/
#include <asm.inc> -#include <internal/i386/asmmacro.S>
#ifdef _M_AMD64 #include <ksamd64.inc> +#include <trapamd64.inc> +#define KI_PUSH_FAKE_ERROR_CODE TF_PUSH_FAKE_ERROR_CODE PUBLIC ApicSpuriousService #else #include <ks386.inc> +#include <internal/i386/asmmacro.S> PUBLIC _ApicSpuriousService #endif
.code
+#ifndef _M_AMD64 TRAP_ENTRY HalpTrap0D, 0 -TRAP_ENTRY HalpApcInterrupt, KI_SOFTWARE_TRAP +TRAP_ENTRY HalpApcInterrupt, KI_PUSH_FAKE_ERROR_CODE TRAP_ENTRY HalpDispatchInterrupt, KI_PUSH_FAKE_ERROR_CODE +#endif TRAP_ENTRY HalpClockInterrupt, KI_PUSH_FAKE_ERROR_CODE TRAP_ENTRY HalpProfileInterrupt, KI_PUSH_FAKE_ERROR_CODE
FUNC ApicSpuriousService +#ifdef _M_AMD64 + .ENDPROLOG +#endif int 3 iret ENDFUNC ApicSpuriousService
Modified: trunk/reactos/hal/halx86/apic/halinit_apic.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/apic/halinit_api... ============================================================================== --- trunk/reactos/hal/halx86/apic/halinit_apic.c [iso-8859-1] (original) +++ trunk/reactos/hal/halx86/apic/halinit_apic.c [iso-8859-1] Wed Sep 7 21:41:50 2011 @@ -27,8 +27,6 @@ IN ULONG ProcessorNumber, IN PLOADER_PARAMETER_BLOCK LoaderBlock) { - DPRINT1("ApicInitializeProcessor(%ld)\n", ProcessorNumber); - /* Initialize the local APIC for this cpu */ ApicInitializeLocalApic(ProcessorNumber);
Modified: trunk/reactos/hal/halx86/apic/rtctimer.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/apic/rtctimer.c?... ============================================================================== --- trunk/reactos/hal/halx86/apic/rtctimer.c [iso-8859-1] (original) +++ trunk/reactos/hal/halx86/apic/rtctimer.c [iso-8859-1] Wed Sep 7 21:41:50 2011 @@ -42,6 +42,9 @@ EFlags = __readeflags(); _disable();
+ /* Acquire CMOS lock */ + HalpAcquireCmosSpinLock(); + // TODO: disable NMI
/* Read value of register A */ @@ -53,6 +56,9 @@
/* Write the new value */ HalpWriteCmos(RTC_REGISTER_A, RegisterA); + + /* Release CMOS lock */ + HalpReleaseCmosSpinLock();
/* Restore interrupts if they were previously enabled */ __writeeflags(EFlags); @@ -67,9 +73,15 @@ UCHAR RegisterB; // TODO: disable NMI
+ /* Acquire CMOS lock */ + HalpAcquireCmosSpinLock(); + /* Enable the periodic interrupt in the CMOS */ RegisterB = HalpReadCmos(RTC_REGISTER_B); HalpWriteCmos(RTC_REGISTER_B, RegisterB | RTC_REG_B_PI); + + /* Release CMOS lock */ + HalpReleaseCmosSpinLock();
// RtcSetClockRate(HalpCurrentRate); } @@ -84,8 +96,9 @@ /* Enter trap */ KiEnterInterruptTrap(TrapFrame); __debugbreak(); + /* Start the interrupt */ - if (HalBeginSystemInterrupt(CLOCK2_LEVEL, PRIMARY_VECTOR_BASE, &Irql)) + if (HalBeginSystemInterrupt(CLOCK_LEVEL, PRIMARY_VECTOR_BASE, &Irql)) { /* Read register C, so that the next interrupt can happen */ HalpReadCmos(RTC_REGISTER_C);;
Modified: trunk/reactos/hal/halx86/apic/tsc.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/apic/tsc.h?rev=5... ============================================================================== --- trunk/reactos/hal/halx86/apic/tsc.h [iso-8859-1] (original) +++ trunk/reactos/hal/halx86/apic/tsc.h [iso-8859-1] Wed Sep 7 21:41:50 2011 @@ -9,7 +9,10 @@ extern LARGE_INTEGER HalpCpuClockFrequency; VOID NTAPI HalpInitializeTsc();
- +#ifdef _M_AMD64 +#define KiGetIdtEntry(Pcr, Vector) &((Pcr)->IdtBase[Vector]) +#else #define KiGetIdtEntry(Pcr, Vector) &((Pcr)->IDT[Vector]) +#endif
#endif
Modified: trunk/reactos/hal/halx86/apic/tsccal.S URL: http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/apic/tsccal.S?re... ============================================================================== --- trunk/reactos/hal/halx86/apic/tsccal.S [iso-8859-1] (original) +++ trunk/reactos/hal/halx86/apic/tsccal.S [iso-8859-1] Wed Sep 7 21:41:50 2011 @@ -3,6 +3,8 @@ #include "tsc.h"
.code + +#ifdef _M_IX86
EXTERN _TscCalibrationPhase:BYTE EXTERN _TscCalibrationArray:QWORD @@ -36,4 +38,43 @@ pop eax iretd
+#else + +EXTERN TscCalibrationPhase:BYTE +EXTERN TscCalibrationArray:DWORD + +PUBLIC TscCalibrationISR +FUNC TscCalibrationISR + push rax + push rcx + push rdx + .ENDPROLOG + + /* The first thing we do is read the current TSC value */ + rdtsc + + /* Read the current phase */ + movzx rcx, byte ptr [TscCalibrationPhase] + + /* Check if we're already done */ + cmp cl, NUM_SAMPLES + jnb CalibrationISR_Exit + + /* Store the current value */ + shl rcx, 1 + lea rax, [TscCalibrationArray] + mov dword ptr [rax + rcx], eax + mov dword ptr [rax + rcx + 4], edx + + /* Advance phase */ + inc byte ptr [TscCalibrationPhase] + +CalibrationISR_Exit: + pop rdx + pop rcx + pop rax + iretq +ENDFUNC TscCalibrationISR +#endif + END