[ros-diffs] [reactos] 08/09: [HDAUDBUS] Correctly mask register values.

[Thomas Faber]

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=25b22131ca5f30a81f6d8…

commit 25b22131ca5f30a81f6d827f1fe480ce33aa4103
Author:     Thomas Faber <thomas.faber(a)reactos.org>
AuthorDate: Mon Feb 25 01:56:25 2019 +0100
Commit:     Thomas Faber <thomas.faber(a)reactos.org>
CommitDate: Tue Feb 26 09:51:48 2019 +0100

    [HDAUDBUS] Correctly mask register values.
    
    See
https://github.com/haiku/haiku/blob/master/src/add-ons/kernel/drivers/audio…
    and
https://github.com/haiku/haiku/blob/master/src/add-ons/kernel/drivers/audio…
    
    This fixes various device reset failures and probably other issues.
---
 drivers/wdm/audio/hdaudbus/fdo.cpp | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/wdm/audio/hdaudbus/fdo.cpp b/drivers/wdm/audio/hdaudbus/fdo.cpp
index a14b5b9dda..84686e3bd3 100644
--- a/drivers/wdm/audio/hdaudbus/fdo.cpp
+++ b/drivers/wdm/audio/hdaudbus/fdo.cpp
@@ -285,19 +285,19 @@ HDA_InitCorbRirbPos(
     if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) {
         DeviceExtension->CorbLength = 256;
 
-        value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE) &
HDAC_CORB_SIZE_MASK;
+        value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE) &
~HDAC_CORB_SIZE_MASK;
         WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE, value |
CORB_SIZE_256_ENTRIES);
     }
     else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) {
         DeviceExtension->CorbLength = 16;
 
-        value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE) &
HDAC_CORB_SIZE_MASK;
+        value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE) &
~HDAC_CORB_SIZE_MASK;
         WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE, value |
CORB_SIZE_16_ENTRIES);
     }
     else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) {
         DeviceExtension->CorbLength = 2;
 
-        value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE) &
HDAC_CORB_SIZE_MASK;
+        value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE) &
~HDAC_CORB_SIZE_MASK;
         WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_SIZE, value |
CORB_SIZE_2_ENTRIES);
     }
 
@@ -306,19 +306,19 @@ HDA_InitCorbRirbPos(
     if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) {
         DeviceExtension->RirbLength = 256;
 
-        value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE) &
HDAC_RIRB_SIZE_MASK;
+        value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE) &
~HDAC_RIRB_SIZE_MASK;
         WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE, value |
RIRB_SIZE_256_ENTRIES);
     }
     else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) {
         DeviceExtension->RirbLength = 16;
 
-        value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE) &
HDAC_RIRB_SIZE_MASK;
+        value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE) &
~HDAC_RIRB_SIZE_MASK;
         WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE, value |
RIRB_SIZE_16_ENTRIES);
     }
     else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) {
         DeviceExtension->RirbLength = 2;
 
-        value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE) &
HDAC_RIRB_SIZE_MASK;
+        value = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE) &
~HDAC_RIRB_SIZE_MASK;
         WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_SIZE, value |
RIRB_SIZE_2_ENTRIES);
     }
 
@@ -349,7 +349,7 @@ HDA_InitCorbRirbPos(
     WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase +
HDAC_DMA_POSITION_BASE_LOWER), CorbPhysicalAddress.LowPart);
     WRITE_REGISTER_ULONG((PULONG)(DeviceExtension->RegBase +
HDAC_DMA_POSITION_BASE_UPPER), CorbPhysicalAddress.HighPart);
 
-    value = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase +
HDAC_CORB_WRITE_POS)) & HDAC_CORB_WRITE_POS_MASK;
+    value = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase +
HDAC_CORB_WRITE_POS)) & ~HDAC_CORB_WRITE_POS_MASK;
     WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_WRITE_POS),
value);
 
     // Reset CORB read pointer. Preserve bits marked as RsvdP.
@@ -392,11 +392,11 @@ HDA_InitCorbRirbPos(
     }
 
     // Reset RIRB write pointer
-    rirbWritePointer = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase +
HDAC_RIRB_WRITE_POS)) & RIRB_WRITE_POS_RESET;
+    rirbWritePointer = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase +
HDAC_RIRB_WRITE_POS)) & ~RIRB_WRITE_POS_RESET;
     WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_RIRB_WRITE_POS),
rirbWritePointer | RIRB_WRITE_POS_RESET);
 
     // Generate interrupt for every response
-    interruptValue = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase +
HDAC_RESPONSE_INTR_COUNT)) & HDAC_RESPONSE_INTR_COUNT_MASK;
+    interruptValue = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase +
HDAC_RESPONSE_INTR_COUNT)) & ~HDAC_RESPONSE_INTR_COUNT_MASK;
     WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase +
HDAC_RESPONSE_INTR_COUNT), interruptValue | 1);
 
     // Setup cached read/write indices
@@ -404,10 +404,10 @@ HDA_InitCorbRirbPos(
     DeviceExtension->CorbWritePos = 0;
 
     // Gentlemen, start your engines...
-    corbControl = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase +
HDAC_CORB_CONTROL)) &HDAC_CORB_CONTROL_MASK;
+    corbControl = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase +
HDAC_CORB_CONTROL)) & ~HDAC_CORB_CONTROL_MASK;
     WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_CORB_CONTROL),
corbControl | CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR);
 
-    rirbControl = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase +
HDAC_RIRB_CONTROL)) & HDAC_RIRB_CONTROL_MASK;
+    rirbControl = READ_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase +
HDAC_RIRB_CONTROL)) & ~HDAC_RIRB_CONTROL_MASK;
     WRITE_REGISTER_USHORT((PUSHORT)(DeviceExtension->RegBase + HDAC_RIRB_CONTROL),
rirbControl | RIRB_CONTROL_DMA_ENABLE | RIRB_CONTROL_OVERRUN_INTR |
RIRB_CONTROL_RESPONSE_INTR);
 
     return STATUS_SUCCESS;
@@ -456,10 +456,10 @@ HDA_ResetController(
     }
 
     // stop DMA
-    Control = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_CONTROL) &
HDAC_CORB_CONTROL_MASK;
+    Control = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_CONTROL) &
~HDAC_CORB_CONTROL_MASK;
     WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_CORB_CONTROL, Control);
 
-    Control = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_CONTROL) &
HDAC_RIRB_CONTROL_MASK;
+    Control = READ_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_CONTROL) &
~HDAC_RIRB_CONTROL_MASK;
     WRITE_REGISTER_UCHAR(DeviceExtension->RegBase + HDAC_RIRB_CONTROL, Control);
 
     for (int timeout = 0; timeout < 10; timeout++) {