Author: aandrejevic
Date: Sun May 10 23:50:33 2015
New Revision: 67647
URL:
http://svn.reactos.org/svn/reactos?rev=67647&view=rev
Log:
[FAST486]
The LMSW instruction doesn't #GP when the program tries to return to real mode.
Rather, it just doesn't happen (the PE bit remains 1).
Modified:
trunk/reactos/lib/fast486/opgroups.c
Modified: trunk/reactos/lib/fast486/opgroups.c
URL:
http://svn.reactos.org/svn/reactos/trunk/reactos/lib/fast486/opgroups.c?rev…
==============================================================================
--- trunk/reactos/lib/fast486/opgroups.c [iso-8859-1] (original)
+++ trunk/reactos/lib/fast486/opgroups.c [iso-8859-1] Sun May 10 23:50:33 2015
@@ -2239,11 +2239,14 @@
{
USHORT MachineStatusWord;
- /* This is a privileged instruction */
- if (Fast486GetCurrentPrivLevel(State) != 0)
- {
- Fast486Exception(State, FAST486_EXCEPTION_GP);
- return;
+ if (State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PE)
+ {
+ /* This is a privileged instruction */
+ if (Fast486GetCurrentPrivLevel(State) != 0)
+ {
+ Fast486Exception(State, FAST486_EXCEPTION_GP);
+ return;
+ }
}
/* Read the new Machine Status Word */
@@ -2253,16 +2256,8 @@
return;
}
- /* This instruction cannot be used to return to real mode */
- if ((State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PE)
- && !(MachineStatusWord & FAST486_CR0_PE))
- {
- Fast486Exception(State, FAST486_EXCEPTION_GP);
- return;
- }
-
- /* Set the lowest 4 bits */
- State->ControlRegisters[FAST486_REG_CR0] &= 0xFFFFFFF0;
+ /* Set the lowest 4 bits, but never clear bit 0 */
+ State->ControlRegisters[FAST486_REG_CR0] &= 0xFFFFFFF1;
State->ControlRegisters[FAST486_REG_CR0] |= MachineStatusWord & 0x0F;
break;