[sserapion] 44639: [UniAta] - Coding late at night can cloud your judgment. - Better fix for pointer truncation(just don't do it.) - Todo send patch upstream
Author: sserapion Date: Thu Dec 17 15:35:25 2009 New Revision: 44639
URL: http://svn.reactos.org/svn/reactos?rev=44639&view=rev Log: [UniAta] - Coding late at night can cloud your judgment. - Better fix for pointer truncation(just don't do it.) - Todo send patch upstream
Modified: branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/bsmaster.h branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_ata.cpp branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_dma.cpp branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_init.cpp branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_sata.cpp
Modified: branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/bsmaster.h URL: http://svn.reactos.org/svn/reactos/branches/ros-amd64-bringup/reactos/driver... ============================================================================== --- branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/bsmaster.h [iso-8859-1] (original) +++ branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/bsmaster.h [iso-8859-1] Thu Dec 17 15:35:25 2009 @@ -1345,7 +1345,7 @@ DDKFASTAPI AtapiWritePort4( IN PHW_CHANNEL chan, - IN ULONG port, + IN ULONG_PTR port, IN ULONG data );
@@ -1353,7 +1353,7 @@ DDKFASTAPI AtapiWritePort2( IN PHW_CHANNEL chan, - IN ULONG port, + IN ULONG_PTR port, IN USHORT data );
@@ -1361,7 +1361,7 @@ DDKFASTAPI AtapiWritePort1( IN PHW_CHANNEL chan, - IN ULONG port, + IN ULONG_PTR port, IN UCHAR data );
@@ -1369,7 +1369,7 @@ DDKFASTAPI AtapiWritePortEx4( IN PHW_CHANNEL chan, - IN ULONG port, + IN ULONG_PTR port, IN ULONG offs, IN ULONG data ); @@ -1378,7 +1378,7 @@ DDKFASTAPI AtapiWritePortEx1( IN PHW_CHANNEL chan, - IN ULONG port, + IN ULONG_PTR port, IN ULONG offs, IN UCHAR data ); @@ -1387,28 +1387,28 @@ DDKFASTAPI AtapiReadPort4( IN PHW_CHANNEL chan, - IN ULONG port + IN ULONG_PTR port );
USHORT DDKFASTAPI AtapiReadPort2( IN PHW_CHANNEL chan, - IN ULONG port + IN ULONG_PTR port );
UCHAR DDKFASTAPI AtapiReadPort1( IN PHW_CHANNEL chan, - IN ULONG port + IN ULONG_PTR port );
ULONG DDKFASTAPI AtapiReadPortEx4( IN PHW_CHANNEL chan, - IN ULONG port, + IN ULONG_PTR port, IN ULONG offs );
@@ -1416,7 +1416,7 @@ DDKFASTAPI AtapiReadPortEx1( IN PHW_CHANNEL chan, - IN ULONG port, + IN ULONG_PTR port, IN ULONG offs );
@@ -1424,7 +1424,7 @@ DDKFASTAPI AtapiWriteBuffer4( IN PHW_CHANNEL chan, - IN ULONG _port, + IN ULONG_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing @@ -1434,7 +1434,7 @@ DDKFASTAPI AtapiWriteBuffer2( IN PHW_CHANNEL chan, - IN ULONG _port, + IN ULONG_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing @@ -1444,7 +1444,7 @@ DDKFASTAPI AtapiReadBuffer4( IN PHW_CHANNEL chan, - IN ULONG _port, + IN ULONG_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing @@ -1454,7 +1454,7 @@ DDKFASTAPI AtapiReadBuffer2( IN PHW_CHANNEL chan, - IN ULONG _port, + IN ULONG_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing
Modified: branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_ata.cpp URL: http://svn.reactos.org/svn/reactos/branches/ros-amd64-bringup/reactos/driver... ============================================================================== --- branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_ata.cpp [iso-8859-1] (original) +++ branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_ata.cpp [iso-8859-1] Thu Dec 17 15:35:25 2009 @@ -240,7 +240,7 @@ DDKFASTAPI \ AtapiWritePort##sz( \ IN PHW_CHANNEL chan, \ - IN ULONG _port, \ + IN ULONG_PTR _port, \ IN _type data \ ) \ { \ @@ -272,7 +272,7 @@ DDKFASTAPI \ AtapiWritePortEx##sz( \ IN PHW_CHANNEL chan, \ - IN ULONG _port, \ + IN ULONG_PTR _port, \ IN ULONG offs, \ IN _type data \ ) \ @@ -305,7 +305,7 @@ DDKFASTAPI \ AtapiReadPort##sz( \ IN PHW_CHANNEL chan, \ - IN ULONG _port \ + IN ULONG_PTR _port \ ) \ { \ PIORES res; \ @@ -336,7 +336,7 @@ DDKFASTAPI \ AtapiReadPortEx##sz( \ IN PHW_CHANNEL chan, \ - IN ULONG _port, \ + IN ULONG_PTR _port, \ IN ULONG offs \ ) \ { \ @@ -367,7 +367,7 @@ DDKFASTAPI \ AtapiReadBuffer##sz( \ IN PHW_CHANNEL chan, \ - IN ULONG _port, \ + IN ULONG_PTR _port, \ IN PVOID Buffer, \ IN ULONG Count, \ IN ULONG Timing \ @@ -412,7 +412,7 @@ DDKFASTAPI \ AtapiWriteBuffer##sz( \ IN PHW_CHANNEL chan, \ - IN ULONG _port, \ + IN ULONG_PTR _port, \ IN PVOID Buffer, \ IN ULONG Count, \ IN ULONG Timing \ @@ -2041,16 +2041,16 @@ goto default_reset; offset = ((Channel & 1) << 7) + ((Channel & 2) << 8); /* disable PHY state change interrupt */ - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0), 0x148 + offset, 0); + AtapiWritePortEx4(NULL, (ULONG_PTR)&deviceExtension->BaseIoAddressSATA_0, 0x148 + offset, 0);
UniataSataClearErr(HwDeviceExtension, j, UNIATA_SATA_IGNORE_CONNECT);
/* reset controller part for this channel */ - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0), 0x48, - AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0), 0x48) | (0xc0 >> Channel)); + AtapiWritePortEx4(NULL, (ULONG_PTR)&deviceExtension->BaseIoAddressSATA_0, 0x48, + AtapiReadPortEx4(NULL, (ULONG_PTR)&deviceExtension->BaseIoAddressSATA_0, 0x48) | (0xc0 >> Channel)); AtapiStallExecution(1000); - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0), 0x48, - AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0), 0x48) & ~(0xc0 >> Channel)); + AtapiWritePortEx4(NULL, (ULONG_PTR)&deviceExtension->BaseIoAddressSATA_0, 0x48, + AtapiReadPortEx4(NULL, (ULONG_PTR)&deviceExtension->BaseIoAddressSATA_0, 0x48) & ~(0xc0 >> Channel));
break; } @@ -3613,7 +3613,7 @@ switch(ChipType) { case PROLD: case PRNEW: - status = AtapiReadPortEx4(chan, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),0x1c); + status = AtapiReadPortEx4(chan, (ULONG_PTR)&deviceExtension->BaseIoAddressBM_0,0x1c); if (!DmaTransfer) break; if (!(status & @@ -3633,10 +3633,10 @@ } break; case PRMIO: - status = AtapiReadPortEx4(chan, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),0x0040); + status = AtapiReadPortEx4(chan, (ULONG_PTR)&deviceExtension->BaseIoAddressBM_0,0x0040); if(ChipFlags & PRSATA) { - pr_status = AtapiReadPortEx4(chan, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),0x006c); - AtapiWritePortEx4(chan, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),0x006c, pr_status & 0x000000ff); + pr_status = AtapiReadPortEx4(chan, (ULONG_PTR)&deviceExtension->BaseIoAddressBM_0,0x006c); + AtapiWritePortEx4(chan, (ULONG_PTR)&deviceExtension->BaseIoAddressBM_0,0x006c, pr_status & 0x000000ff); } if(pr_status & (0x11 << Channel)) { // TODO: reset channel @@ -3662,11 +3662,11 @@
/* get and clear interrupt status */ if(ChipFlags & NVQ) { - pr_status = AtapiReadPortEx4(chan, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),offs); - AtapiWritePortEx4(chan, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),offs, (0x0fUL << shift) | 0x00f000f0); + pr_status = AtapiReadPortEx4(chan, (ULONG_PTR)&deviceExtension->BaseIoAddressSATA_0,offs); + AtapiWritePortEx4(chan, (ULONG_PTR)&deviceExtension->BaseIoAddressSATA_0,offs, (0x0fUL << shift) | 0x00f000f0); } else { - pr_status = AtapiReadPortEx1(chan, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),offs); - AtapiWritePortEx1(chan, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),offs, (0x0f << shift)); + pr_status = AtapiReadPortEx1(chan,(ULONG_PTR)&deviceExtension->BaseIoAddressSATA_0,offs); + AtapiWritePortEx1(chan, (ULONG_PTR)&deviceExtension->BaseIoAddressSATA_0,offs, (0x0f << shift)); } KdPrint2((PRINT_PREFIX " pr_status %x\n", pr_status));
Modified: branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_dma.cpp URL: http://svn.reactos.org/svn/reactos/branches/ros-amd64-bringup/reactos/driver... ============================================================================== --- branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_dma.cpp [iso-8859-1] (original) +++ branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_dma.cpp [iso-8859-1] Thu Dec 17 15:35:25 2009 @@ -495,10 +495,10 @@ if(ChipType == PRNEW) { ULONG Channel = deviceExtension->Channel + lChannel; if(chan->ChannelCtrlFlags & CTRFLAGS_LBA48) { - AtapiWritePortEx1(chan, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),0x11, - AtapiReadPortEx1(chan, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),0x11) | + AtapiWritePortEx1(chan, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11, + AtapiReadPortEx1(chan, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11) | (Channel ? 0x08 : 0x02)); - AtapiWritePortEx4(chan, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),(Channel ? 0x24 : 0x20), + AtapiWritePortEx4(chan, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0),(Channel ? 0x24 : 0x20), ((Srb->SrbFlags & SRB_FLAGS_DATA_IN) ? 0x05000000 : 0x06000000) | (Srb->DataTransferLength >> 1) ); } @@ -562,10 +562,10 @@ if(ChipType == PRNEW) { ULONG Channel = deviceExtension->Channel + lChannel; if(chan->ChannelCtrlFlags & CTRFLAGS_LBA48) { - AtapiWritePortEx1(chan, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),0x11, - AtapiReadPortEx1(chan, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),0x11) & + AtapiWritePortEx1(chan, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11, + AtapiReadPortEx1(chan, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11) & ~(Channel ? 0x08 : 0x02)); - AtapiWritePortEx4(chan, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),(Channel ? 0x24 : 0x20), + AtapiWritePortEx4(chan, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0),(Channel ? 0x24 : 0x20), 0 ); } @@ -1083,18 +1083,18 @@ apiomode = 4; for(i=udmamode; i>=0; i--) { if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) { - AtapiWritePortEx4(chan, PtrToUlong(&deviceExtension->BaseIoAddressBM_0), mode_reg, cyr_udmatiming[udmamode]); + AtapiWritePortEx4(chan, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0), mode_reg, cyr_udmatiming[udmamode]); return; } } for(i=wdmamode; i>=0; i--) { if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) { - AtapiWritePortEx4(chan, PtrToUlong(&deviceExtension->BaseIoAddressBM_0), mode_reg, cyr_wdmatiming[wdmamode]); + AtapiWritePortEx4(chan, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0), mode_reg, cyr_wdmatiming[wdmamode]); return; } } if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode)) { - AtapiWritePortEx4(chan, PtrToUlong(&deviceExtension->BaseIoAddressBM_0), mode_reg, cyr_piotiming[apiomode]); + AtapiWritePortEx4(chan, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0), mode_reg, cyr_piotiming[apiomode]); return; } return; @@ -1837,8 +1837,8 @@ case ATA_WDMA2: reg24 = 0x00002020; break; case ATA_UDMA2: reg24 = 0x00911030; break; } - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),(dev*8) + 0x20, reg20); - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),(dev*8) + 0x24, reg24); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0),(dev*8) + 0x20, reg20); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0),(dev*8) + 0x24, reg24); } // cyrix_timing()
VOID
Modified: branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_init.cpp URL: http://svn.reactos.org/svn/reactos/branches/ros-amd64-bringup/reactos/driver... ============================================================================== --- branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_init.cpp [iso-8859-1] (original) +++ branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_init.cpp [iso-8859-1] Thu Dec 17 15:35:25 2009 @@ -1526,17 +1526,17 @@ KdPrint2((PRINT_PREFIX "BaseIoAddressSATA_0=%x\n", deviceExtension->BaseIoAddressSATA_0.Addr)); if(ChipFlags & NVQ) { /* clear interrupt status */ - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),offs, 0x00ff00ff); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs, 0x00ff00ff); /* enable device and PHY state change interrupts */ - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),offs+4, 0x000d000d); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs+4, 0x000d000d); /* disable NCQ support */ - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),0x0400, - AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),0x0400) & 0xfffffff9); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0400, + AtapiReadPortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0400) & 0xfffffff9); } else { /* clear interrupt status */ - AtapiWritePortEx1(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),offs, 0xff); + AtapiWritePortEx1(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs, 0xff); /* enable device and PHY state change interrupts */ - AtapiWritePortEx1(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),offs+1, 0xdd); + AtapiWritePortEx1(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs+1, 0xdd); } /* enable PCI interrupt */ ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400)); @@ -1567,16 +1567,16 @@ /* setup clocks */ if(c == CHAN_NOT_SPECIFIED) { // ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); - AtapiWritePortEx1(NULL, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),0x11, - AtapiReadPortEx1(NULL, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),0x11) | 0x0a ); + AtapiWritePortEx1(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11, + AtapiReadPortEx1(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11) | 0x0a ); } /* FALLTHROUGH */ case PROLD: /* enable burst mode */ // ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); if(c == CHAN_NOT_SPECIFIED) { - AtapiWritePortEx1(NULL, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),0x1f, - AtapiReadPortEx1(NULL, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),0x1f) | 0x01 ); + AtapiWritePortEx1(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0),0x1f, + AtapiReadPortEx1(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0),0x1f) | 0x01 ); } else { // check 80-pin cable chan = &deviceExtension->chan[c]; @@ -1601,7 +1601,7 @@ case PRMIO: if(c == CHAN_NOT_SPECIFIED) { if(ChipFlags & PRSATA) { - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressBM_0),0x6c, 0x000000ff); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressBM_0),0x6c, 0x000000ff); } } else { chan = &deviceExtension->chan[c]; @@ -1680,16 +1680,16 @@ unit10 = (c & 2); if(ChipFlags & SIINOSATAIRQ) { KdPrint2((PRINT_PREFIX "Disable broken SATA intr on c=%x\n", c)); - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),0); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),0); } } } else { if(ChipFlags & SIINOSATAIRQ) { KdPrint2((PRINT_PREFIX "Disable broken SATA intr on c=%x\n", c)); - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),0); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),0); } else { KdPrint2((PRINT_PREFIX "Enable SATA intr on c=%x\n", c)); - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); } } } @@ -1699,16 +1699,16 @@ // Enable 3rd and 4th channels if (ChipFlags & SII4CH) { KdPrint2((PRINT_PREFIX "SII4CH\n")); - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),0x0200, 0x00000002); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0200, 0x00000002); } } else { chan = &deviceExtension->chan[c]; /* dont block interrupts */ //ChangePciConfig4(0x48, (a & ~0x03c00000)); - tmp32 = AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),0x48); - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),0x48, (1 << 22) << c); + tmp32 = AtapiReadPortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48, (1 << 22) << c); // flush - tmp32 = AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAddressSATA_0),0x48); + tmp32 = AtapiReadPortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48);
/* Initialize FIFO PCI bus arbitration */ GetPciConfig1(offsetof(PCI_COMMON_CONFIG, CacheLineSize), tmp8);
Modified: branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_sata.cpp URL: http://svn.reactos.org/svn/reactos/branches/ros-amd64-bringup/reactos/driver... ============================================================================== --- branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_sata.cpp [iso-8859-1] (original) +++ branches/ros-amd64-bringup/reactos/drivers/storage/ide/uniata/id_sata.cpp [iso-8859-1] Thu Dec 17 15:35:25 2009 @@ -218,20 +218,20 @@ ULONGLONG base;
/* reset AHCI controller */ - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC, - AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC) | AHCI_GHC_HR); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC, + AtapiReadPortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC) | AHCI_GHC_HR); AtapiStallExecution(1000000); - if(AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC) & AHCI_GHC_HR) { + if(AtapiReadPortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC) & AHCI_GHC_HR) { KdPrint2((PRINT_PREFIX " AHCI reset failed\n")); return FALSE; }
/* enable AHCI mode */ - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC, - AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC) | AHCI_GHC_AE); - - CAP = AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_CAP); - PI = AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_PI); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC, + AtapiReadPortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC) | AHCI_GHC_AE); + + CAP = AtapiReadPortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_CAP); + PI = AtapiReadPortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_PI); /* get the number of HW channels */ for(i=PI, n=0; i; n++, i=i>>1); deviceExtension->NumberChannels = @@ -242,14 +242,14 @@ }
/* clear interrupts */ - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_IS, - AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_IS)); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_IS, + AtapiReadPortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_IS));
/* enable AHCI interrupts */ - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC, - AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC) | AHCI_GHC_IE); - - version = AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_VS); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC, + AtapiReadPortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_GHC) | AHCI_GHC_IE); + + version = AtapiReadPortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_VS); KdPrint2((PRINT_PREFIX " AHCI version %x%x.%x%x controller with %d ports (mask %x) detected\n", (version >> 24) & 0xff, (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff, deviceExtension->NumberChannels, PI)); @@ -295,15 +295,15 @@ KdPrint2((PRINT_PREFIX " AHCI buffer allocation failed\n")); return FALSE; } - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), offs + IDX_AHCI_P_CLB, + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), offs + IDX_AHCI_P_CLB, (ULONG)(base & 0xffffffff)); - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), offs + IDX_AHCI_P_CLB + 4, + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), offs + IDX_AHCI_P_CLB + 4, (ULONG)((base >> 32) & 0xffffffff));
base = chan->AHCI_CL_PhAddr + ATA_AHCI_MAX_TAGS; - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), offs + IDX_AHCI_P_FB, + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), offs + IDX_AHCI_P_FB, (ULONG)(base & 0xffffffff)); - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), offs + IDX_AHCI_P_FB + 4, + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), offs + IDX_AHCI_P_FB + 4, (ULONG)((base >> 32) & 0xffffffff));
chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE; @@ -333,7 +333,7 @@
KdPrint(("UniataAhciStatus:\n"));
- hIS = AtapiReadPortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_IS); + hIS = AtapiReadPortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_IS); KdPrint((" hIS %x\n", hIS)); hIS &= (1 << Channel); if(!hIS) { @@ -346,7 +346,7 @@ SError.Reg = AtapiReadPort4(chan, IDX_SATA_SError);
/* clear interrupt(s) */ - AtapiWritePortEx4(NULL, PtrToUlong(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_IS, hIS); + AtapiWritePortEx4(NULL, (ULONG_PTR)(&deviceExtension->BaseIoAHCI_0), IDX_AHCI_IS, hIS); AtapiWritePort4(chan, base + IDX_AHCI_P_IS, IS.Reg); AtapiWritePort4(chan, IDX_SATA_SError, SError.Reg);
-
sserapion＠svn.reactos.org