[rgampa] 75644: [USBXHCI] - changed usnxhci.c , usbxhci.h, hardware.h, roothub.c following reactos coding style. CORE-13344
Author: rgampa Date: Wed Aug 23 07:03:27 2017 New Revision: 75644
URL: http://svn.reactos.org/svn/reactos?rev=75644&view=rev Log: [USBXHCI] - changed usnxhci.c , usbxhci.h, hardware.h, roothub.c following reactos coding style. CORE-13344
Modified: branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/hardware.h branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/roothub.c branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.c branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.h
Modified: branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/hardware.h URL: http://svn.reactos.org/svn/reactos/branches/GSoC_2017/usbxhci/reactos/driver... ============================================================================== --- branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/hardware.h [iso-8859-1] (original) +++ branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/hardware.h [iso-8859-1] Wed Aug 23 07:03:27 2017 @@ -24,215 +24,250 @@ #define XHCI_ERSTDP 14
-typedef volatile union _XHCI_CAPLENGHT_INTERFACE_VERSION { - struct { - ULONG CapabilityRegistersLength : 8; - ULONG Rsvd : 8; - ULONG HostControllerInterfaceVersion : 16; - }; - ULONG AsULONG; +typedef volatile union _XHCI_CAPLENGHT_INTERFACE_VERSION +{ + struct + { + ULONG CapabilityRegistersLength : 8; + ULONG Rsvd : 8; + ULONG HostControllerInterfaceVersion : 16; + }; + ULONG AsULONG; } XHCI_CAPLENGHT_INTERFACE_VERSION;
-typedef volatile union _XHCI_HC_STRUCTURAL_PARAMS_1 { - struct { - ULONG NumberOfDeviceSlots : 8; // MAXSLOTS - ULONG NumberOfInterrupters : 11; // MAXINTRS - ULONG Rsvd : 5; - ULONG NumberOfPorts : 8; //MAXPORTS - }; - ULONG AsULONG; +typedef volatile union _XHCI_HC_STRUCTURAL_PARAMS_1 +{ + struct + { + ULONG NumberOfDeviceSlots : 8; // MAXSLOTS + ULONG NumberOfInterrupters : 11; // MAXINTRS + ULONG Rsvd : 5; + ULONG NumberOfPorts : 8; //MAXPORTS + }; + ULONG AsULONG; } XHCI_HC_STRUCTURAL_PARAMS_1;
-typedef volatile union _XHCI_HC_STRUCTURAL_PARAMS_2 { - struct { - ULONG Ist : 4; // Isochronous Scheduling Treshold - ULONG ERSTMax : 4; //Even ring segment table max - ULONG Rsvd : 13; - ULONG MaxSPBuffersHi : 5; //Max Scratchpad buffers high - ULONG SPR : 1; //Scratchpad Restore - ULONG MaxSPBuffersLo : 5; //Max Scratchpad buffers Low - }; - ULONG AsULONG; +typedef volatile union _XHCI_HC_STRUCTURAL_PARAMS_2 +{ + struct + { + ULONG Ist : 4; // Isochronous Scheduling Treshold + ULONG ERSTMax : 4; //Even ring segment table max + ULONG Rsvd : 13; + ULONG MaxSPBuffersHi : 5; //Max Scratchpad buffers high + ULONG SPR : 1; //Scratchpad Restore + ULONG MaxSPBuffersLo : 5; //Max Scratchpad buffers Low + }; + ULONG AsULONG; } XHCI_HC_STRUCTURAL_PARAMS_2;
-typedef volatile union _XHCI_HC_STRUCTURAL_PARAMS_3 { - struct { - ULONG U1DeviceExitLatecy : 8; - ULONG Rsvd : 8; - ULONG U2DeviceExitLatecy : 16; - }; - ULONG AsULONG; +typedef volatile union _XHCI_HC_STRUCTURAL_PARAMS_3 +{ + struct + { + ULONG U1DeviceExitLatecy : 8; + ULONG Rsvd : 8; + ULONG U2DeviceExitLatecy : 16; + }; + ULONG AsULONG; } XHCI_HC_STRUCTURAL_PARAMS_3;
-typedef volatile union _XHCI_HC_CAPABILITY_PARAMS_1 { // need to comment full forms, pg 291 in xHCI documentation - struct { - ULONG AC64 : 1; - ULONG BNC : 1; - ULONG CSZ : 1; - ULONG PPC : 1; - ULONG PIND : 1; - ULONG LHRC : 1; - ULONG LTC : 1; - ULONG NSS : 1; - ULONG PAE : 1; - ULONG SPC : 1; - ULONG SEC : 1; - ULONG CFC : 1; - ULONG MaxPSASize : 4; - ULONG xECP : 16; - }; - ULONG AsULONG; +typedef volatile union _XHCI_HC_CAPABILITY_PARAMS_1 +{ // need to comment full forms, pg 291 in xHCI documentation + struct + { + ULONG AC64 : 1; + ULONG BNC : 1; + ULONG CSZ : 1; + ULONG PPC : 1; + ULONG PIND : 1; + ULONG LHRC : 1; + ULONG LTC : 1; + ULONG NSS : 1; + ULONG PAE : 1; + ULONG SPC : 1; + ULONG SEC : 1; + ULONG CFC : 1; + ULONG MaxPSASize : 4; + ULONG xECP : 16; + }; + ULONG AsULONG; } XHCI_HC_CAPABILITY_PARAMS_1;
-typedef volatile union _XHCI_DOORBELL_OFFSET { - struct { - ULONG Rsvd : 2; - ULONG DBArrayOffset : 30; - }; - ULONG AsULONG; +typedef volatile union _XHCI_DOORBELL_OFFSET +{ + struct + { + ULONG Rsvd : 2; + ULONG DBArrayOffset : 30; + }; + ULONG AsULONG; } XHCI_DOORBELL_OFFSET;
-typedef volatile union _XHCI_RT_REGISTER_SPACE_OFFSET { //RUNTIME REGISTER SPACE OFFSET - struct { - ULONG Rsvd : 5; - ULONG RTSOffset : 27; - }; - ULONG AsULONG; +typedef volatile union _XHCI_RT_REGISTER_SPACE_OFFSET +{ //RUNTIME REGISTER SPACE OFFSET + struct { + ULONG Rsvd : 5; + ULONG RTSOffset : 27; + }; + ULONG AsULONG; } XHCI_RT_REGISTER_SPACE_OFFSET;
-typedef volatile union _XHCI_HC_CAPABILITY_PARAMS_2 { - struct { - ULONG U3C : 1; - ULONG CMC : 1; - ULONG FSC : 1; - ULONG CTC : 1; - ULONG LEC : 1; - ULONG CIC : 1; - ULONG Rsvd : 26; - }; - ULONG AsULONG; +typedef volatile union _XHCI_HC_CAPABILITY_PARAMS_2 +{ + struct + { + ULONG U3C : 1; + ULONG CMC : 1; + ULONG FSC : 1; + ULONG CTC : 1; + ULONG LEC : 1; + ULONG CIC : 1; + ULONG Rsvd : 26; + }; + ULONG AsULONG; } XHCI_HC_CAPABILITY_PARAMS_2;
-typedef volatile union _XHCI_USB_COMMAND { - struct { - ULONG RunStop : 1; - ULONG HCReset : 1; - ULONG InterrupterEnable : 1; - ULONG HostSystemErrorEnable : 1; - ULONG RsvdP1 : 3; - ULONG LightHCReset : 1; - ULONG ControllerSaveState : 1; - ULONG ControllerRestoreState : 1; - ULONG EnableWrapEvent : 1; - ULONG EnableU3Stop : 1; - ULONG RsvdP2 : 1; - ULONG CEMEnable : 1; - ULONG RsvdP3 : 18; - }; - ULONG AsULONG; +typedef volatile union _XHCI_USB_COMMAND +{ + struct + { + ULONG RunStop : 1; + ULONG HCReset : 1; + ULONG InterrupterEnable : 1; + ULONG HostSystemErrorEnable : 1; + ULONG RsvdP1 : 3; + ULONG LightHCReset : 1; + ULONG ControllerSaveState : 1; + ULONG ControllerRestoreState : 1; + ULONG EnableWrapEvent : 1; + ULONG EnableU3Stop : 1; + ULONG RsvdP2 : 1; + ULONG CEMEnable : 1; + ULONG RsvdP3 : 18; + }; + ULONG AsULONG; } XHCI_USB_COMMAND; -C_ASSERT(sizeof(XHCI_USB_COMMAND)==sizeof(ULONG)); -typedef volatile union _XHCI_USB_STATUS { - struct { - ULONG HCHalted : 1; - ULONG RsvdZ1 : 1; - ULONG HostSystemError : 1; - ULONG EventInterrupt : 1; - ULONG PortChangeDetect : 1; - ULONG RsvdZ2 : 3; - ULONG SaveStateStatus : 1; - ULONG RestoreStateStatus : 1; - ULONG SaveRestoreError : 1; - ULONG ControllerNotReady : 1; - ULONG HCError : 1; - ULONG RsvdZ3 : 19; - }; - ULONG AsULONG; +C_ASSERT(sizeof(XHCI_USB_COMMAND) == sizeof(ULONG)); + +typedef volatile union _XHCI_USB_STATUS +{ + struct + { + ULONG HCHalted : 1; + ULONG RsvdZ1 : 1; + ULONG HostSystemError : 1; + ULONG EventInterrupt : 1; + ULONG PortChangeDetect : 1; + ULONG RsvdZ2 : 3; + ULONG SaveStateStatus : 1; + ULONG RestoreStateStatus : 1; + ULONG SaveRestoreError : 1; + ULONG ControllerNotReady : 1; + ULONG HCError : 1; + ULONG RsvdZ3 : 19; + }; + ULONG AsULONG; } XHCI_USB_STATUS; -C_ASSERT(sizeof(XHCI_USB_STATUS)==sizeof(ULONG)); -typedef volatile union _XHCI_PAGE_SIZE { - struct { - ULONG PageSize : 16; - ULONG Rsvd : 16; - }; - ULONG AsULONG; +C_ASSERT(sizeof(XHCI_USB_STATUS) == sizeof(ULONG)); + +typedef volatile union _XHCI_PAGE_SIZE +{ + struct + { + ULONG PageSize : 16; + ULONG Rsvd : 16; + }; + ULONG AsULONG; } XHCI_PAGE_SIZE;
-typedef volatile union _XHCI_DEVICE_NOTIFICATION_CONTROL { - struct { - ULONG NotificationEnable : 16; - ULONG Rsvd : 16; - }; - ULONG AsULONG; +typedef volatile union _XHCI_DEVICE_NOTIFICATION_CONTROL +{ + struct + { + ULONG NotificationEnable : 16; + ULONG Rsvd : 16; + }; + ULONG AsULONG; } XHCI_DEVICE_NOTIFICATION_CONTROL;
-typedef volatile union _XHCI_COMMAND_RING_CONTROL { - struct { - ULONGLONG RingCycleState : 1; - ULONGLONG CommandStop : 1; - ULONGLONG CommandAbort : 1; - ULONGLONG CommandRingRunning : 1; - ULONGLONG RsvdP : 2; - ULONGLONG CommandRingPointerLo : 26; - ULONGLONG CommandRingPointerHi : 32; - }; - ULONGLONG AsULONGLONG; +typedef volatile union _XHCI_COMMAND_RING_CONTROL +{ + struct + { + ULONGLONG RingCycleState : 1; + ULONGLONG CommandStop : 1; + ULONGLONG CommandAbort : 1; + ULONGLONG CommandRingRunning : 1; + ULONGLONG RsvdP : 2; + ULONGLONG CommandRingPointerLo : 26; + ULONGLONG CommandRingPointerHi : 32; + }; + ULONGLONG AsULONGLONG; } XHCI_COMMAND_RING_CONTROL;
-typedef volatile union _XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY_POINTER { - struct { - ULONGLONG RsvdZ : 6; - ULONGLONG DCBAAPointerLo : 26; - ULONGLONG DCBAAPointerHi : 32; - }; - ULONGLONG AsULONGLONG; +typedef volatile union _XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY_POINTER +{ + struct + { + ULONGLONG RsvdZ : 6; + ULONGLONG DCBAAPointerLo : 26; + ULONGLONG DCBAAPointerHi : 32; + }; + ULONGLONG AsULONGLONG; } XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY_POINTER;
-typedef volatile union _XHCI_CONFIGURE { - struct { - ULONG MaxDeviceSlotsEnabled : 8; - ULONG U3EntryEnable : 1; - ULONG ConfigurationInfoEnable : 1; - ULONG Rsvd : 22; - }; - ULONG AsULONG; +typedef volatile union _XHCI_CONFIGURE +{ + struct + { + ULONG MaxDeviceSlotsEnabled : 8; + ULONG U3EntryEnable : 1; + ULONG ConfigurationInfoEnable : 1; + ULONG Rsvd : 22; + }; + ULONG AsULONG; } XHCI_CONFIGURE; C_ASSERT(sizeof(XHCI_CONFIGURE) == sizeof(ULONG));
#define PORT_STATUS_MASK 0x4F01FFE9 // 0100 1111 0000 0001 1111 1111 1110 1001 // RW 1, RW1C/RW1S 0, RO 1 -typedef volatile union _XHCI_PORT_STATUS_CONTROL { - struct { - ULONG CurrentConnectStatus : 1; - ULONG PortEnableDisable : 1; - ULONG RsvdZ1 : 1; - ULONG OverCurrentActive : 1; - ULONG PortReset : 1; - ULONG PortLinkState : 4; - ULONG PortPower : 1; - ULONG PortSpeed : 4; - ULONG PortIndicatorControl : 2; - ULONG LinkWriteStrobe : 1; - ULONG ConnectStatusChange : 1; - ULONG PortEnableDisableChange : 1; - ULONG WarmResetChange : 1; - ULONG OverCurrentChange : 1; - ULONG PortResetChange : 1; - ULONG PortLinkStateChange : 1; - ULONG ConfigErrorChange : 1; - ULONG ColdAttachStatus : 1; - ULONG WakeONConnectEnable : 1; - ULONG WakeONDisconnectEnable : 1; - ULONG WakeONOverCurrentEnable : 1; - ULONG RsvdZ2 : 2; - ULONG DeviceRemovable : 1; - ULONG WarmPortReset : 1; - }; - ULONG AsULONG; +typedef volatile union _XHCI_PORT_STATUS_CONTROL +{ + struct + { + ULONG CurrentConnectStatus : 1; + ULONG PortEnableDisable : 1; + ULONG RsvdZ1 : 1; + ULONG OverCurrentActive : 1; + ULONG PortReset : 1; + ULONG PortLinkState : 4; + ULONG PortPower : 1; + ULONG PortSpeed : 4; + ULONG PortIndicatorControl : 2; + ULONG LinkWriteStrobe : 1; + ULONG ConnectStatusChange : 1; + ULONG PortEnableDisableChange : 1; + ULONG WarmResetChange : 1; + ULONG OverCurrentChange : 1; + ULONG PortResetChange : 1; + ULONG PortLinkStateChange : 1; + ULONG ConfigErrorChange : 1; + ULONG ColdAttachStatus : 1; + ULONG WakeONConnectEnable : 1; + ULONG WakeONDisconnectEnable : 1; + ULONG WakeONOverCurrentEnable : 1; + ULONG RsvdZ2 : 2; + ULONG DeviceRemovable : 1; + ULONG WarmPortReset : 1; + }; + ULONG AsULONG; } XHCI_PORT_STATUS_CONTROL;
// Interrupt Register Set -typedef volatile union _XHCI_INTERRUPTER_MANAGEMENT { - struct { +typedef volatile union _XHCI_INTERRUPTER_MANAGEMENT +{ + struct + { ULONG InterruptPending : 1; ULONG InterruptEnable : 1; ULONG RsvdP : 30; @@ -240,45 +275,55 @@ ULONG AsULONG; } XHCI_INTERRUPTER_MANAGEMENT;
-typedef volatile union _XHCI_INTERRUPTER_MODERATION { - struct { +typedef volatile union _XHCI_INTERRUPTER_MODERATION +{ + struct + { ULONG InterruptModIterval : 16; ULONG InterruptModCounter : 16; }; ULONG AsULONG; } XHCI_INTERRUPTER_MODERATION;
-typedef volatile union _XHCI_EVENT_RING_TABLE_SIZE { - struct { +typedef volatile union _XHCI_EVENT_RING_TABLE_SIZE +{ + struct + { ULONG EventRingSegTableSize : 16; ULONG RsvdP : 16; }; ULONG AsULONG; } XHCI_EVENT_RING_TABLE_SIZE;
-typedef volatile union _XHCI_EVENT_RING_TABLE_BASE_ADDR { - struct { - ULONGLONG RsvdP : 6; - ULONGLONG EventRingSegTableBaseAddr : 58; - }; - ULONGLONG AsULONGLONG; +typedef volatile union _XHCI_EVENT_RING_TABLE_BASE_ADDR +{ + struct + { + ULONGLONG RsvdP : 6; + ULONGLONG EventRingSegTableBaseAddr : 58; + }; + ULONGLONG AsULONGLONG; } XHCI_EVENT_RING_TABLE_BASE_ADDR;
-typedef volatile union _XHCI_EVENT_RING_DEQUEUE_POINTER { - struct { - ULONGLONG DequeueERSTIndex : 3; - ULONGLONG EventHandlerBusy : 1; - ULONGLONG EventRingSegDequeuePointer : 60; - }; - ULONGLONG AsULONGLONG; +typedef volatile union _XHCI_EVENT_RING_DEQUEUE_POINTER +{ + struct + { + ULONGLONG DequeueERSTIndex : 3; + ULONGLONG EventHandlerBusy : 1; + ULONGLONG EventRingSegDequeuePointer : 60; + }; + ULONGLONG AsULONGLONG; } XHCI_EVENT_RING_DEQUEUE_POINTER;
// Doorbell register -typedef volatile union _XHCI_DOORBELL { - struct { - ULONG DoorBellTarget : 8; - ULONG RsvdZ : 8; - ULONG DoorbellStreamID : 16; - }; - ULONG AsULONG; +typedef volatile union _XHCI_DOORBELL +{ + struct + { + ULONG DoorBellTarget : 8; + ULONG RsvdZ : 8; + ULONG DoorbellStreamID : 16; + }; + ULONG AsULONG; } XHCI_DOORBELL;
Modified: branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/roothub.c URL: http://svn.reactos.org/svn/reactos/branches/GSoC_2017/usbxhci/reactos/driver... ============================================================================== --- branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/roothub.c [iso-8859-1] (original) +++ branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/roothub.c [iso-8859-1] Wed Aug 23 07:03:27 2017 @@ -1,8 +1,6 @@ #include "usbxhci.h" - //#define NDEBUG #include <debug.h> - #define NDEBUG_XHCI_ROOT_HUB #include "dbg_xhci.h"
@@ -31,7 +29,6 @@ Over-current Protection Mode: Global Over-current Protection. */ RootHubData->HubCharacteristics &= 3; - RootHubData->PowerOnToPowerGood = 2; RootHubData->HubControlCurrent = 0; } @@ -52,7 +49,7 @@ IN USHORT Port, IN PULONG PortStatus) { - //DPRINT1("XHCI_RH_GetPortStatus: function initiated\n"); + //DPRINT1("XHCI_RH_GetPortStatus: function initiated\n"); commented to remove too many windbg outputs PXHCI_EXTENSION XhciExtension; PULONG PortStatusRegPointer; XHCI_PORT_STATUS_CONTROL PortStatusRegister; @@ -61,9 +58,8 @@ XhciExtension = (PXHCI_EXTENSION)xhciExtension; ASSERT(Port != 0 && Port <= XhciExtension->NumberOfPorts); PortStatusRegPointer = (XhciExtension->OperationalRegs) + (XHCI_PORTSC + (Port - 1)*4); - PortStatusRegister.AsULONG = READ_REGISTER_ULONG(PortStatusRegPointer) ; - //DPRINT("XHCI_RH_GetPortStatus: Port - %i\n", Port); - //DPRINT("XHCI_RH_GetPortStatus: PortStatus Register, port - %p , %i\n", PortStatusRegister.AsULONG, Port); + PortStatusRegister.AsULONG = READ_REGISTER_ULONG(PortStatusRegPointer); + /* ULONG ConnectStatus : 1; // Current Connect Status ULONG EnableStatus : 1; // Port Enabled/Disabled @@ -124,9 +120,10 @@ portstatus.UsbPortStatus.ResetStatus = PortStatusRegister.PortReset; portstatus.UsbPortStatus.PowerStatus = PortStatusRegister.PortPower; portstatus.UsbPortStatus.LsDeviceAttached = 0;//PortStatusRegister.PortEnableDisable; - // if (PortStatusRegister.PortSpeed) { + // if (PortStatusRegister.PortSpeed) + //{ // this check is not needed in vmware. removed for testing. portstatus.UsbPortStatus.HsDeviceAttached = PortStatusRegister.CurrentConnectStatus; - // } + //} portstatus.UsbPortStatus.TestMode = 0;//PortStatusRegister.PortPower; portstatus.UsbPortStatus.IndicatorControl = 0;//PortStatusRegister.PortIndicatorControl;
@@ -139,11 +136,8 @@ portstatus.UsbPortStatusChange.LsDeviceAttachedChange = 0;//PortStatusRegister.ConnectStatusChange; portstatus.UsbPortStatusChange.HsDeviceAttachedChange = PortStatusRegister.ConnectStatusChange; portstatus.UsbPortStatusChange.TestModeChange = 0;//PortStatusRegister.ConnectStatusChange; - portstatus.UsbPortStatusChange.IndicatorControlChange =0;// PortStatusRegister.ConnectStatusChange; - - - //DPRINT("XHCI_RH_GetPortStatus: PortStatus - %p\n", portstatus.AsULONG); - + portstatus.UsbPortStatusChange.IndicatorControlChange = 0;// PortStatusRegister.ConnectStatusChange; + *PortStatus = portstatus.AsULONG;
return MP_STATUS_SUCCESS; @@ -154,7 +148,7 @@ XHCI_RH_GetHubStatus(IN PVOID xhciExtension, IN PULONG HubStatus) { - //DPRINT1("XHCI_RH_GetHubStatus: function initiated\n"); + //DPRINT1("XHCI_RH_GetHubStatus: function initiated\n"); //removed to reduce windbg output *HubStatus = 0; return 0; } @@ -190,14 +184,13 @@ XhciExtension = (PXHCI_EXTENSION)xhciExtension; ASSERT(Port != 0 && Port <= XhciExtension->NumberOfPorts); PortStatusRegPointer = (XhciExtension->OperationalRegs) + (XHCI_PORTSC + (Port - 1)*4); - PortStatusRegister.AsULONG = READ_REGISTER_ULONG(PortStatusRegPointer) ; + PortStatusRegister.AsULONG = READ_REGISTER_ULONG(PortStatusRegPointer);
PortStatusRegister.AsULONG = PortStatusRegister.AsULONG & PORT_STATUS_MASK; PortStatusRegister.PortReset = 1;
- WRITE_REGISTER_ULONG(PortStatusRegPointer , PortStatusRegister.AsULONG ); - - + WRITE_REGISTER_ULONG(PortStatusRegPointer, PortStatusRegister.AsULONG ); + return MP_STATUS_SUCCESS; }
@@ -214,12 +207,12 @@ XhciExtension = (PXHCI_EXTENSION)xhciExtension; ASSERT(Port != 0 && Port <= XhciExtension->NumberOfPorts); PortStatusRegPointer = (XhciExtension->OperationalRegs) + (XHCI_PORTSC + (Port - 1)*4); - PortStatusRegister.AsULONG = READ_REGISTER_ULONG(PortStatusRegPointer) ; + PortStatusRegister.AsULONG = READ_REGISTER_ULONG(PortStatusRegPointer);
PortStatusRegister.AsULONG = PortStatusRegister.AsULONG & PORT_STATUS_MASK; PortStatusRegister.PortPower = 1;
- WRITE_REGISTER_ULONG(PortStatusRegPointer , PortStatusRegister.AsULONG ); + WRITE_REGISTER_ULONG(PortStatusRegPointer, PortStatusRegister.AsULONG );
return MP_STATUS_SUCCESS; } @@ -259,7 +252,7 @@ PortStatusRegister.AsULONG = PortStatusRegister.AsULONG & PORT_STATUS_MASK; PortStatusRegister.PortEnableDisable = 1;
- WRITE_REGISTER_ULONG(PortStatusRegPointer , PortStatusRegister.AsULONG ); + WRITE_REGISTER_ULONG(PortStatusRegPointer, PortStatusRegister.AsULONG );
PortStatusRegister.AsULONG = READ_REGISTER_ULONG(PortStatusRegPointer) ;
@@ -273,7 +266,6 @@ IN USHORT Port) { DPRINT1("XHCI_RH_ClearFeaturePortPower: function initiated\n"); - return 0; }
@@ -316,12 +308,12 @@ XhciExtension = (PXHCI_EXTENSION)xhciExtension; ASSERT(Port != 0 && Port <= XhciExtension->NumberOfPorts); PortStatusRegPointer = (XhciExtension->OperationalRegs) + (XHCI_PORTSC + (Port - 1)*4); - PortStatusRegister.AsULONG = READ_REGISTER_ULONG(PortStatusRegPointer) ; + PortStatusRegister.AsULONG = READ_REGISTER_ULONG(PortStatusRegPointer);
PortStatusRegister.AsULONG = PortStatusRegister.AsULONG & PORT_STATUS_MASK; PortStatusRegister.ConnectStatusChange = 1;
- WRITE_REGISTER_ULONG(PortStatusRegPointer , PortStatusRegister.AsULONG ); + WRITE_REGISTER_ULONG(PortStatusRegPointer, PortStatusRegister.AsULONG );
PortStatusRegister.AsULONG = READ_REGISTER_ULONG(PortStatusRegPointer) ;
@@ -343,12 +335,12 @@ ASSERT(Port != 0 && Port <= XhciExtension->NumberOfPorts); PortStatusRegPointer = (XhciExtension->OperationalRegs) + (XHCI_PORTSC + (Port - 1)*4);
- PortStatusRegister.AsULONG = READ_REGISTER_ULONG(PortStatusRegPointer) ; + PortStatusRegister.AsULONG = READ_REGISTER_ULONG(PortStatusRegPointer);
PortStatusRegister.AsULONG = PortStatusRegister.AsULONG & PORT_STATUS_MASK; PortStatusRegister.PortResetChange = 1;
- WRITE_REGISTER_ULONG(PortStatusRegPointer , PortStatusRegister.AsULONG ); + WRITE_REGISTER_ULONG(PortStatusRegPointer, PortStatusRegister.AsULONG );
PortStatusRegister.AsULONG = READ_REGISTER_ULONG(PortStatusRegPointer) ;
@@ -378,37 +370,34 @@ NTAPI XHCI_RH_DisableIrq(IN PVOID xhciExtension) { - //DPRINT1("XHCI_RH_DisableIrq: function initiated\n"); + //DPRINT1("XHCI_RH_DisableIrq: function initiated\n"); removed to reduce windbg output PXHCI_EXTENSION XhciExtension; PULONG OperationalRegs; XHCI_USB_COMMAND usbCommand;
XhciExtension = (PXHCI_EXTENSION)xhciExtension; OperationalRegs = XhciExtension->OperationalRegs; - usbCommand.AsULONG =READ_REGISTER_ULONG (OperationalRegs + XHCI_USBCMD); + usbCommand.AsULONG =READ_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD);
usbCommand.InterrupterEnable = 0;
- WRITE_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD,usbCommand.AsULONG ); - //DPRINT1("XHCI_RH_DisableIrq: Disable Interupts succesfull\n"); + WRITE_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD,usbCommand.AsULONG); }
VOID NTAPI XHCI_RH_EnableIrq(IN PVOID xhciExtension) { - //DPRINT1("XHCI_RH_EnableIrq: function initiated\n"); + //DPRINT1("XHCI_RH_EnableIrq: function initiated\n"); removed to reduce windbg output PXHCI_EXTENSION XhciExtension; PULONG OperationalRegs; XHCI_USB_COMMAND usbCommand;
XhciExtension = (PXHCI_EXTENSION)xhciExtension; OperationalRegs = XhciExtension->OperationalRegs; - usbCommand.AsULONG =READ_REGISTER_ULONG (OperationalRegs + XHCI_USBCMD); + usbCommand.AsULONG =READ_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD);
usbCommand.InterrupterEnable = 1;
- WRITE_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD,usbCommand.AsULONG ); - //DPRINT1("XHCI_RH_EnableIrq: Enable Interupts\n"); - -} + WRITE_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD,usbCommand.AsULONG); +}
Modified: branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.c URL: http://svn.reactos.org/svn/reactos/branches/GSoC_2017/usbxhci/reactos/driver... ============================================================================== --- branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.c [iso-8859-1] (original) +++ branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.c [iso-8859-1] Wed Aug 23 07:03:27 2017 @@ -1,7 +1,5 @@ #include "usbxhci.h" - #include <debug.h> - #define NDEBUG_XHCI_TRACE #include "dbg_xhci.h"
@@ -9,12 +7,11 @@
VOID NTAPI -XHCI_Write64bitReg(IN PULONG baseAddr, - IN ULONGLONG data) -{ - //DPRINT1("XHCI_Write64bitReg: function initiated\n"); - WRITE_REGISTER_ULONG(baseAddr, data); - WRITE_REGISTER_ULONG(baseAddr+1, data >> 32); +XHCI_Write64bitReg(IN PULONG BaseAddr, + IN ULONGLONG Data) +{ + WRITE_REGISTER_ULONG(BaseAddr, Data); + WRITE_REGISTER_ULONG(BaseAddr + 1, Data >> 32); }
MPSTATUS @@ -95,6 +92,7 @@ { DPRINT1("XHCI_CloseEndpoint: UNIMPLEMENTED. FIXME\n"); } + MPSTATUS NTAPI XHCI_ProcessEvent (IN PXHCI_EXTENSION XhciExtension) @@ -112,34 +110,29 @@
RunTimeRegisterBase = XhciExtension-> RunTimeRegisterBase; dequeue_pointer = HcResourcesVA-> EventRing.dequeue_pointer; - /*DPRINT("XHCI_ProcessEvent: eventtrb 0 word0 - %p\n", HcResourcesVA->EventRing.firstSeg.XhciTrb[0].GenericTRB.Word0); - DPRINT("XHCI_ProcessEvent: eventtrb 0 word1 - %p\n", HcResourcesVA->EventRing.firstSeg.XhciTrb[0].GenericTRB.Word1); - DPRINT("XHCI_ProcessEvent: eventtrb 0 word2 - %p\n", HcResourcesVA->EventRing.firstSeg.XhciTrb[0].GenericTRB.Word2); - DPRINT("XHCI_ProcessEvent: eventtrb 0 word3 - %p\n", HcResourcesVA->EventRing.firstSeg.XhciTrb[0].GenericTRB.Word3); - DPRINT("XHCI_ProcessEvent: deque_ptr - %p\n", dequeue_pointer); - DPRINT("XHCI_ProcessEvent: base addr - %p\n", &(HcResourcesVA->EventRing.firstSeg.XhciTrb[0]));*/ - - while (TRUE) { + + while (TRUE) + { eventTRB = (*dequeue_pointer).EventTRB; - if (eventTRB.EventGenericTRB.CycleBit != HcResourcesVA-> EventRing.ConsumerCycleState){ + if (eventTRB.EventGenericTRB.CycleBit != HcResourcesVA->EventRing.ConsumerCycleState) + { DPRINT1("XHCI_ProcessEvent: cycle bit mismatch. end of processing\n"); - //DPRINT("XHCI_ProcessEvent: eventtrb word0 - %p\n", eventTRB.EventGenericTRB.Word0); - //DPRINT("XHCI_ProcessEvent: eventtrb word1 - %p\n", eventTRB.EventGenericTRB.Word1); - //DPRINT("XHCI_ProcessEvent: eventtrb word2 - %p\n", eventTRB.EventGenericTRB.Word2); - //DPRINT("XHCI_ProcessEvent: eventtrb cycle bit - %x\n", eventTRB.EventGenericTRB.CycleBit); break; } TRBType = eventTRB.EventGenericTRB.TRBType; - switch (TRBType){ + switch (TRBType) + { case TRANSFER_EVENT: DPRINT1("XHCI_ProcessEvent: TRANSFER_EVENT \n"); break; case COMMAND_COMPLETION_EVENT: DPRINT1("XHCI_ProcessEvent: COMMAND_COMPLETION_EVENT\n"); - if(eventTRB.CommandCompletionTRB.CompletionCode == SUCCESS){ + if (eventTRB.CommandCompletionTRB.CompletionCode == SUCCESS) + { DPRINT1("XHCI_ProcessEvent: COMMAND_COMPLETION_EVENT, successful command completion\n"); } - else DPRINT1("XHCI_ProcessEvent: COMMAND_COMPLETION_EVENT, unsuccessful command completion %i \n",eventTRB.CommandCompletionTRB.CompletionCode); + else DPRINT1("XHCI_ProcessEvent: COMMAND_COMPLETION_EVENT, unsuccessful command completion %i \n", + eventTRB.CommandCompletionTRB.CompletionCode); break; case PORT_STATUS_CHANGE_EVENT: DPRINT1("XHCI_ProcessEvent: Port Status change event\n"); @@ -160,29 +153,27 @@ DPRINT1("XHCI_ProcessEvent: MF_INDEX_WARP_EVENT\n"); break; default: - DPRINT1("XHCI_ProcessEvent: Unknown TRBType - %x\n", - TRBType); - DbgBreakPoint(); + DPRINT1("XHCI_ProcessEvent: Unknown TRBType - %x\n", + TRBType); + DbgBreakPoint(); break; } - if (dequeue_pointer == &(HcResourcesVA->EventRing.firstSeg.XhciTrb[255])){ - HcResourcesVA-> EventRing.ConsumerCycleState = ~(HcResourcesVA-> EventRing.ConsumerCycleState); - HcResourcesVA-> EventRing.ProducerCycleState = ~(HcResourcesVA-> EventRing.ProducerCycleState); + if (dequeue_pointer == &(HcResourcesVA->EventRing.firstSeg.XhciTrb[255])) + { + HcResourcesVA->EventRing.ConsumerCycleState = ~(HcResourcesVA->EventRing.ConsumerCycleState); + HcResourcesVA->EventRing.ProducerCycleState = ~(HcResourcesVA->EventRing.ProducerCycleState); dequeue_pointer = &(HcResourcesVA->EventRing.firstSeg.XhciTrb[0]); } dequeue_pointer = dequeue_pointer + 1; }
- //erstdp.AsULONGLONG = READ_REGISTER_ULONG(RunTimeRegisterBase + XHCI_ERSTDP + 1); - //erstdp.AsULONGLONG = erstdp.AsULONGLONG <<32; - //erstdp.AsULONGLONG = erstdp.AsULONGLONG + READ_REGISTER_ULONG(RunTimeRegisterBase + XHCI_ERSTDP); HcResourcesVA-> EventRing.dequeue_pointer = dequeue_pointer; HcResourcesVA-> EventRing.enqueue_pointer = dequeue_pointer;
erstdp.AsULONGLONG = HcResourcesPA.QuadPart + ((ULONG_PTR)dequeue_pointer - (ULONG_PTR)HcResourcesVA); ASSERT(erstdp.AsULONGLONG >= HcResourcesPA.QuadPart && erstdp.AsULONGLONG < HcResourcesPA.QuadPart + sizeof(XHCI_HC_RESOURCES)) ; - erstdp.DequeueERSTIndex =0; - XHCI_Write64bitReg (RunTimeRegisterBase + XHCI_ERSTDP, erstdp.AsULONGLONG); + erstdp.DequeueERSTIndex = 0; + XHCI_Write64bitReg(RunTimeRegisterBase + XHCI_ERSTDP, erstdp.AsULONGLONG); return MP_STATUS_SUCCESS; }
@@ -201,52 +192,54 @@ XHCI_TRB CheckLink; PHYSICAL_ADDRESS LinkPointer;
- HcResourcesVA = XhciExtension -> HcResourcesVA; - HcResourcesPA = XhciExtension -> HcResourcesPA; - enqueue_pointer = HcResourcesVA -> CommandRing.enqueue_pointer; - dequeue_pointer = HcResourcesVA -> CommandRing.dequeue_pointer; + HcResourcesVA = XhciExtension->HcResourcesVA; + HcResourcesPA = XhciExtension->HcResourcesPA; + enqueue_pointer = HcResourcesVA->CommandRing.enqueue_pointer; + dequeue_pointer = HcResourcesVA->CommandRing.dequeue_pointer; // check if ring is full - if ((enqueue_pointer + 1) == dequeue_pointer) { + if ((enqueue_pointer + 1) == dequeue_pointer) + { DPRINT1 ("XHCI_SendCommand : Command ring is full \n"); return MP_STATUS_FAILURE; } // check if the trb is link trb. CheckLink = *enqueue_pointer; - if (CheckLink.LinkTRB.TRBType == LINK){ + if (CheckLink.LinkTRB.TRBType == LINK) + { LinkPointer.QuadPart = CheckLink.GenericTRB.Word1; LinkPointer.QuadPart = LinkPointer.QuadPart << 32; LinkPointer.QuadPart = LinkPointer.QuadPart + CheckLink.GenericTRB.Word0; - ASSERT(LinkPointer.QuadPart >= HcResourcesPA.QuadPart && LinkPointer.QuadPart < HcResourcesPA.QuadPart + sizeof(XHCI_HC_RESOURCES)) ; + ASSERT(LinkPointer.QuadPart >= HcResourcesPA.QuadPart && LinkPointer.QuadPart < HcResourcesPA.QuadPart + sizeof(XHCI_HC_RESOURCES)); enqueue_pointer_prev = enqueue_pointer; enqueue_pointer = (PXHCI_TRB)(HcResourcesVA + LinkPointer.QuadPart - HcResourcesPA.QuadPart); - //enqueue_pointer = &(HcResourcesVA->CommandRing.firstSeg.XhciTrb[0]); - if ((enqueue_pointer == dequeue_pointer) || (enqueue_pointer == dequeue_pointer + 1)){ // it can't move ahead break out of function + if ((enqueue_pointer == dequeue_pointer) || (enqueue_pointer == dequeue_pointer + 1)) + { // it can't move ahead break out of function DPRINT1 ("XHCI_SendCommand : Command ring is full \n"); return MP_STATUS_FAILURE; - } - // now the link trb is valid. set its cycle state to Producer cycle state for the command ring to read + } + // now the link trb is valid. set its cycle state to Producer cycle state for the command ring to read CheckLink.LinkTRB.CycleBit = HcResourcesVA -> CommandRing.ProducerCycleState; // write the link trb back. *enqueue_pointer_prev = CheckLink; // now we can go ahead to the next pointer where we want to write the new trb. before that check and toggle if necessaary. - if (CheckLink.LinkTRB.ToggleCycle == 1){ - HcResourcesVA -> CommandRing.ProducerCycleState = ~ (HcResourcesVA -> CommandRing.ProducerCycleState); - //HcResourcesVA -> CommandRing.ConsumerCycleState = ~ (HcResourcesVA -> CommandRing.ConsumerCycleState); update this when the xHC reaches link trb + if (CheckLink.LinkTRB.ToggleCycle == 1) + { + HcResourcesVA -> CommandRing.ProducerCycleState = ~ (HcResourcesVA -> CommandRing.ProducerCycleState); //update this when the xHC reaches link trb } } // place trb on the command ring *enqueue_pointer = CommandTRB; - enqueue_pointer = enqueue_pointer+1; - HcResourcesVA -> CommandRing.enqueue_pointer = enqueue_pointer; + enqueue_pointer = enqueue_pointer + 1; + HcResourcesVA->CommandRing.enqueue_pointer = enqueue_pointer; // ring doorbell DoorBellRegisterBase = XhciExtension->DoorBellRegisterBase; Doorbell_0.DoorBellTarget = 0; Doorbell_0.RsvdZ = 0; Doorbell_0.AsULONG = 0; WRITE_REGISTER_ULONG(DoorBellRegisterBase, Doorbell_0.AsULONG); - - return MP_STATUS_SUCCESS; -} + return MP_STATUS_SUCCESS; +} + MPSTATUS NTAPI XHCI_ControllerWorkTest(IN PXHCI_EXTENSION XhciExtension, @@ -352,11 +345,12 @@ //DbgBreakPoint(); return MP_STATUS_SUCCESS; } + MPSTATUS NTAPI XHCI_InitializeResources(IN PXHCI_EXTENSION XhciExtension, - IN PVOID resourcesStartVA, - IN PVOID resourcesStartPA) + IN PVOID resourcesStartVA, + IN PVOID resourcesStartPA) { DPRINT1("XHCI_InitializeResources: function initiated\n");
@@ -368,16 +362,20 @@ USHORT MaxScratchPadBuffers;
PULONG RunTimeRegisterBase; - //XHCI_INTERRUPTER_MANAGEMENT Iman; - //XHCI_INTERRUPTER_MODERATION Imod; XHCI_EVENT_RING_TABLE_SIZE erstz; XHCI_EVENT_RING_TABLE_BASE_ADDR erstba; XHCI_EVENT_RING_DEQUEUE_POINTER erstdp; XHCI_EVENT_RING_SEGMENT_TABLE EventRingSegTable;
XHCI_COMMAND_RING_CONTROL CommandRingControlRegister, CommandRingControlRegister_temp; - XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY_POINTER DCBAAPointer; + XHCI_TRB CommandLinkTRB; + XHCI_LINK_ADDR RingStartAddr; + + PHYSICAL_ADDRESS Zero, Max; + PMDL ScratchPadArrayMDL; + PXHCI_SCRATCHPAD_BUFFER_ARRAY BufferArrayPointer; + PMDL ScratchPadBufferMDL;
DPRINT_XHCI("XHCI_InitializeResources: BaseVA - %p, BasePA - %p\n", resourcesStartVA, @@ -394,18 +392,19 @@
//DCBAA init DCBAAPointer.AsULONGLONG = HcResourcesPA.QuadPart + FIELD_OFFSET(XHCI_HC_RESOURCES, DCBAA); - DPRINT1("XHCI_InitializeResources : DCBAAPointer %p\n",DCBAAPointer.AsULONGLONG ); - - XHCI_Write64bitReg (OperationalRegs + XHCI_DCBAAP,DCBAAPointer.AsULONGLONG); + DPRINT1("XHCI_InitializeResources : DCBAAPointer %p\n", DCBAAPointer.AsULONGLONG ); + + XHCI_Write64bitReg(OperationalRegs + XHCI_DCBAAP, DCBAAPointer.AsULONGLONG);
// command ring intialisation. HcResourcesVA->CommandRing.enqueue_pointer = &(HcResourcesVA->CommandRing.firstSeg.XhciTrb[0]); HcResourcesVA->CommandRing.dequeue_pointer = &(HcResourcesVA->CommandRing.firstSeg.XhciTrb[0]); - for(int i=0; i<256; i++){ - HcResourcesVA->CommandRing.firstSeg.XhciTrb[i].GenericTRB.Word0=0; - HcResourcesVA->CommandRing.firstSeg.XhciTrb[i].GenericTRB.Word1=0; - HcResourcesVA->CommandRing.firstSeg.XhciTrb[i].GenericTRB.Word2=0; - HcResourcesVA->CommandRing.firstSeg.XhciTrb[i].GenericTRB.Word3=0; + for (int i=0; i<256; i++) + { + HcResourcesVA->CommandRing.firstSeg.XhciTrb[i].GenericTRB.Word0 = 0; + HcResourcesVA->CommandRing.firstSeg.XhciTrb[i].GenericTRB.Word1 = 0; + HcResourcesVA->CommandRing.firstSeg.XhciTrb[i].GenericTRB.Word2 = 0; + HcResourcesVA->CommandRing.firstSeg.XhciTrb[i].GenericTRB.Word3 = 0; } CommandRingControlRegister.AsULONGLONG = HcResourcesPA.QuadPart + FIELD_OFFSET(XHCI_HC_RESOURCES, CommandRing.firstSeg); CommandRingControlRegister_temp.AsULONGLONG = READ_REGISTER_ULONG(OperationalRegs + XHCI_CRCR + 1) | READ_REGISTER_ULONG(OperationalRegs + XHCI_CRCR); @@ -413,21 +412,20 @@ HcResourcesVA->CommandRing.ProducerCycleState = 1; HcResourcesVA->CommandRing.ConsumerCycleState = 1; CommandRingControlRegister.RsvdP = CommandRingControlRegister_temp.RsvdP; - DPRINT1("XHCI_InitializeResources : CommandRingControlRegister %p\n",CommandRingControlRegister.AsULONGLONG ); - XHCI_Write64bitReg (OperationalRegs + XHCI_CRCR, CommandRingControlRegister.AsULONGLONG); + DPRINT1("XHCI_InitializeResources : CommandRingControlRegister %p\n", CommandRingControlRegister.AsULONGLONG ); + XHCI_Write64bitReg(OperationalRegs + XHCI_CRCR, CommandRingControlRegister.AsULONGLONG);
// Place link trb with toggle cycle state in the last link trb. - XHCI_TRB CommandLinkTRB; + CommandLinkTRB.GenericTRB.Word0 = 0; CommandLinkTRB.GenericTRB.Word1 = 0; CommandLinkTRB.GenericTRB.Word2 = 0; CommandLinkTRB.GenericTRB.Word3 = 0; - XHCI_LINK_ADDR RingStartAddr;
RingStartAddr.AsULONGLONG = HcResourcesPA.QuadPart + FIELD_OFFSET(XHCI_HC_RESOURCES, CommandRing.firstSeg); - CommandLinkTRB.GenericTRB.RsvdZ1 = 0; //RingStartAddr & 0x00000000FFFFFFF0; // physical addr is needed. but recheck assignment + CommandLinkTRB.GenericTRB.RsvdZ1 = 0; CommandLinkTRB.LinkTRB.RingSegmentPointerLo = RingStartAddr.RingSegmentPointerLo; - CommandLinkTRB.LinkTRB.RingSegmentPointerHi = RingStartAddr.RingSegmentPointerHi; //(RingStartAddr & 0xFFFFFFFF00000000) >>32; + CommandLinkTRB.LinkTRB.RingSegmentPointerHi = RingStartAddr.RingSegmentPointerHi; CommandLinkTRB.LinkTRB.InterrupterTarget = 0; CommandLinkTRB.LinkTRB.CycleBit = ~(HcResourcesVA->CommandRing.ProducerCycleState); CommandLinkTRB.LinkTRB.ToggleCycle = 1; //impt @@ -444,8 +442,8 @@ // dont change imod now erstz.AsULONG = READ_REGISTER_ULONG(RunTimeRegisterBase + XHCI_ERSTSZ) ; erstz.EventRingSegTableSize = 1; - DPRINT1("XHCI_InitializeResources : erstz.AsULONG %p\n",erstz.AsULONG ); - WRITE_REGISTER_ULONG (RunTimeRegisterBase + XHCI_ERSTSZ , erstz.AsULONG); + DPRINT1("XHCI_InitializeResources : erstz.AsULONG %p\n", erstz.AsULONG ); + WRITE_REGISTER_ULONG(RunTimeRegisterBase + XHCI_ERSTSZ, erstz.AsULONG); // event ring dequeue pointer. erstdp.AsULONGLONG = HcResourcesPA.QuadPart + FIELD_OFFSET(XHCI_HC_RESOURCES, EventRing.firstSeg.XhciTrb[0]);
@@ -454,9 +452,9 @@
HcResourcesVA->EventRing.ProducerCycleState = 1; HcResourcesVA->EventRing.ConsumerCycleState = 1; - //ASSERT(erstdp.AsULONGLONG & 0x0F == 0); + erstdp.DequeueERSTIndex =0; - DPRINT1("XHCI_InitializeResources : erstdp.AsULONGLONG %p\n",erstdp.AsULONGLONG ); + DPRINT1("XHCI_InitializeResources : erstdp.AsULONGLONG %p\n", erstdp.AsULONGLONG ); XHCI_Write64bitReg(RunTimeRegisterBase + XHCI_ERSTDP, erstdp.AsULONGLONG); // event ring segment table base address array
@@ -465,72 +463,77 @@ EventRingSegTable.RingSegmentSize = 256; EventRingSegTable.RsvdZ = 0; HcResourcesVA->EventRingSegTable = EventRingSegTable; - DPRINT1("XHCI_InitializeResources : erstba.AsULONGLONG %p\n",erstba.AsULONGLONG ); + DPRINT1("XHCI_InitializeResources : erstba.AsULONGLONG %p\n", erstba.AsULONGLONG ); XHCI_Write64bitReg(RunTimeRegisterBase + XHCI_ERSTBA, erstba.AsULONGLONG); // intially enque and deque are equal.
- for(int i=0; i<256; i++){ - HcResourcesVA->EventRing.firstSeg.XhciTrb[i].GenericTRB.Word0=0; - HcResourcesVA->EventRing.firstSeg.XhciTrb[i].GenericTRB.Word1=0; - HcResourcesVA->EventRing.firstSeg.XhciTrb[i].GenericTRB.Word2=0; - HcResourcesVA->EventRing.firstSeg.XhciTrb[i].GenericTRB.Word3=0; + for (int i=0; i<256; i++) + { + HcResourcesVA->EventRing.firstSeg.XhciTrb[i].GenericTRB.Word0 = 0; + HcResourcesVA->EventRing.firstSeg.XhciTrb[i].GenericTRB.Word1 = 0; + HcResourcesVA->EventRing.firstSeg.XhciTrb[i].GenericTRB.Word2 = 0; + HcResourcesVA->EventRing.firstSeg.XhciTrb[i].GenericTRB.Word3 = 0; }
// check if the controller supports 4k page size or quit. PageSize = XhciExtension-> PageSize; MaxScratchPadBuffers = XhciExtension->MaxScratchPadBuffers;
- if (MaxScratchPadBuffers == 0){ // xHCI may declare 0 scratchpad arrays. if so there is no need for memory allocation. + if (MaxScratchPadBuffers == 0) + { // xHCI may declare 0 scratchpad arrays. if so there is no need for memory allocation. return MP_STATUS_SUCCESS; } //if ((PageSize & (1 << 0)) == 0){ // this is how it is implemented in Haiko - if ((PageSize & (1 << 0)) == 0) { + if ((PageSize & (1 << 0)) == 0) + { DPRINT1("XHCI_InitializeResources : fail. does not support 4k page size %p\n",PageSize); return MP_STATUS_FAILURE; } // allocate scratchpad buffer array - PHYSICAL_ADDRESS Zero, Max; + Zero.QuadPart = 0; Max.QuadPart = -1; - PMDL ScratchPadArrayMDL; - PXHCI_SCRATCHPAD_BUFFER_ARRAY BufferArrayPointer; - BufferArrayPointer = MmAllocateContiguousMemory (MaxScratchPadBuffers* sizeof(XHCI_SCRATCHPAD_BUFFER_ARRAY),Max); - if (BufferArrayPointer == NULL){ + + BufferArrayPointer = MmAllocateContiguousMemory(MaxScratchPadBuffers * sizeof(XHCI_SCRATCHPAD_BUFFER_ARRAY), Max); + if (BufferArrayPointer == NULL) + { DPRINT1("XHCI_InitializeResources : Scratch pad array ContiguousMemory allcoation fail NULL\n"); return MP_STATUS_FAILURE; } - ScratchPadArrayMDL = IoAllocateMdl(BufferArrayPointer, MaxScratchPadBuffers* sizeof(XHCI_SCRATCHPAD_BUFFER_ARRAY), FALSE, FALSE, NULL); - if (ScratchPadArrayMDL == NULL) { + ScratchPadArrayMDL = IoAllocateMdl(BufferArrayPointer, MaxScratchPadBuffers * sizeof(XHCI_SCRATCHPAD_BUFFER_ARRAY), FALSE, FALSE, NULL); + if (ScratchPadArrayMDL == NULL) + { DPRINT1("XHCI_InitializeResources : Scratch pad array could not be allocated. it is NULL\n"); MmFreeContiguousMemory(BufferArrayPointer); return MP_STATUS_FAILURE; } MmBuildMdlForNonPagedPool(ScratchPadArrayMDL);
- HcResourcesVA-> DCBAA.ContextBaseAddr[0].QuadPart = MmGetMdlPfnArray(ScratchPadArrayMDL)[0] << PAGE_SHIFT; + HcResourcesVA->DCBAA.ContextBaseAddr[0].QuadPart = MmGetMdlPfnArray(ScratchPadArrayMDL)[0] << PAGE_SHIFT; //allocate scratchpad buffers - PMDL ScratchPadBufferMDL; + ScratchPadBufferMDL = MmAllocatePagesForMdlEx(Zero, Max, Zero, MaxScratchPadBuffers*PAGE_SIZE, MmNonCached, 0); - if (ScratchPadBufferMDL == NULL) { + if (ScratchPadBufferMDL == NULL) + { IoFreeMdl(ScratchPadArrayMDL); MmFreeContiguousMemory(BufferArrayPointer); return MP_STATUS_FAILURE; } - if (MmGetMdlByteCount(ScratchPadBufferMDL) < MaxScratchPadBuffers*PAGE_SIZE) { + if (MmGetMdlByteCount(ScratchPadBufferMDL) < MaxScratchPadBuffers*PAGE_SIZE) + { MmFreePagesFromMdl(ScratchPadBufferMDL); ExFreePool(ScratchPadBufferMDL); - IoFreeMdl(ScratchPadArrayMDL); MmFreeContiguousMemory(BufferArrayPointer); return MP_STATUS_FAILURE; } - for (int i = 0; i < MaxScratchPadBuffers ; i++){ + for (int i = 0; i < MaxScratchPadBuffers ; i++) + { BufferArrayPointer[i].AsULONGLONG = MmGetMdlPfnArray(ScratchPadBufferMDL)[i] << PAGE_SHIFT; } XhciExtension-> ScratchPadArrayMDL = ScratchPadArrayMDL; XhciExtension-> ScratchPadBufferMDL = ScratchPadBufferMDL; - //DbgBreakPoint(); return MP_STATUS_SUCCESS; }
@@ -541,8 +544,6 @@ DPRINT1("XHCI_InitializeHardware: function initiated\n"); PULONG BaseIoAdress; PULONG OperationalRegs; - - XHCI_USB_COMMAND Command; XHCI_USB_STATUS Status; LARGE_INTEGER CurrentTime = {{0, 0}}; @@ -556,7 +557,7 @@ BaseIoAdress = XhciExtension->BaseIoAdress;
KeQuerySystemTime(&CurrentTime); - CurrentTime.QuadPart += 100 * 10000; // 100 msec + CurrentTime.QuadPart += 100 * 10000;
Status.AsULONG = READ_REGISTER_ULONG(OperationalRegs + XHCI_USBSTS); ASSERT(Status.ControllerNotReady != 1); // this is needed before writing anything to the operaational or doorbell registers @@ -564,7 +565,7 @@ Command.AsULONG = READ_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD); Command.HCReset = 1; WRITE_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD, Command.AsULONG); - while(TRUE) + while (TRUE) { KeQuerySystemTime(&LastTime);
@@ -578,7 +579,7 @@ if (LastTime.QuadPart >= CurrentTime.QuadPart) { DPRINT1("XHCI_InitializeHardware: Software Reset failed!\n"); - return 7; + return MP_STATUS_FAILURE; } } DPRINT("XHCI_InitializeHardware: Reset - OK\n"); @@ -589,7 +590,7 @@
Command.AsULONG = READ_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD); Config.AsULONG = READ_REGISTER_ULONG(OperationalRegs + XHCI_CONFIG); - ASSERT(Command.RunStop==0); //required before setting max device slots enabled. + ASSERT(Command.RunStop == 0); //required before setting max device slots enabled. Config.MaxDeviceSlotsEnabled = 1; // max possible value is number of slots HCSPARAMS1 Config.U3EntryEnable = 0; Config.ConfigurationInfoEnable = 0; @@ -635,26 +636,26 @@ XhciExtension->BaseIoAdress = BaseIoAdress;
CapLenReg.AsULONG = READ_REGISTER_ULONG(BaseIoAdress); - CapLenReg.Rsvd=0; - CapLenReg.HostControllerInterfaceVersion=0; - CapabilityRegLength= (UCHAR)CapLenReg.CapabilityRegistersLength ; + CapLenReg.Rsvd = 0; + CapLenReg.HostControllerInterfaceVersion = 0; + CapabilityRegLength = (UCHAR)CapLenReg.CapabilityRegistersLength; OperationalRegs = (PULONG)((ULONG_PTR)BaseIoAdress + CapabilityRegLength); XhciExtension->OperationalRegs = OperationalRegs;
DoorBellOffsetRegister.AsULONG = READ_REGISTER_ULONG(BaseIoAdress + XHCI_DBOFF); - DoorBellRegisterBase = (PULONG)((PBYTE)BaseIoAdress + DoorBellOffsetRegister.AsULONG ); + DoorBellRegisterBase = (PULONG)((PBYTE)BaseIoAdress + DoorBellOffsetRegister.AsULONG); XhciExtension->DoorBellRegisterBase = DoorBellRegisterBase;
RTSOffsetRegister.AsULONG = READ_REGISTER_ULONG(BaseIoAdress + XHCI_RTSOFF); - RunTimeRegisterBase = (PULONG)((PBYTE)BaseIoAdress + RTSOffsetRegister.AsULONG ); - XhciExtension->RunTimeRegisterBase = RunTimeRegisterBase ; + RunTimeRegisterBase = (PULONG)((PBYTE)BaseIoAdress + RTSOffsetRegister.AsULONG); + XhciExtension->RunTimeRegisterBase = RunTimeRegisterBase;
PageSizeReg.AsULONG = READ_REGISTER_ULONG(OperationalRegs + XHCI_PGSZ); XhciExtension->PageSize = PageSizeReg.PageSize; HCSPARAMS2.AsULONG = READ_REGISTER_ULONG(BaseIoAdress + XHCI_HCSP2); MaxScratchPadBuffers = 0; MaxScratchPadBuffers = HCSPARAMS2.MaxSPBuffersHi; - MaxScratchPadBuffers= MaxScratchPadBuffers<<5; + MaxScratchPadBuffers = MaxScratchPadBuffers << 5; MaxScratchPadBuffers = MaxScratchPadBuffers + HCSPARAMS2.MaxSPBuffersLo; XhciExtension->MaxScratchPadBuffers = MaxScratchPadBuffers;
@@ -693,10 +694,11 @@
// starting the controller Command.AsULONG = READ_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD); - Command.RunStop =1; - WRITE_REGISTER_ULONG (OperationalRegs + XHCI_USBCMD, Command.AsULONG ); - - MPStatus = XHCI_ControllerWorkTest(XhciExtension,Resources->StartVA, Resources->StartPA ); + Command.RunStop = 1; + WRITE_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD, Command.AsULONG); + + //below line should be uncommented if you want to use the controller work test function + //MPStatus = XHCI_ControllerWorkTest(XhciExtension,Resources->StartVA, Resources->StartPA );
return MP_STATUS_SUCCESS; } @@ -713,12 +715,14 @@ PMDL ScratchPadArrayMDL; PMDL ScratchPadBufferMDL; PXHCI_SCRATCHPAD_BUFFER_ARRAY BufferArrayPointer; + XhciExtension = (PXHCI_EXTENSION) xhciExtension; MaxScratchPadBuffers = XhciExtension->MaxScratchPadBuffers; // free memory allocated to scratchpad buffers. ScratchPadArrayMDL = XhciExtension-> ScratchPadArrayMDL; ScratchPadBufferMDL = XhciExtension-> ScratchPadBufferMDL; - if (MaxScratchPadBuffers != 0){ + if (MaxScratchPadBuffers != 0) + { // free the scratchpad buffers MmFreePagesFromMdl(ScratchPadBufferMDL); ExFreePool(ScratchPadBufferMDL); @@ -734,11 +738,12 @@ NTAPI XHCI_SuspendController(IN PVOID xhciExtension) { + DPRINT1("XHCI_SuspendController: function initiated\n"); PXHCI_EXTENSION XhciExtension; XhciExtension = (PXHCI_EXTENSION)xhciExtension;
XhciExtension->Flags |= XHCI_FLAGS_CONTROLLER_SUSPEND; - DPRINT1("XHCI_SuspendController: function initiated\n"); + }
MPSTATUS @@ -770,25 +775,20 @@ PULONG RunTimeRegisterBase; XHCI_INTERRUPTER_MANAGEMENT Iman; PXHCI_EXTENSION XhciExtension; + XhciExtension = (PXHCI_EXTENSION)xhciExtension;
- RunTimeRegisterBase = XhciExtension-> RunTimeRegisterBase; - + RunTimeRegisterBase = XhciExtension->RunTimeRegisterBase; Iman.AsULONG = READ_REGISTER_ULONG(RunTimeRegisterBase + XHCI_IMAN); if (Iman.InterruptPending == 0) { return FALSE; } - Iman.InterruptPending =1; - + Iman.InterruptPending = 1; WRITE_REGISTER_ULONG(RunTimeRegisterBase + XHCI_IMAN, Iman.AsULONG); DPRINT1("XHCI_InterruptService: Succesful Interupt\n"); // changing the enque pointer - - XHCI_ProcessEvent(xhciExtension); - - - + return TRUE; }
@@ -798,7 +798,7 @@ IN BOOLEAN IsDoEnableInterrupts) { DPRINT1("XHCI_InterruptDpc: function initiated\n"); - + XHCI_ProcessEvent(xhciExtension); }
MPSTATUS @@ -891,7 +891,7 @@ NTAPI XHCI_Get32BitFrameNumber(IN PVOID xhciExtension) { - //DPRINT1("XHCI_Get32BitFrameNumber: function initiated\n"); + //DPRINT1("XHCI_Get32BitFrameNumber: function initiated\n"); this function is called multiple times. commented out to reduce output in windbg return 0; }
@@ -911,21 +911,15 @@ PULONG OperationalRegs; PULONG RunTimeRegisterBase; XHCI_INTERRUPTER_MANAGEMENT Iman; - //XHCI_USB_COMMAND usbCommand; - - + XhciExtension = (PXHCI_EXTENSION)xhciExtension; OperationalRegs = XhciExtension->OperationalRegs; - //usbCommand.AsULONG =READ_REGISTER_ULONG (OperationalRegs + XHCI_USBCMD); - RunTimeRegisterBase = XhciExtension -> RunTimeRegisterBase; - Iman.AsULONG = READ_REGISTER_ULONG(RunTimeRegisterBase + XHCI_IMAN) ; + + RunTimeRegisterBase = XhciExtension->RunTimeRegisterBase; + Iman.AsULONG = READ_REGISTER_ULONG(RunTimeRegisterBase + XHCI_IMAN); Iman.InterruptEnable = 1; - WRITE_REGISTER_ULONG (RunTimeRegisterBase + XHCI_IMAN , Iman.AsULONG); - - //usbCommand.InterrupterEnable = 1; - - //WRITE_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD,usbCommand.AsULONG ); - DPRINT1("XHCI_EnableInterrupts: Interrupts enabled\n"); + WRITE_REGISTER_ULONG(RunTimeRegisterBase + XHCI_IMAN, Iman.AsULONG); + DPRINT1("XHCI_EnableInterrupts: Interrupts enabled\n"); }
VOID @@ -937,33 +931,25 @@ PULONG OperationalRegs; PULONG RunTimeRegisterBase; XHCI_INTERRUPTER_MANAGEMENT Iman; - //XHCI_USB_COMMAND usbCommand; - - + XhciExtension = (PXHCI_EXTENSION)xhciExtension; OperationalRegs = XhciExtension->OperationalRegs; - //usbCommand.AsULONG =READ_REGISTER_ULONG (OperationalRegs + XHCI_USBCMD); + RunTimeRegisterBase = XhciExtension -> RunTimeRegisterBase; - Iman.AsULONG = READ_REGISTER_ULONG(RunTimeRegisterBase + XHCI_IMAN) ; + Iman.AsULONG = READ_REGISTER_ULONG(RunTimeRegisterBase + XHCI_IMAN); Iman.InterruptEnable = 0; - WRITE_REGISTER_ULONG (RunTimeRegisterBase + XHCI_IMAN , Iman.AsULONG); - - //usbCommand.InterrupterEnable = 1; - - //WRITE_REGISTER_ULONG(OperationalRegs + XHCI_USBCMD,usbCommand.AsULONG ); - DPRINT1("XHCI_EnableInterrupts: Interrupts enabled\n"); + WRITE_REGISTER_ULONG(RunTimeRegisterBase + XHCI_IMAN,Iman.AsULONG); + + DPRINT1("XHCI_EnableInterrupts: Interrupts enabled\n"); }
VOID NTAPI XHCI_PollController(IN PVOID xhciExtension) { - //DPRINT1("XHCI_PollController: function initiated\n"); + //DPRINT1("XHCI_PollController: function initiated\n"); commented out to reduce windbg output PXHCI_EXTENSION XhciExtension; PULONG OperationalRegs; - //ULONG Port; - //XHCI_PORT_STATUS_CONTROL PortSC; -
XhciExtension = (PXHCI_EXTENSION)xhciExtension; OperationalRegs = XhciExtension->OperationalRegs; @@ -973,7 +959,6 @@ RegPacket.UsbPortInvalidateRootHub(XhciExtension); return; } - //RegPacket.UsbPortInvalidateRootHub(xhciExtension);
}
@@ -1092,7 +1077,7 @@ DPRINT("DriverEntry: DriverObject - %p, RegistryPath - %wZ\n", DriverObject, RegistryPath); - if (USBPORT_GetHciMn() != USBPORT_HCI_MN) // Don't know the purpose + if (USBPORT_GetHciMn() != USBPORT_HCI_MN) { return STATUS_INSUFFICIENT_RESOURCES; } @@ -1169,7 +1154,7 @@ DriverObject->DriverUnload = XHCI_Unload;
DPRINT1("XHCI_DriverEntry: after driver unload, before usbport_reg call. FIXME\n"); - //DbgBreakPoint(); + return USBPORT_RegisterUSBPortDriver(DriverObject, 200, &RegPacket); // 200- is version for usb 2... - // return STATUS_SUCCESS; + }
Modified: branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.h URL: http://svn.reactos.org/svn/reactos/branches/GSoC_2017/usbxhci/reactos/driver... ============================================================================== --- branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.h [iso-8859-1] (original) +++ branches/GSoC_2017/usbxhci/reactos/drivers/usb/usbxhci/usbxhci.h [iso-8859-1] Wed Aug 23 07:03:27 2017 @@ -26,21 +26,21 @@ #define NO_OP 8
// COMMAND TRB IDs -#define ENABLE_SLOT_COMMAND 9 -#define DISABLE_SLOT_COMMAND 10 -#define ADDRESS_DEVICE_COMMAND 11 -#define CONFIGURE_ENDPOINT_COMMAND 12 -#define EVALUATE_CONTEXT_COMMAND 13 -#define RESET_ENDPOINT_COMMAND 14 -#define STOP_ENDPOINT_COMMAND 15 -#define SET_TR_DEQUEUE_COMMAND 16 -#define RESET_DEVICE_COMMAND 17 -#define FORCE_EVENT_COMMMAND 18 -#define NEGOTIATE_BANDWIDTH_COMMAND 19 -#define SET_LATENCY_TOLERANCE_COMMAND 20 -#define GET_PORT_BANDWIDTH_COMMAND 21 -#define FORCE_HEADER_COMMAND 22 -#define NO_OP_COMMAND 23 +#define ENABLE_SLOT_COMMAND 9 +#define DISABLE_SLOT_COMMAND 10 +#define ADDRESS_DEVICE_COMMAND 11 +#define CONFIGURE_ENDPOINT_COMMAND 12 +#define EVALUATE_CONTEXT_COMMAND 13 +#define RESET_ENDPOINT_COMMAND 14 +#define STOP_ENDPOINT_COMMAND 15 +#define SET_TR_DEQUEUE_COMMAND 16 +#define RESET_DEVICE_COMMAND 17 +#define FORCE_EVENT_COMMMAND 18 +#define NEGOTIATE_BANDWIDTH_COMMAND 19 +#define SET_LATENCY_TOLERANCE_COMMAND 20 +#define GET_PORT_BANDWIDTH_COMMAND 21 +#define FORCE_HEADER_COMMAND 22 +#define NO_OP_COMMAND 23
// EVENT TRB IDs #define TRANSFER_EVENT 32 @@ -92,12 +92,16 @@ #define SPLIT_TRNASACTION_ERROR 36
//Data structures -typedef struct _XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY { - PHYSICAL_ADDRESS ContextBaseAddr [256]; +typedef struct _XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY +{ + PHYSICAL_ADDRESS ContextBaseAddr [256]; } XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY, *PXHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY; + //----------------------------------------LINK TRB-------------------------------------------------------------------- -typedef union _XHCI_LINK_ADDR{ - struct { +typedef union _XHCI_LINK_ADDR +{ + struct + { ULONGLONG RsvdZ1 : 4; ULONGLONG RingSegmentPointerLo : 28; ULONGLONG RingSegmentPointerHi : 32; @@ -105,19 +109,24 @@ ULONGLONG AsULONGLONG; } XHCI_LINK_ADDR;
-typedef struct _XHCI_LINK_TRB{ - struct { +typedef struct _XHCI_LINK_TRB +{ + struct + { ULONG RsvdZ1 : 4; ULONG RingSegmentPointerLo : 28; }; - struct { + struct + { ULONG RingSegmentPointerHi : 32; }; - struct { + struct + { ULONG RsvdZ2 : 22; ULONG InterrupterTarget : 10; }; - struct { + struct + { ULONG CycleBit : 1; ULONG ToggleCycle : 1; ULONG RsvdZ3 : 2; @@ -130,6 +139,7 @@ //ULONG AsULONG; } XHCI_LINK_TRB; C_ASSERT(sizeof(XHCI_LINK_TRB) == 16); + //----------------------------------------generic trb---------------------------------------------------------------- typedef struct _XHCI_GENERIC_TRB { ULONG Word0; @@ -139,46 +149,49 @@ }XHCI_GENERIC_TRB, *PXHCI_GENERIC_TRB; C_ASSERT(sizeof(XHCI_GENERIC_TRB) == 16); //----------------------------------------Command TRBs---------------------------------------------------------------- -typedef struct _XHCI_COMMAND_NO_OP_TRB { - ULONG RsvdZ1; - ULONG RsvdZ2; - ULONG RsvdZ3; - struct{ - ULONG CycleBit : 1; - ULONG RsvdZ4 : 9; - ULONG TRBType : 6; - ULONG RsvdZ5 : 16; - }; +typedef struct _XHCI_COMMAND_NO_OP_TRB +{ + ULONG RsvdZ1; + ULONG RsvdZ2; + ULONG RsvdZ3; + struct + { + ULONG CycleBit : 1; + ULONG RsvdZ4 : 9; + ULONG TRBType : 6; + ULONG RsvdZ5 : 16; + }; } XHCI_COMMAND_NO_OP_TRB; C_ASSERT(sizeof(XHCI_COMMAND_NO_OP_TRB) == 16); -typedef union _XHCI_COMMAND_TRB { + +typedef union _XHCI_COMMAND_TRB +{ XHCI_COMMAND_NO_OP_TRB NoOperation; - //XHCI_LINK_TRB Link; - //XHCI_GENERIC_TRB GenericTRB; }XHCI_COMMAND_TRB, *PXHCI_COMMAND_TRB; C_ASSERT(sizeof(XHCI_COMMAND_TRB) == 16); -/*typedef struct _XHCI_COMMAND_RING { - XHCI_COMMAND_TRB Segment[4]; - PXHCI_COMMAND_TRB CREnquePointer; - PXHCI_COMMAND_TRB CRDequePointer; -} XHCI_COMMAND_RING;*/ + //----------------------------------------CONTROL TRANSFER DATA STRUCTUERS-------------------------------------------- -typedef struct _XHCI_CONTROL_SETUP_TRB { - struct { +typedef struct _XHCI_CONTROL_SETUP_TRB +{ + struct + { ULONG bmRequestType : 8; ULONG bRequest : 8; ULONG wValue : 16; }; - struct { + struct + { ULONG wIndex : 16; ULONG wLength : 16; }; - struct { + struct + { ULONG TRBTransferLength : 17; ULONG RsvdZ : 5; ULONG InterrupterTarget : 10; }; - struct { + struct + { ULONG CycleBit : 1; ULONG RsvdZ1 : 4; ULONG InterruptOnCompletion : 1; @@ -188,22 +201,27 @@ ULONG TransferType : 2; ULONG RsvdZ3 : 14; }; - //ULONG AsULONG; } XHCI_CONTROL_SETUP_TRB; C_ASSERT(sizeof(XHCI_CONTROL_SETUP_TRB) == 16); -typedef struct _XHCI_CONTROL_DATA_TRB { - struct { + +typedef struct _XHCI_CONTROL_DATA_TRB +{ + struct + { ULONG DataBufferPointerLo : 32; }; - struct { + struct + { ULONG DataBufferPointerHi : 32; }; - struct { + struct + { ULONG TRBTransferLength : 17; ULONG TDSize : 5; ULONG InterrupterTarget : 10; }; - struct { + struct + { ULONG CycleBit : 1; ULONG EvaluateNextTRB : 1; ULONG InterruptOnShortPacket : 1; @@ -216,21 +234,26 @@ ULONG Direction : 1; ULONG RsvdZ2 : 15; }; - //ULONG AsULONG; } XHCI_CONTROL_DATA_TRB; C_ASSERT(sizeof(XHCI_CONTROL_DATA_TRB) == 16); -typedef struct _XHCI_CONTROL_STATUS_TRB { - struct { + +typedef struct _XHCI_CONTROL_STATUS_TRB +{ + struct + { ULONG RsvdZ1 : 32; }; - struct { + struct + { ULONG RsvdZ2 : 32; }; - struct { + struct + { ULONG RsvdZ : 22; ULONG InterrupterTarget : 10; }; - struct { + struct + { ULONG CycleBit : 1; ULONG EvaluateNextTRB : 1; ULONG ChainBit : 2; @@ -240,28 +263,34 @@ ULONG Direction : 1; ULONG RsvdZ4 : 15; }; - // ULONG AsULONG; } XHCI_CONTROL_STATUS_TRB; C_ASSERT(sizeof(XHCI_CONTROL_STATUS_TRB) == 16); -typedef union _XHCI_CONTROL_TRB { + +typedef union _XHCI_CONTROL_TRB +{ XHCI_CONTROL_SETUP_TRB SetupTRB; XHCI_CONTROL_DATA_TRB DataTRB; XHCI_CONTROL_STATUS_TRB StatusTRB; XHCI_GENERIC_TRB GenericTRB; } XHCI_CONTROL_TRB, *PXHCI_CONTROL_TRB; C_ASSERT(sizeof(XHCI_CONTROL_TRB) == 16); + //----------------event strucs------------------- -typedef struct _XHCI_EVENT_COMMAND_COMPLETION_TRB{ - struct { +typedef struct _XHCI_EVENT_COMMAND_COMPLETION_TRB +{ + struct + { ULONG RsvdZ1 : 4; ULONG CommandTRBPointerLo : 28; }; ULONG CommandTRBPointerHi; - struct { + struct + { ULONG CommandCompletionParam : 24; ULONG CompletionCode : 8; }; - struct { + struct + { ULONG CycleBit : 1; ULONG RsvdZ2 : 9; ULONG TRBType : 6; @@ -271,17 +300,21 @@ } XHCI_EVENT_COMMAND_COMPLETION_TRB; C_ASSERT(sizeof(XHCI_EVENT_COMMAND_COMPLETION_TRB) == 16);
-typedef struct _XHCI_EVENT_PORT_STATUS_CHANGE_TRB{ - struct { +typedef struct _XHCI_EVENT_PORT_STATUS_CHANGE_TRB +{ + struct + { ULONG RsvdZ1 : 24; ULONG PortID : 8; }; ULONG RsvdZ2; - struct { + struct + { ULONG RsvdZ3 : 24; ULONG CompletionCode : 8; }; - struct { + struct + { ULONG CycleBit : 1; ULONG RsvdZ4 : 9; ULONG TRBType : 6; @@ -290,11 +323,13 @@ } XHCI_EVENT_PORT_STATUS_CHANGE_TRB; C_ASSERT(sizeof(XHCI_EVENT_PORT_STATUS_CHANGE_TRB) == 16);
-typedef struct _XHCI_EVENT_GENERIC_TRB{ +typedef struct _XHCI_EVENT_GENERIC_TRB +{ ULONG Word0; ULONG Word1; ULONG Word2; - struct { + struct + { ULONG CycleBit : 1; ULONG RsvdZ1 : 9; ULONG TRBType : 6; @@ -304,94 +339,107 @@ }XHCI_EVENT_GENERIC_TRB; C_ASSERT(sizeof(XHCI_EVENT_GENERIC_TRB) == 16);
-typedef union _XHCI_EVENT_TRB { - XHCI_EVENT_COMMAND_COMPLETION_TRB CommandCompletionTRB; - XHCI_EVENT_PORT_STATUS_CHANGE_TRB PortStatusChangeTRB; - XHCI_EVENT_GENERIC_TRB EventGenericTRB; +typedef union _XHCI_EVENT_TRB +{ + XHCI_EVENT_COMMAND_COMPLETION_TRB CommandCompletionTRB; + XHCI_EVENT_PORT_STATUS_CHANGE_TRB PortStatusChangeTRB; + XHCI_EVENT_GENERIC_TRB EventGenericTRB; }XHCI_EVENT_TRB, *PXHCI_EVENT_TRB; C_ASSERT(sizeof(XHCI_EVENT_TRB) == 16);
-typedef struct _XHCI_EVENT_RING_SEGMENT_TABLE{ +typedef struct _XHCI_EVENT_RING_SEGMENT_TABLE +{ ULONGLONG RingSegmentBaseAddr; - struct { - ULONGLONG RingSegmentSize : 16; + struct + { + ULONGLONG RingSegmentSize : 16; ULONGLONG RsvdZ : 48; }; } XHCI_EVENT_RING_SEGMENT_TABLE; //------------------------------------main structs-----------------------
-typedef union _XHCI_TRB { +typedef union _XHCI_TRB +{ XHCI_COMMAND_TRB CommandTRB; XHCI_LINK_TRB LinkTRB; XHCI_CONTROL_TRB ControlTRB; XHCI_EVENT_TRB EventTRB; XHCI_GENERIC_TRB GenericTRB; } XHCI_TRB, *PXHCI_TRB; - -typedef struct _XHCI_SEGMENT { +C_ASSERT(sizeof(XHCI_TRB) == 16); + +typedef struct _XHCI_SEGMENT +{ XHCI_TRB XhciTrb[256]; PVOID nextSegment; -}XHCI_SEGMENT , *PXHCI_SEGMENT; - -typedef struct _XHCI_RING { - //XHCI_TRB XhciTrb[256]; +}XHCI_SEGMENT, *PXHCI_SEGMENT; + +typedef struct _XHCI_RING +{ XHCI_SEGMENT firstSeg; PXHCI_TRB dequeue_pointer; PXHCI_TRB enqueue_pointer; PXHCI_SEGMENT enqueue_segment; PXHCI_SEGMENT dequeue_segment; - struct { - UCHAR ProducerCycleState : 1; - UCHAR ConsumerCycleState : 1; - }; - //ULONGLONG Padding; + struct + { + UCHAR ProducerCycleState : 1; + UCHAR ConsumerCycleState : 1; + }; } XHCI_RING, *PXHCI_RING; -typedef struct _XHCI_HC_RESOURCES { - XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY DCBAA; - DECLSPEC_ALIGN(16) XHCI_RING EventRing ; - DECLSPEC_ALIGN(64) XHCI_RING CommandRing ; - DECLSPEC_ALIGN(64) XHCI_EVENT_RING_SEGMENT_TABLE EventRingSegTable; + +typedef struct _XHCI_HC_RESOURCES +{ + XHCI_DEVICE_CONTEXT_BASE_ADD_ARRAY DCBAA; + DECLSPEC_ALIGN(16) XHCI_RING EventRing ; + DECLSPEC_ALIGN(64) XHCI_RING CommandRing ; + DECLSPEC_ALIGN(64) XHCI_EVENT_RING_SEGMENT_TABLE EventRingSegTable; } XHCI_HC_RESOURCES, *PXHCI_HC_RESOURCES; C_ASSERT (FIELD_OFFSET(XHCI_HC_RESOURCES,EventRing)% 16 == 0); C_ASSERT (FIELD_OFFSET(XHCI_HC_RESOURCES,CommandRing)% 64 == 0); C_ASSERT (FIELD_OFFSET(XHCI_HC_RESOURCES,EventRingSegTable)% 64 == 0);
-typedef struct _XHCI_EXTENSION { - ULONG Reserved; - ULONG Flags; - PULONG BaseIoAdress; - PULONG OperationalRegs; - PULONG RunTimeRegisterBase; - PULONG DoorBellRegisterBase; - UCHAR FrameLengthAdjustment; - BOOLEAN IsStarted; - USHORT HcSystemErrors; - ULONG PortRoutingControl; - USHORT NumberOfPorts; // HCSPARAMS1 => N_PORTS - USHORT PortPowerControl; // HCSPARAMS => Port Power Control (PPC) - USHORT PageSize; - USHORT MaxScratchPadBuffers; - PMDL ScratchPadArrayMDL; - PMDL ScratchPadBufferMDL; - PXHCI_HC_RESOURCES HcResourcesVA; - PHYSICAL_ADDRESS HcResourcesPA; +typedef struct _XHCI_EXTENSION +{ + ULONG Reserved; + ULONG Flags; + PULONG BaseIoAdress; + PULONG OperationalRegs; + PULONG RunTimeRegisterBase; + PULONG DoorBellRegisterBase; + UCHAR FrameLengthAdjustment; + BOOLEAN IsStarted; + USHORT HcSystemErrors; + ULONG PortRoutingControl; + USHORT NumberOfPorts; // HCSPARAMS1 => N_PORTS + USHORT PortPowerControl; // HCSPARAMS => Port Power Control (PPC) + USHORT PageSize; + USHORT MaxScratchPadBuffers; + PMDL ScratchPadArrayMDL; + PMDL ScratchPadBufferMDL; + PXHCI_HC_RESOURCES HcResourcesVA; + PHYSICAL_ADDRESS HcResourcesPA; } XHCI_EXTENSION, *PXHCI_EXTENSION;
-typedef struct _XHCI_ENDPOINT { - ULONG Reserved; +typedef struct _XHCI_ENDPOINT +{ + ULONG Reserved; } XHCI_ENDPOINT, *PXHCI_ENDPOINT;
-typedef struct _XHCI_TRANSFER { - ULONG Reserved; +typedef struct _XHCI_TRANSFER +{ + ULONG Reserved; } XHCI_TRANSFER, *PXHCI_TRANSFER;
-typedef union _XHCI_SCRATCHPAD_BUFFER_ARRAY{ - struct { - ULONGLONG RsvdZ1 : 12; - ULONGLONG bufferBaseAddr : 52; - }; - ULONGLONG AsULONGLONG; +typedef union _XHCI_SCRATCHPAD_BUFFER_ARRAY +{ + struct + { + ULONGLONG RsvdZ1 : 12; + ULONGLONG bufferBaseAddr : 52; + }; + ULONGLONG AsULONGLONG; } XHCI_SCRATCHPAD_BUFFER_ARRAY, *PXHCI_SCRATCHPAD_BUFFER_ARRAY; C_ASSERT(sizeof(XHCI_SCRATCHPAD_BUFFER_ARRAY) == 8); //roothub functions
-
rgampa＠svn.reactos.org