[ros-arm-bringup] 41928: Add some more intrinsics, and change _enable and _disable to use the new ARMv6 instructions instead... we'll have to make similar changes to the routines that use SWP

Author: ros-arm-bringup
Date: Sun Jul 12 14:49:47 2009
New Revision: 41928

URL: http://svn.reactos.org/svn/reactos?rev=41928&view=rev
Log:
Add some more intrinsics, and change _enable and _disable to use the new ARMv6
instructions instead... we'll have to make similar changes to the routines that use
SWP

Modified:
    trunk/reactos/include/crt/mingw32/intrin_arm.h

Modified: trunk/reactos/include/crt/mingw32/intrin_arm.h
URL:
http://svn.reactos.org/svn/reactos/trunk/reactos/include/crt/mingw32/intrin…
==============================================================================
--- trunk/reactos/include/crt/mingw32/intrin_arm.h [iso-8859-1] (original)
+++ trunk/reactos/include/crt/mingw32/intrin_arm.h [iso-8859-1] Sun Jul 12 14:49:47 2009
@@ -121,6 +121,14 @@
     return (void *)_InterlockedExchange((volatile long * const)Target, (const
long)Value);
 }
 
+
+
+__INTRIN_INLINE unsigned char _BitScanReverse(unsigned long * const Index, const unsigned
long Mask)
+{
+    *Index = 31 - __builtin_clz(Mask);
+	return Mask ? 1 : 0;
+}
+
 __INTRIN_INLINE char _InterlockedAnd8(volatile char * const value, const char mask)
 {
 	char x;
@@ -294,13 +302,17 @@
 	return _InterlockedExchangeAdd16(lpAddend, 1) + 1;
 }
 
+__INTRIN_INLINE long _InterlockedAddLargeStatistic(volatile long long * const Addend,
const long Value)
+{
+    *Addend += Value;
+    return Value;
+}
+
 __INTRIN_INLINE void _disable(void)
 {
     __asm__ __volatile__
     (
-     "mrs r1, cpsr;"
-     "orr r1, r1, #0x80;"
-     "msr cpsr, r1;"
+     "cpsid i    @ __cli" : : : "memory", "cc"
     );
 }
 
@@ -308,10 +320,18 @@
 {
     __asm__ __volatile__
     (
-     "mrs r1, cpsr;"
-     "bic r1, r1, #0x80;"
-     "msr cpsr, r1;"
+     "cpsie i    @ __sti" : : : "memory", "cc"
     );
+}
+
+__INTRIN_INLINE unsigned char _interlockedbittestandset(volatile long * a, const long b)
+{
+	return (_InterlockedOr(a, 1 << b) >> b) & 1;
+}
+
+__INTRIN_INLINE unsigned char _interlockedbittestandreset(volatile long * a, const long
b)
+{
+	return (_InterlockedAnd(a, ~(1 << b)) >> b) & 1;
 }
 
 #ifndef __MSVCRT__