[tkreuzer] 53838: [NTOSKRNL] - Cleanup amd64 mm.h header - Call MiScanMemoryDescriptors earlier, since it doesn't depend on anything except the loader block. - MiComputeColorInformation() and the c...
Author: tkreuzer Date: Sat Sep 24 14:22:13 2011 New Revision: 53838
URL: http://svn.reactos.org/svn/reactos?rev=53838&view=rev Log: [NTOSKRNL] - Cleanup amd64 mm.h header - Call MiScanMemoryDescriptors earlier, since it doesn't depend on anything except the loader block. - MiComputeColorInformation() and the calculation of the pfn database size are portable, so move them out of MiInitMachineDependent
Modified: trunk/reactos/ntoskrnl/include/internal/amd64/mm.h trunk/reactos/ntoskrnl/mm/ARM3/i386/init.c trunk/reactos/ntoskrnl/mm/ARM3/mminit.c
Modified: trunk/reactos/ntoskrnl/include/internal/amd64/mm.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/include/internal/a... ============================================================================== --- trunk/reactos/ntoskrnl/include/internal/amd64/mm.h [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/include/internal/amd64/mm.h [iso-8859-1] Sat Sep 24 14:22:13 2011 @@ -1,16 +1,10 @@ /* - * Lowlevel memory managment definitions + * kernel internal memory managment definitions for amd64 */ - #pragma once
-#define _MI_PAGING_LEVELS 4 - -/* Helper macros */ -#define PAGE_MASK(x) ((x)&(~0xfff)) -#define PAE_PAGE_MASK(x) ((x)&(~0xfffLL)) - /* Memory layout base addresses */ +#define MI_LOWEST_VAD_ADDRESS (PVOID)0x000000007FF00000ULL #define MI_HIGHEST_USER_ADDRESS (PVOID)0x000007FFFFFEFFFFULL #define MI_USER_PROBE_ADDRESS (PVOID)0x000007FFFFFF0000ULL #define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0xFFFF080000000000ULL @@ -28,128 +22,58 @@ #define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL #define MI_SYSTEM_CACHE_WS_START (PVOID)0xFFFFF78000001000ULL // CHECKME
-#define MI_LOWEST_VAD_ADDRESS (PVOID)0x000000007FF00000ULL - +#define MM_HIGHEST_USER_ADDRESS_WOW64 0x7FFEFFFF +#define MM_SYSTEM_RANGE_START_WOW64 0x80000000 + + +#define MI_SYSTEM_PTE_END (PVOID)((ULONG64)MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1) #define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(KSEG0_BASE) +#define MM_HIGHEST_VAD_ADDRESS (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE)) +#define MI_MAPPING_RANGE_START (ULONG64)HYPER_SPACE +#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + MI_HYPERSPACE_PTES * PAGE_SIZE)
/* Memory sizes */ #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT) -#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19*1024*1024) >> PAGE_SHIFT) -#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32*1024*1024) >> PAGE_SHIFT) -#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024) -#define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024) -#define MI_MAX_FREE_PAGE_LISTS 4 -#define MI_MIN_INIT_PAGED_POOLSIZE (32 * 1024 * 1024) -#define MI_SESSION_VIEW_SIZE (20 * 1024 * 1024) -#define MI_SESSION_POOL_SIZE (16 * 1024 * 1024) -#define MI_SESSION_IMAGE_SIZE (8 * 1024 * 1024) -#define MI_SESSION_WORKING_SET_SIZE (4 * 1024 * 1024) -#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \ - MI_SESSION_POOL_SIZE + \ - MI_SESSION_IMAGE_SIZE + \ - MI_SESSION_WORKING_SET_SIZE) -#define MI_SYSTEM_VIEW_SIZE (16 * 1024 * 1024) -#define MI_NUMBER_SYSTEM_PTES 22000 - -#define MI_MIN_SECONDARY_COLORS 8 -#define MI_SECONDARY_COLORS 64 -#define MI_MAX_SECONDARY_COLORS 1024 - -#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB) -#define MI_ALLOCATION_FRAGMENT (64 * _1KB) -#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB) - -#define MM_HIGHEST_VAD_ADDRESS \ - (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE)) - -#define MM_HIGHEST_USER_ADDRESS_WOW64 0x7FFEFFFF -#define MM_SYSTEM_RANGE_START_WOW64 0x80000000 - -PULONG64 -FORCEINLINE -MmGetPageDirectory(VOID) -{ - return (PULONG64)__readcr3(); -} - -PMMPTE -FORCEINLINE -MiAddressToPxe(PVOID Address) -{ - ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3); - Offset &= PXI_MASK << 3; - return (PMMPTE)(PXE_BASE + Offset); -} - -PMMPTE -FORCEINLINE -MiAddressToPpe(PVOID Address) -{ - ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3); - Offset &= 0x3FFFF << 3; - return (PMMPTE)(PPE_BASE + Offset); -} - -PMMPTE -FORCEINLINE -_MiAddressToPde(PVOID Address) -{ - ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3); - Offset &= 0x7FFFFFF << 3; - return (PMMPTE)(PDE_BASE + Offset); -} -#define MiAddressToPde(x) _MiAddressToPde((PVOID)(x)) - -PMMPTE -FORCEINLINE -_MiAddressToPte(PVOID Address) -{ - ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3); - Offset &= 0xFFFFFFFFFULL << 3; - return (PMMPTE)(PTE_BASE + Offset); -} -#define MiAddressToPte(x) _MiAddressToPte((PVOID)(x)) - -ULONG -FORCEINLINE -MiAddressToPti(PVOID Address) -{ - return ((((ULONG64)Address) >> PTI_SHIFT) & 0x1FF); -} -#define MiAddressToPteOffset(x) MiAddressToPti(x) // FIXME: bad name - -ULONG -FORCEINLINE -MiAddressToPxi(PVOID Address) -{ - return ((((ULONG64)Address) >> PXI_SHIFT) & 0x1FF); -} - - -/* Convert a PTE into a corresponding address */ -PVOID -FORCEINLINE -MiPteToAddress(PMMPTE Pte) -{ - /* Use signed math */ - LONG64 Temp = (LONG64)Pte; - Temp <<= 25; - Temp >>= 16; - return (PVOID)Temp; -} -#define MiPdeToAddress MiPteToAddress - -BOOLEAN -FORCEINLINE -MiIsPdeForAddressValid(PVOID Address) -{ - return ((MiAddressToPxe(Address)->u.Hard.Valid) && - (MiAddressToPpe(Address)->u.Hard.Valid) && - (MiAddressToPde(Address)->u.Hard.Valid)); -} - -#define MiPdeToPte(PDE) ((PMMPTE)MiPteToAddress(PDE)) -#define MiPteToPde(PTE) ((PMMPDE)MiAddressToPte(PTE)) +#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19*1024*1024) >> PAGE_SHIFT) +#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32*1024*1024) >> PAGE_SHIFT) +#define MI_MIN_INIT_PAGED_POOLSIZE (32 * 1024 * 1024) +#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024) +#define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024) +#define MI_SYSTEM_VIEW_SIZE (16 * 1024 * 1024) +#define MI_MIN_SECONDARY_COLORS 8 +#define MI_SECONDARY_COLORS 64 +#define MI_MAX_SECONDARY_COLORS 1024 +#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB) +#define MI_ALLOCATION_FRAGMENT (64 * _1KB) +#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB) +#define MI_SESSION_WORKING_SET_SIZE (4 * 1024 * 1024) +#define MI_SESSION_VIEW_SIZE (20 * 1024 * 1024) +#define MI_SESSION_POOL_SIZE (16 * 1024 * 1024) +#define MI_SESSION_IMAGE_SIZE (8 * 1024 * 1024) +#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \ + MI_SESSION_POOL_SIZE + \ + MI_SESSION_IMAGE_SIZE + \ + MI_SESSION_WORKING_SET_SIZE) + +/* Misc constants */ +#define _MI_PAGING_LEVELS 4 +#define MI_NUMBER_SYSTEM_PTES 22000 +#define MI_MAX_FREE_PAGE_LISTS 4 +#define NR_SECTION_PAGE_TABLES 1024 +#define NR_SECTION_PAGE_ENTRIES 1024 +#define MI_HYPERSPACE_PTES (256 - 1) +#define MI_ZERO_PTES (32) +#define MI_DUMMY_PTE (PMMPTE)(MI_MAPPING_RANGE_END + PAGE_SIZE) +#define MI_VAD_BITMAP (PMMPTE)(MI_DUMMY_PTE + PAGE_SIZE) +#define MI_WORKING_SET_LIST (PMMPTE)(MI_VAD_BITMAP + PAGE_SIZE) +/* FIXME - different architectures have different cache line sizes... */ +#define MM_CACHE_LINE_SIZE 32 + +/* Helper macros */ +#define PAGE_MASK(x) ((x)&(~0xfff)) +#define PAE_PAGE_MASK(x) ((x)&(~0xfffLL)) +#define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0) +#define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
#define ADDR_TO_PAGE_TABLE(v) ((ULONG)(((ULONG_PTR)(v)) / (512 * PAGE_SIZE))) #define ADDR_TO_PDE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))) @@ -161,43 +85,6 @@ #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF) #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF) #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF) - -FORCEINLINE -VOID -MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte, - IN PMMPTE PointerPte) -{ - /* Store the Address */ - NewPte->u.Long = (ULONG64)PointerPte; - - /* Mark this as a prototype PTE */ - NewPte->u.Proto.Prototype = 1; - NewPte->u.Proto.Valid = 1; - NewPte->u.Proto.ReadOnly = 0; - NewPte->u.Proto.Protection = 0; -} - -/* Sign extend 48 bits */ -#define MiProtoPteToPte(x) \ - (PMMPTE)((LONG64)(x)->u.Proto.ProtoAddress) - -/* We don't use these hacks */ -VOID -FORCEINLINE -MmUpdatePageDir(PEPROCESS Process, PVOID Address, ULONG Size) -{ - /* Nothing to do */ -} - -VOID -FORCEINLINE -MmInitGlobalKernelPageDirectory(VOID) -{ - /* Nothing to do */ -} - -#define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0) -#define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
/* Easy accessing PFN in PTE */ #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber) @@ -227,34 +114,123 @@ // FIXME!!! #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \ ((x) / (4*1024*1024)) - #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \ ((((x)) % (4*1024*1024)) / (4*1024))
-#define NR_SECTION_PAGE_TABLES 1024 -#define NR_SECTION_PAGE_ENTRIES 1024 - //#define TEB_BASE 0x7FFDE000 - -#define MI_HYPERSPACE_PTES (256 - 1) -#define MI_ZERO_PTES (32) -#define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE -#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \ - MI_HYPERSPACE_PTES * PAGE_SIZE) -#define MI_DUMMY_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \ - PAGE_SIZE) -#define MI_VAD_BITMAP (PMMPTE)(MI_DUMMY_PTE + \ - PAGE_SIZE) -#define MI_WORKING_SET_LIST (PMMPTE)(MI_VAD_BITMAP + \ - PAGE_SIZE) -
/* On x86, these two are the same */ #define MMPDE MMPTE #define PMMPDE PMMPTE
-/* -* FIXME - different architectures have different cache line sizes... -*/ -#define MM_CACHE_LINE_SIZE 32 - +PULONG64 +FORCEINLINE +MmGetPageDirectory(VOID) +{ + return (PULONG64)__readcr3(); +} + +PMMPTE +FORCEINLINE +MiAddressToPxe(PVOID Address) +{ + ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3); + Offset &= PXI_MASK << 3; + return (PMMPTE)(PXE_BASE + Offset); +} + +PMMPTE +FORCEINLINE +MiAddressToPpe(PVOID Address) +{ + ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3); + Offset &= 0x3FFFF << 3; + return (PMMPTE)(PPE_BASE + Offset); +} + +PMMPTE +FORCEINLINE +_MiAddressToPde(PVOID Address) +{ + ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3); + Offset &= 0x7FFFFFF << 3; + return (PMMPTE)(PDE_BASE + Offset); +} +#define MiAddressToPde(x) _MiAddressToPde((PVOID)(x)) + +PMMPTE +FORCEINLINE +_MiAddressToPte(PVOID Address) +{ + ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3); + Offset &= 0xFFFFFFFFFULL << 3; + return (PMMPTE)(PTE_BASE + Offset); +} +#define MiAddressToPte(x) _MiAddressToPte((PVOID)(x)) + +ULONG +FORCEINLINE +MiAddressToPti(PVOID Address) +{ + return ((((ULONG64)Address) >> PTI_SHIFT) & 0x1FF); +} +#define MiAddressToPteOffset(x) MiAddressToPti(x) // FIXME: bad name + +ULONG +FORCEINLINE +MiAddressToPxi(PVOID Address) +{ + return ((((ULONG64)Address) >> PXI_SHIFT) & 0x1FF); +} + + +/* Convert a PTE into a corresponding address */ +PVOID +FORCEINLINE +MiPteToAddress(PMMPTE Pte) +{ + /* Use signed math */ + LONG64 Temp = (LONG64)Pte; + Temp <<= 25; + Temp >>= 16; + return (PVOID)Temp; +} +#define MiPdeToAddress MiPteToAddress + +BOOLEAN +FORCEINLINE +MiIsPdeForAddressValid(PVOID Address) +{ + return ((MiAddressToPxe(Address)->u.Hard.Valid) && + (MiAddressToPpe(Address)->u.Hard.Valid) && + (MiAddressToPde(Address)->u.Hard.Valid)); +} + +#define MiPdeToPte(PDE) ((PMMPTE)MiPteToAddress(PDE)) +#define MiPteToPde(PTE) ((PMMPDE)MiAddressToPte(PTE)) + +FORCEINLINE +VOID +MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte, + IN PMMPTE PointerPte) +{ + /* Store the Address */ + NewPte->u.Long = (ULONG64)PointerPte; + + /* Mark this as a prototype PTE */ + NewPte->u.Proto.Prototype = 1; + NewPte->u.Proto.Valid = 1; + NewPte->u.Proto.ReadOnly = 0; + NewPte->u.Proto.Protection = 0; +} + +/* Sign extend 48 bits */ +#define MiProtoPteToPte(x) (PMMPTE)((LONG64)(x)->u.Proto.ProtoAddress) + +VOID +FORCEINLINE +MmInitGlobalKernelPageDirectory(VOID) +{ + /* Nothing to do */ +} +
Modified: trunk/reactos/ntoskrnl/mm/ARM3/i386/init.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/mm/ARM3/i386/init.... ============================================================================== --- trunk/reactos/ntoskrnl/mm/ARM3/i386/init.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/mm/ARM3/i386/init.c [iso-8859-1] Sat Sep 24 14:22:13 2011 @@ -265,27 +265,6 @@ /* Compute non paged pool limits and size */ MiComputeNonPagedPoolVa(MiNumberOfFreePages);
- /* Compute color information (L2 cache-separated paging lists) */ - MiComputeColorInformation(); - - // - // Calculate the number of bytes for the PFN database - // then add the color tables and convert to pages - // - MxPfnAllocation = (MmHighestPhysicalPage + 1) * sizeof(MMPFN); - MxPfnAllocation += (MmSecondaryColors * sizeof(MMCOLOR_TABLES) * 2); - MxPfnAllocation >>= PAGE_SHIFT; - - // - // We have to add one to the count here, because in the process of - // shifting down to the page size, we actually ended up getting the - // lower aligned size (so say, 0x5FFFF bytes is now 0x5F pages). - // Later on, we'll shift this number back into bytes, which would cause - // us to end up with only 0x5F000 bytes -- when we actually want to have - // 0x60000 bytes. - // - MxPfnAllocation++; - // // Now calculate the nonpaged pool expansion VA region //
Modified: trunk/reactos/ntoskrnl/mm/ARM3/mminit.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/mm/ARM3/mminit.c?r... ============================================================================== --- trunk/reactos/ntoskrnl/mm/ARM3/mminit.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/mm/ARM3/mminit.c [iso-8859-1] Sat Sep 24 14:22:13 2011 @@ -1884,6 +1884,9 @@ IncludeType[LoaderBBTMemory] = FALSE; if (Phase == 0) { + /* Count physical pages on the system */ + MiScanMemoryDescriptors(LoaderBlock); + /* Initialize the phase 0 temporary event */ KeInitializeEvent(&MiTempEvent, NotificationEvent, FALSE);
@@ -1939,14 +1942,9 @@ MmZeroingPageThreadActive = FALSE;
// - // Count physical pages on the system - // - MiScanMemoryDescriptors(LoaderBlock); + // Check if this is a machine with less than 19MB of RAM + // PageCount = MmNumberOfPhysicalPages; - - // - // Check if this is a machine with less than 19MB of RAM - // if (PageCount < MI_MIN_PAGES_FOR_SYSPTE_TUNING) { // @@ -2031,6 +2029,23 @@ /* Make sure it's not too low */ if (MmLargeStackSize < KERNEL_STACK_SIZE) MmLargeStackSize = KERNEL_STACK_SIZE; } + + /* Compute color information (L2 cache-separated paging lists) */ + MiComputeColorInformation(); + + // Calculate the number of bytes for the PFN database + // then add the color tables and convert to pages + MxPfnAllocation = (MmHighestPhysicalPage + 1) * sizeof(MMPFN); + MxPfnAllocation += (MmSecondaryColors * sizeof(MMCOLOR_TABLES) * 2); + MxPfnAllocation >>= PAGE_SHIFT; + + // We have to add one to the count here, because in the process of + // shifting down to the page size, we actually ended up getting the + // lower aligned size (so say, 0x5FFFF bytes is now 0x5F pages). + // Later on, we'll shift this number back into bytes, which would cause + // us to end up with only 0x5F000 bytes -- when we actually want to have + // 0x60000 bytes. + MxPfnAllocation++;
/* Initialize the platform-specific parts */ MiInitMachineDependent(LoaderBlock);
-
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