[sir_richard] 48288: [NTOS]: Another long-lost-promised straggler for Timo. There may be more of these needed, this is what I had done on my disk.
Author: sir_richard Date: Mon Jul 26 21:45:42 2010 New Revision: 48288
URL: http://svn.reactos.org/svn/reactos?rev=48288&view=rev Log: [NTOS]: Another long-lost-promised straggler for Timo. There may be more of these needed, this is what I had done on my disk.
Modified: trunk/reactos/ntoskrnl/mm/ARM3/mdlsup.c trunk/reactos/ntoskrnl/mm/ARM3/mminit.c trunk/reactos/ntoskrnl/mm/ARM3/pagfault.c trunk/reactos/ntoskrnl/mm/ARM3/pool.c
Modified: trunk/reactos/ntoskrnl/mm/ARM3/mdlsup.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/mm/ARM3/mdlsup.c?r... ============================================================================== --- trunk/reactos/ntoskrnl/mm/ARM3/mdlsup.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/mm/ARM3/mdlsup.c [iso-8859-1] Mon Jul 26 21:45:42 2010 @@ -813,6 +813,10 @@ // Assume failure and check for non-mapped pages // *MdlPages = -1; +#if (_MI_PAGING_LEVELS >= 3) + /* Should be checking the PPE and PXE */ + ASSERT(FALSE); +#endif while ((PointerPde->u.Hard.Valid == 0) || (PointerPte->u.Hard.Valid == 0)) {
Modified: trunk/reactos/ntoskrnl/mm/ARM3/mminit.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/mm/ARM3/mminit.c?r... ============================================================================== --- trunk/reactos/ntoskrnl/mm/ARM3/mminit.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/mm/ARM3/mminit.c [iso-8859-1] Mon Jul 26 21:45:42 2010 @@ -153,6 +153,7 @@ PVOID MiSystemViewStart; SIZE_T MmSystemViewSize;
+#if (_MI_PAGING_LEVELS == 2) // // A copy of the system page directory (the page directory associated with the // System process) is kept (double-mapped) by the manager in order to lazily @@ -161,6 +162,7 @@ // PFN_NUMBER MmSystemPageDirectory[PD_COUNT]; PMMPTE MmSystemPagePtes; +#endif
// // The system cache starts right after hyperspace. The first few pages are for @@ -228,6 +230,9 @@ /* And these store the respective highest PTE/PDE address */ PMMPTE MiHighestUserPte; PMMPDE MiHighestUserPde; +#if (_MI_PAGING_LEVELS >= 3) +/* We need the highest PPE and PXE addresses */ +#endif
/* These variables define the system cache address space */ PVOID MmSystemCacheStart; @@ -1476,7 +1481,7 @@ PFN_NUMBER PageFrameIndex; KIRQL OldIrql; ULONG Size, BitMapSize; - +#if (_MI_PAGING_LEVELS == 2) // // Get the page frame number for the system page directory // @@ -1502,7 +1507,7 @@ ASSERT(PD_COUNT == 1); TempPte.u.Hard.PageFrameNumber = MmSystemPageDirectory[0]; MI_WRITE_VALID_PTE(PointerPte, TempPte); - +#endif // // Let's get back to paged pool work: size it up. // By default, it should be twice as big as nonpaged pool. @@ -1554,6 +1559,14 @@ // So now get the PDE for paged pool and zero it out // PointerPde = MiAddressToPde(MmPagedPoolStart); + +#if (_MI_PAGING_LEVELS >= 3) + /* On these systems, there's no double-mapping, so instead, the PPE and PXEs + * are setup to span the entire paged pool area, so there's no need for the + * system PD */ + ASSERT(FALSE); +#endif + RtlZeroMemory(PointerPde, (1 + MiAddressToPde(MmPagedPoolEnd) - PointerPde) * sizeof(MMPTE));
@@ -1573,7 +1586,14 @@ PageFrameIndex = MiRemoveZeroPage(0); TempPte.u.Hard.PageFrameNumber = PageFrameIndex; MI_WRITE_VALID_PTE(PointerPde, TempPte); - +#if (_MI_PAGING_LEVELS >= 3) + /* Use the PPE of MmPagedPoolStart that was setup above */ +// Bla = PFN_FROM_PTE(PpeAddress(MmPagedPool...)); + ASSERT(FALSE); +#else + /* Do it this way */ +// Bla = MmSystemPageDirectory[(PointerPde - (PMMPTE)PDE_BASE) / PDE_COUNT] +#endif /* Initialize the PFN entry for it */ MiInitializePfnForOtherProcess(PageFrameIndex, PointerPde, @@ -1700,7 +1720,10 @@ /* Highest PTE and PDE based on the addresses above */ MiHighestUserPte = MiAddressToPte(MmHighestUserAddress); MiHighestUserPde = MiAddressToPde(MmHighestUserAddress); - +#if (_MI_PAGING_LEVELS >= 3) + /* We need the highest PPE and PXE addresses */ + ASSERT(FALSE); +#endif // // Get the size of the boot loader's image allocations and then round // that region up to a PDE size, so that any PDEs we might create for
Modified: trunk/reactos/ntoskrnl/mm/ARM3/pagfault.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/mm/ARM3/pagfault.c... ============================================================================== --- trunk/reactos/ntoskrnl/mm/ARM3/pagfault.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/mm/ARM3/pagfault.c [iso-8859-1] Mon Jul 26 21:45:42 2010 @@ -463,7 +463,11 @@ // PointerPte = MiAddressToPte(Address); PointerPde = MiAddressToPde(Address); - +#if (_MI_PAGING_LEVELS >= 3) + /* We need the PPE and PXE addresses */ + ASSERT(FALSE); +#endif + // // Check for dispatch-level snafu // @@ -488,6 +492,11 @@ // if (Mode == UserMode) return STATUS_ACCESS_VIOLATION;
+#if (_MI_PAGING_LEVELS >= 3) + /* Need to check PXE and PDE validity */ + ASSERT(FALSE); +#endif + // // Is the PDE valid? // @@ -497,12 +506,12 @@ // Debug spew (eww!) // DPRINT("Invalid PDE\n"); - +#if (_MI_PAGING_LEVELS == 2) // // Handle mapping in "Special" PDE directoreis // MiCheckPdeForPagedPool(Address); - +#endif // // Now we SHOULD be good // @@ -556,7 +565,7 @@ // This might happen...not sure yet // DPRINT1("FAULT ON PAGE TABLES: %p %lx %lx!\n", Address, *PointerPte, *PointerPde); - +#if (_MI_PAGING_LEVELS == 2) // // Map in the page table // @@ -565,7 +574,7 @@ DPRINT1("PAGE TABLES FAULTED IN!\n"); return STATUS_SUCCESS; } - +#endif // // Otherwise the page table doesn't actually exist // @@ -650,6 +659,11 @@ /* Lock the working set */ MiLockProcessWorkingSet(CurrentProcess, CurrentThread);
+#if (_MI_PAGING_LEVELS >= 3) + /* Need to check/handle PPE and PXE validity too */ + ASSERT(FALSE); +#endif + /* First things first, is the PDE valid? */ ASSERT(PointerPde != MiAddressToPde(PTE_BASE)); ASSERT(PointerPde->u.Hard.LargePage == 0); @@ -679,6 +693,10 @@
/* We should come back with APCs enabled, and with a valid PDE */ ASSERT(KeAreAllApcsDisabled() == TRUE); +#if (_MI_PAGING_LEVELS >= 3) + /* Need to check/handle PPE and PXE validity too */ + ASSERT(FALSE); +#endif ASSERT(PointerPde->u.Hard.Valid == 1); }
Modified: trunk/reactos/ntoskrnl/mm/ARM3/pool.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/mm/ARM3/pool.c?rev... ============================================================================== --- trunk/reactos/ntoskrnl/mm/ARM3/pool.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/mm/ARM3/pool.c [iso-8859-1] Mon Jul 26 21:45:42 2010 @@ -329,14 +329,16 @@ /* Request a page */ PageFrameNumber = MiRemoveAnyPage(0); TempPte.u.Hard.PageFrameNumber = PageFrameNumber; - + +#if (_MI_PAGING_LEVELS >= 3) + /* On PAE/x64 systems, there's no double-buffering */ + ASSERT(FALSE); +#else // // Save it into our double-buffered system page directory // -#ifndef _M_AMD64 /* This seems to be making the assumption that one PDE is one page long */ C_ASSERT(PAGE_SIZE == (PD_COUNT * (sizeof(MMPTE) * PDE_COUNT))); -#endif MmSystemPagePtes[(ULONG_PTR)PointerPte & (PAGE_SIZE - 1) / sizeof(MMPTE)] = TempPte;
@@ -347,7 +349,7 @@
/* Write the actual PTE now */ MI_WRITE_VALID_PTE(PointerPte++, TempPte); - +#endif // // Move on to the next expansion address //
-
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