[cwittich] 62493: [uniata] update uniata to 45a3 fixes installation on ATI IXP700 SATA controller
Author: cwittich Date: Thu Mar 13 18:54:06 2014 New Revision: 62493
URL: http://svn.reactos.org/svn/reactos?rev=62493&view=rev Log: [uniata] update uniata to 45a3 fixes installation on ATI IXP700 SATA controller
Modified: trunk/reactos/drivers/storage/ide/uniata/bm_devs.h trunk/reactos/drivers/storage/ide/uniata/bsmaster.h trunk/reactos/drivers/storage/ide/uniata/id_ata.cpp trunk/reactos/drivers/storage/ide/uniata/id_dma.cpp trunk/reactos/drivers/storage/ide/uniata/id_init.cpp trunk/reactos/drivers/storage/ide/uniata/id_sata.cpp trunk/reactos/drivers/storage/ide/uniata/uniata_ver.h
Modified: trunk/reactos/drivers/storage/ide/uniata/bm_devs.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/drivers/storage/ide/uniata/... ============================================================================== --- trunk/reactos/drivers/storage/ide/uniata/bm_devs.h [iso-8859-1] (original) +++ trunk/reactos/drivers/storage/ide/uniata/bm_devs.h [iso-8859-1] Thu Mar 13 18:54:06 2014 @@ -1,6 +1,6 @@ /*++
-Copyright (c) 2002-2012 Alexandr A. Telyatnikov (Alter) +Copyright (c) 2002-2014 Alexandr A. Telyatnikov (Alter)
Module Name: bm_devs.h @@ -103,14 +103,6 @@ #define ATA_ATP865A 0x00081191 #define ATA_ATP865R 0x00091191
-#define ATA_AMD_ID 0x1022 -#define ATA_AMD755 0x74011022 -#define ATA_AMD756 0x74091022 -#define ATA_AMD766 0x74111022 -#define ATA_AMD768 0x74411022 -#define ATA_AMD8111 0x74691022 -#define ATA_AMD5536 0x209a1022 - #define ATA_ACER_LABS_ID 0x10b9 #define ATA_ALI_1533 0x153310b9 #define ATA_ALI_5228 0x522810b9 @@ -119,6 +111,24 @@ #define ATA_ALI_5287 0x528710b9 #define ATA_ALI_5288 0x528810b9 #define ATA_ALI_5289 0x528910b9 + +#define ATA_AMD_ID 0x1022 +#define ATA_AMD755 0x74011022 +#define ATA_AMD756 0x74091022 +#define ATA_AMD766 0x74111022 +#define ATA_AMD768 0x74411022 +#define ATA_AMD8111 0x74691022 +#define ATA_AMD5536 0x209a1022 +#define ATA_AMD_HUDSON2_S1 0x78001022 +#define ATA_AMD_HUDSON2_S2 0x78011022 +#define ATA_AMD_HUDSON2_S3 0x78021022 +#define ATA_AMD_HUDSON2_S4 0x78031022 +#define ATA_AMD_HUDSON2_S5 0x78041022 +#define ATA_AMD_HUDSON2 0x780c1022 + +#define ATA_ADAPTEC_ID 0x9005 +#define ATA_ADAPTEC_1420 0x02419005 +#define ATA_ADAPTEC_1430 0x02439005
#define ATA_ATI_ID 0x1002 #define ATA_ATI_IXP200 0x43491002 @@ -136,6 +146,7 @@ #define ATA_ATI_IXP700_S4 0x43931002 #define ATA_ATI_IXP800_S1 0x43941002 #define ATA_ATI_IXP800_S2 0x43951002 +#define ATA_ATI_4385 0x43851002
#define ATA_CENATEK_ID 0x16ca #define ATA_CENATEK_ROCKET 0x000116ca @@ -209,6 +220,10 @@ #define ATA_I82801IB_AH4 0x29238086 #define ATA_I82801IB_R1 0x29258086 #define ATA_I82801IB_S2 0x29268086 +#define ATA_I82801IBM_S1 0x29288086 +#define ATA_I82801IBM_AH 0x29298086 +#define ATA_I82801IBM_R1 0x292a8086 +#define ATA_I82801IBM_S2 0x292d8086 #define ATA_I82801JIB_S1 0x3a208086 #define ATA_I82801JIB_AH 0x3a228086 #define ATA_I82801JIB_R1 0x3a258086 @@ -265,13 +280,31 @@ #define ATA_PPT_R5 0x1e0e8086 #define ATA_PPT_R6 0x1e0f8086
+#define ATA_LPT_S1 0x8c008086 +#define ATA_LPT_S2 0x8c018086 +#define ATA_LPT_AH1 0x8c028086 +#define ATA_LPT_AH2 0x8c038086 +#define ATA_LPT_R1 0x8c048086 +#define ATA_LPT_R2 0x8c058086 +#define ATA_LPT_R3 0x8c068086 +#define ATA_LPT_R4 0x8c078086 +#define ATA_LPT_S3 0x8c088086 +#define ATA_LPT_S4 0x8c098086 +#define ATA_LPT_R5 0x8c0e8086 +#define ATA_LPT_R6 0x8c0f8086 + #define ATA_I31244 0x32008086 #define ATA_ISCH 0x811a8086 #define ATA_DH89XXCC 0x23238086
+#define ATA_COLETOCRK_AH1 0x23a38086 +#define ATA_COLETOCRK_S1 0x23a18086 +#define ATA_COLETOCRK_S2 0x23a68086 + #define ATA_JMICRON_ID 0x197b #define ATA_JMB360 0x2360197b #define ATA_JMB361 0x2361197b +#define ATA_JMB362 0x2362197b #define ATA_JMB363 0x2363197b #define ATA_JMB365 0x2365197b #define ATA_JMB366 0x2366197b @@ -596,12 +629,14 @@ #define PRNEW 1 #define PRTX 2 #define PRMIO 3 -#define PRIDX 4 #define PRTX4 0x0100 #define PRSX4K 0x0200 #define PRSX6K 0x0400 #define PRSATA 0x0800 -#define PRDUAL 0x1000 +#define PRCMBO 0x1000 +#define PRG2 0x2000 +#define PRCMBO2 (PRCMBO | PRG2) +#define PRSATA2 (PRSATA | PRG2)
#define SWKS33 0 #define SWKS66 1 @@ -611,6 +646,7 @@ #define SIIOLD 0 #define SIICMD 1 #define SIIMIO 2 +#define ATI700 3
#define SIIINTR 0x0100 #define SIIENINTR 0x0200 @@ -644,11 +680,11 @@ #define NV4OFF 0x0100 #define NVQ 0x0200
-#define VIA33 0 +#define VIA33 4 #define VIA66 1 #define VIA100 2 #define VIA133 3 -#define AMDNVIDIA 4 +#define AMDNVIDIA 0 #define AMDCABLE 0x0100 #define AMDBUG 0x0200 #define VIABAR 0x0400 @@ -692,12 +728,12 @@ PCI_DEV_HW_SPEC_BM( 5229, 10b9, 0x20, ATA_UDMA2, "ALI M5229 UDMA2" , ALIOLD ), PCI_DEV_HW_SPEC_BM( 5229, 10b9, 0x00, ATA_WDMA2, "ALI M5229 WDMA2" , ALIOLD ),
- PCI_DEV_HW_SPEC_BM( 7401, 1022, 0x00, ATA_UDMA2, "AMD 755" , AMDNVIDIA | 0x00 ), - PCI_DEV_HW_SPEC_BM( 7409, 1022, 0x00, ATA_UDMA4, "AMD 756" , AMDNVIDIA | UNIATA_NO80CHK ), - PCI_DEV_HW_SPEC_BM( 7411, 1022, 0x00, ATA_UDMA5, "AMD 766" , AMDNVIDIA | AMDBUG ), - PCI_DEV_HW_SPEC_BM( 7441, 1022, 0x00, ATA_UDMA5, "AMD 768" , AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 7469, 1022, 0x00, ATA_UDMA6, "AMD 8111" , AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 209a, 1022, 0x00, ATA_UDMA5, "AMD CS5536" , AMDNVIDIA ), + PCI_DEV_HW_SPEC_BM( 7401, 1022, 0x00, ATA_UDMA2, "AMD 755" , 0 | 0x00 ), + PCI_DEV_HW_SPEC_BM( 7409, 1022, 0x00, ATA_UDMA4, "AMD 756" , 0 | UNIATA_NO80CHK ), + PCI_DEV_HW_SPEC_BM( 7411, 1022, 0x00, ATA_UDMA5, "AMD 766" , 0 | AMDBUG ), + PCI_DEV_HW_SPEC_BM( 7441, 1022, 0x00, ATA_UDMA5, "AMD 768" , 0 ), + PCI_DEV_HW_SPEC_BM( 7469, 1022, 0x00, ATA_UDMA6, "AMD 8111" , 0 ), + PCI_DEV_HW_SPEC_BM( 209a, 1022, 0x00, ATA_UDMA5, "AMD CS5536" , 0 ),
PCI_DEV_HW_SPEC_BM( 4349, 1002, 0x00, ATA_UDMA5, "ATI IXP200" , 0 ), PCI_DEV_HW_SPEC_BM( 4369, 1002, 0x00, ATA_UDMA6, "ATI IXP300" , 0 ), @@ -706,9 +742,21 @@ PCI_DEV_HW_SPEC_BM( 4379, 1002, 0x00, ATA_SA150, "ATI IXP400" , SIIMIO | SIIBUG | SIINOSATAIRQ | UNIATA_SATA ), PCI_DEV_HW_SPEC_BM( 437a, 1002, 0x00, ATA_SA300, "ATI IXP400" , SIIMIO | SIIBUG | SIINOSATAIRQ | UNIATA_SATA ), PCI_DEV_HW_SPEC_BM( 438c, 1002, 0x00, ATA_UDMA6, "ATI IXP600" , 0 ), - PCI_DEV_HW_SPEC_BM( 4380, 1002, 0x00, ATA_SA150, "ATI IXP600" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 4380, 1002, 0x00, ATA_SA300, "ATI IXP600" , UNIATA_SATA | UNIATA_AHCI ), PCI_DEV_HW_SPEC_BM( 439c, 1002, 0x00, ATA_UDMA6, "ATI IXP700" , 0 ), - PCI_DEV_HW_SPEC_BM( 4390, 1002, 0x00, ATA_SA150, "ATI IXP700" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 4390, 1002, 0x00, ATA_SA300, "ATI IXP700" , ATI700 | UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 4391, 1002, 0x00, ATA_SA300, "ATI IXP700" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 4392, 1002, 0x00, ATA_SA300, "ATI IXP700" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 4393, 1002, 0x00, ATA_SA300, "ATI IXP700" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 4394, 1002, 0x00, ATA_SA300, "ATI IXP700/800" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 4395, 1002, 0x00, ATA_SA300, "ATI IXP700/800" , UNIATA_SATA | UNIATA_AHCI ), + + PCI_DEV_HW_SPEC_BM( 780c, 1002, 0x00, ATA_UDMA6, "ATI Hudson-2" , 0 ), + PCI_DEV_HW_SPEC_BM( 7800, 1002, 0x00, ATA_SA300, "ATI Hudson-2" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 7801, 1002, 0x00, ATA_SA300, "ATI Hudson-2" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 7802, 1002, 0x00, ATA_SA300, "ATI Hudson-2" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 7803, 1002, 0x00, ATA_SA300, "ATI Hudson-2" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 7804, 1002, 0x00, ATA_SA300, "ATI Hudson-2" , UNIATA_SATA | UNIATA_AHCI ),
PCI_DEV_HW_SPEC_BM( 0004, 1103, 0x05, ATA_UDMA6, "HighPoint HPT372" , HPT372 | 0x00 | UNIATA_RAID_CONTROLLER), PCI_DEV_HW_SPEC_BM( 0004, 1103, 0x03, ATA_UDMA5, "HighPoint HPT370" , HPT370 | 0x00 | UNIATA_RAID_CONTROLLER), @@ -778,7 +826,6 @@
PCI_DEV_HW_SPEC_BM( 2920, 8086, 0x00, ATA_SA300, "Intel ICH9" , I6CH | UNIATA_SATA ), PCI_DEV_HW_SPEC_BM( 2926, 8086, 0x00, ATA_SA300, "Intel ICH9" , I6CH2 | UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 282a, 8086, 0x00, ATA_SA300, "Intel ICH9" , I6CH2 | UNIATA_SATA ), PCI_DEV_HW_SPEC_BM( 2921, 8086, 0x00, ATA_SA300, "Intel ICH9" , UNIATA_SATA | UNIATA_AHCI ),/* ??? */ PCI_DEV_HW_SPEC_BM( 2922, 8086, 0x00, ATA_SA300, "Intel ICH9" , UNIATA_SATA | UNIATA_AHCI ), PCI_DEV_HW_SPEC_BM( 2923, 8086, 0x00, ATA_SA300, "Intel ICH9" , UNIATA_SATA | UNIATA_AHCI ), @@ -846,56 +893,150 @@ PCI_DEV_HW_SPEC_BM( 1e0e, 8086, 0x00, ATA_SA300, "Intel Panther Point" , UNIATA_SATA | UNIATA_AHCI ), PCI_DEV_HW_SPEC_BM( 1e0f, 8086, 0x00, ATA_SA300, "Intel Panther Point" , UNIATA_SATA | UNIATA_AHCI ),
+ PCI_DEV_HW_SPEC_BM( 8c00, 8086, 0x00, ATA_SA300, "Intel Lynx Point" , I6CH | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 8c01, 8086, 0x00, ATA_SA300, "Intel Lynx Point" , I6CH | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 8c02, 8086, 0x00, ATA_SA300, "Intel Lynx Point" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 8c03, 8086, 0x00, ATA_SA300, "Intel Lynx Point" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 8c04, 8086, 0x00, ATA_SA300, "Intel Lynx Point" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 8c05, 8086, 0x00, ATA_SA300, "Intel Lynx Point" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 8c06, 8086, 0x00, ATA_SA300, "Intel Lynx Point" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 8c07, 8086, 0x00, ATA_SA300, "Intel Lynx Point" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 8c08, 8086, 0x00, ATA_SA300, "Intel Lynx Point" , I6CH2 | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 8c09, 8086, 0x00, ATA_SA300, "Intel Lynx Point" , I6CH2 | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 8c0e, 8086, 0x00, ATA_SA300, "Intel Lynx Point" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 8c0f, 8086, 0x00, ATA_SA300, "Intel Lynx Point" , UNIATA_SATA | UNIATA_AHCI ), + // PCI_DEV_HW_SPEC_BM( 3200, 8086, 0x00, ATA_SA150, "Intel 31244" , UNIATA_SATA ), PCI_DEV_HW_SPEC_BM( 811a, 8086, 0x00, ATA_UDMA5, "Intel SCH" , 0 ), PCI_DEV_HW_SPEC_BM( 2323, 8086, 0x00, ATA_SA300, "Intel DH98xxCC" , UNIATA_SATA | UNIATA_AHCI ),
- PCI_DEV_HW_SPEC_BM( 2360, 197b, 0x00, ATA_SA300, "JMB360" , UNIATA_SATA | UNIATA_AHCI ), - - PCI_DEV_HW_SPEC_BM( 2361, 197b, 0x00, ATA_UDMA6, "JMB361" , 0 ), - PCI_DEV_HW_SPEC_BM( 2363, 197b, 0x00, ATA_UDMA6, "JMB363" , 0 ), - PCI_DEV_HW_SPEC_BM( 2365, 197b, 0x00, ATA_UDMA6, "JMB365" , 0 ), - PCI_DEV_HW_SPEC_BM( 2366, 197b, 0x00, ATA_UDMA6, "JMB366" , 0 ), - PCI_DEV_HW_SPEC_BM( 2368, 197b, 0x00, ATA_UDMA6, "JMB368" , 0 ), + PCI_DEV_HW_SPEC_BM( 23a3, 8086, 0x00, ATA_SA300, "COLETOCRK" , I6CH2 | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 23a1, 8086, 0x00, ATA_SA300, "COLETOCRK" , I6CH2 | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 23a6, 8086, 0x00, ATA_SA300, "COLETOCRK" , UNIATA_SATA | UNIATA_AHCI ), + + PCI_DEV_HW_SPEC_BM( 2360, 197b, 0x00, ATA_SA300, "JMB360" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 2361, 197b, 0x00, ATA_UDMA6, "JMB361" , 0 ), + PCI_DEV_HW_SPEC_BM( 2362, 197b, 0x00, ATA_SA300, "JMB362" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 2363, 197b, 0x00, ATA_UDMA6, "JMB363" , 0 ), + PCI_DEV_HW_SPEC_BM( 2365, 197b, 0x00, ATA_UDMA6, "JMB365" , 0 ), + PCI_DEV_HW_SPEC_BM( 2366, 197b, 0x00, ATA_UDMA6, "JMB366" , 0 ), + PCI_DEV_HW_SPEC_BM( 2368, 197b, 0x00, ATA_UDMA6, "JMB368" , 0 ), /* - PCI_DEV_HW_SPEC_BM( 5040, 11ab, 0x00, ATA_SA150, "Marvell 88SX5040" , UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 5041, 11ab, 0x00, ATA_SA150, "Marvell 88SX5041" , UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 5080, 11ab, 0x00, ATA_SA150, "Marvell 88SX5080" , UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 5081, 11ab, 0x00, ATA_SA150, "Marvell 88SX5081" , UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 6041, 11ab, 0x00, ATA_SA300, "Marvell 88SX6041" , UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 6081, 11ab, 0x00, ATA_SA300, "Marvell 88SX6081" , UNIATA_SATA ),*/ - PCI_DEV_HW_SPEC_BM( 6101, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6101" , 0 ), - PCI_DEV_HW_SPEC_BM( 6121, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6121" , 0 ), - PCI_DEV_HW_SPEC_BM( 6145, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6145" , 0 ), - - PCI_DEV_HW_SPEC_BM( 01bc, 10de, 0x00, ATA_UDMA5, "nVidia nForce" , AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 0065, 10de, 0x00, ATA_UDMA6, "nVidia nForce2" , AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 0085, 10de, 0x00, ATA_UDMA6, "nVidia nForce2 Pro",AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 008e, 10de, 0x00, ATA_SA150, "nVidia nForce2 Pro S1",UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 00d5, 10de, 0x00, ATA_UDMA6, "nVidia nForce3" , AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 00e5, 10de, 0x00, ATA_UDMA6, "nVidia nForce3 Pro",AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 00e3, 10de, 0x00, ATA_SA150, "nVidia nForce3 Pro S1",UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 00ee, 10de, 0x00, ATA_SA150, "nVidia nForce3 Pro S2",UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 0035, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP", AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 0036, 10de, 0x00, ATA_SA150, "nVidia nForce MCP S1",NV4OFF | UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 003e, 10de, 0x00, ATA_SA150, "nVidia nForce MCP S2",NV4OFF | UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 0053, 10de, 0x00, ATA_UDMA6, "nVidia nForce CK804", AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 0054, 10de, 0x00, ATA_SA300, "nVidia nForce CK804 S1",NV4OFF | UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 0055, 10de, 0x00, ATA_SA300, "nVidia nForce CK804 S2",NV4OFF | UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 0265, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP51", AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 0266, 10de, 0x00, ATA_SA300, "nVidia nForce MCP51 S1",NV4OFF | NVQ | UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 0267, 10de, 0x00, ATA_SA300, "nVidia nForce MCP51 S2",NV4OFF | NVQ | UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 036e, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP55", AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 037e, 10de, 0x00, ATA_SA300, "nVidia nForce MCP55 S1",NV4OFF | NVQ | UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 037f, 10de, 0x00, ATA_SA300, "nVidia nForce MCP55 S2",NV4OFF | NVQ | UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 03ec, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP61", AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 03e7, 10de, 0x00, ATA_SA300, "nVidia nForce MCP61 S1",NV4OFF | NVQ | UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 03f6, 10de, 0x00, ATA_SA300, "nVidia nForce MCP61 S2",NV4OFF | NVQ | UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 03f7, 10de, 0x00, ATA_SA300, "nVidia nForce MCP61 S3",NV4OFF | NVQ | UNIATA_SATA ), - PCI_DEV_HW_SPEC_BM( 0448, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP65", AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 0560, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP67", AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 056c, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP73", AMDNVIDIA ), - PCI_DEV_HW_SPEC_BM( 0759, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP77", AMDNVIDIA ), + PCI_DEV_HW_SPEC_BM( 5040, 11ab, 0x00, ATA_SA150, "Marvell 88SX5040" , UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 5041, 11ab, 0x00, ATA_SA150, "Marvell 88SX5041" , UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 5080, 11ab, 0x00, ATA_SA150, "Marvell 88SX5080" , UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 5081, 11ab, 0x00, ATA_SA150, "Marvell 88SX5081" , UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 6041, 11ab, 0x00, ATA_SA300, "Marvell 88SX6041" , UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 6081, 11ab, 0x00, ATA_SA300, "Marvell 88SX6081" , UNIATA_SATA ),*/ + PCI_DEV_HW_SPEC_BM( 6101, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6101" , 0 ), + PCI_DEV_HW_SPEC_BM( 6102, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6102" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 6111, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6111" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 6121, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6121" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 6141, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6141" , UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 6145, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6145" , UNIATA_SATA | UNIATA_AHCI ), +/* PCI_DEV_HW_SPEC_BM( 91a4, 1b4b, 0x00, ATA_UDMA6, "Marvell 88SE912x" , 0 ),*/ + + PCI_DEV_HW_SPEC_BM( 01bc, 10de, 0x00, ATA_UDMA5, "nVidia nForce" , 0 ), + PCI_DEV_HW_SPEC_BM( 0065, 10de, 0x00, ATA_UDMA6, "nVidia nForce2" , 0 ), + PCI_DEV_HW_SPEC_BM( 0085, 10de, 0x00, ATA_UDMA6, "nVidia nForce2 Pro",0 ), + PCI_DEV_HW_SPEC_BM( 008e, 10de, 0x00, ATA_SA150, "nVidia nForce2 Pro S1",UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 00d5, 10de, 0x00, ATA_UDMA6, "nVidia nForce3" , 0 ), + PCI_DEV_HW_SPEC_BM( 00e5, 10de, 0x00, ATA_UDMA6, "nVidia nForce3 Pro",0 ), + PCI_DEV_HW_SPEC_BM( 00e3, 10de, 0x00, ATA_SA150, "nVidia nForce3 Pro S1",UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 00ee, 10de, 0x00, ATA_SA150, "nVidia nForce3 Pro S2",UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 0035, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP", 0 ), + PCI_DEV_HW_SPEC_BM( 0036, 10de, 0x00, ATA_SA150, "nVidia nForce MCP S1",NV4OFF | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 003e, 10de, 0x00, ATA_SA150, "nVidia nForce MCP S2",NV4OFF | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 0053, 10de, 0x00, ATA_UDMA6, "nVidia nForce CK804", 0 ), + PCI_DEV_HW_SPEC_BM( 0054, 10de, 0x00, ATA_SA300, "nVidia nForce CK804 S1",NV4OFF | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 0055, 10de, 0x00, ATA_SA300, "nVidia nForce CK804 S2",NV4OFF | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 0265, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP51", 0 ), + PCI_DEV_HW_SPEC_BM( 0266, 10de, 0x00, ATA_SA300, "nVidia nForce MCP51 S1",NV4OFF | NVQ | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 0267, 10de, 0x00, ATA_SA300, "nVidia nForce MCP51 S2",NV4OFF | NVQ | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 036e, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP55", 0 ), + PCI_DEV_HW_SPEC_BM( 037e, 10de, 0x00, ATA_SA300, "nVidia nForce MCP55 S1",NV4OFF | NVQ | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 037f, 10de, 0x00, ATA_SA300, "nVidia nForce MCP55 S2",NV4OFF | NVQ | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 03ec, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP61", 0 ), + PCI_DEV_HW_SPEC_BM( 03e7, 10de, 0x00, ATA_SA300, "nVidia nForce MCP61 S1",NV4OFF | NVQ | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 03f6, 10de, 0x00, ATA_SA300, "nVidia nForce MCP61 S2",NV4OFF | NVQ | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 03f7, 10de, 0x00, ATA_SA300, "nVidia nForce MCP61 S3",NV4OFF | NVQ | UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 0448, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP65", 0 ), + PCI_DEV_HW_SPEC_BM( 044c, 10de, 0x00, ATA_SA300, "nVidia nForce MCP65 A0", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 044d, 10de, 0x00, ATA_SA300, "nVidia nForce MCP65 A1", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 044e, 10de, 0x00, ATA_SA300, "nVidia nForce MCP65 A2", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 044f, 10de, 0x00, ATA_SA300, "nVidia nForce MCP65 A3", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 045c, 10de, 0x00, ATA_SA300, "nVidia nForce MCP65 A4", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 045d, 10de, 0x00, ATA_SA300, "nVidia nForce MCP65 A5", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 045e, 10de, 0x00, ATA_SA300, "nVidia nForce MCP65 A6", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 045f, 10de, 0x00, ATA_SA300, "nVidia nForce MCP65 A7", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0560, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP67", 0 ), + PCI_DEV_HW_SPEC_BM( 0550, 10de, 0x00, ATA_SA300, "nVidia nForce MCP67 A0", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0551, 10de, 0x00, ATA_SA300, "nVidia nForce MCP67 A1", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0552, 10de, 0x00, ATA_SA300, "nVidia nForce MCP67 A2", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0553, 10de, 0x00, ATA_SA300, "nVidia nForce MCP67 A3", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0554, 10de, 0x00, ATA_SA300, "nVidia nForce MCP67 A4", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0555, 10de, 0x00, ATA_SA300, "nVidia nForce MCP67 A5", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0556, 10de, 0x00, ATA_SA300, "nVidia nForce MCP67 A6", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0557, 10de, 0x00, ATA_SA300, "nVidia nForce MCP67 A7", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0558, 10de, 0x00, ATA_SA300, "nVidia nForce MCP67 A8", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0559, 10de, 0x00, ATA_SA300, "nVidia nForce MCP67 A9", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 055A, 10de, 0x00, ATA_SA300, "nVidia nForce MCP67 AA", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 055B, 10de, 0x00, ATA_SA300, "nVidia nForce MCP67 AB", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0584, 10de, 0x00, ATA_SA300, "nVidia nForce MCP67 AC", UNIATA_SATA | UNIATA_AHCI ), + + PCI_DEV_HW_SPEC_BM( 056c, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP73", 0 ), + PCI_DEV_HW_SPEC_BM( 07f0, 10de, 0x00, ATA_SA300, "nVidia nForce MCP73 A0", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 07f1, 10de, 0x00, ATA_SA300, "nVidia nForce MCP73 A1", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 07f2, 10de, 0x00, ATA_SA300, "nVidia nForce MCP73 A2", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 07f3, 10de, 0x00, ATA_SA300, "nVidia nForce MCP73 A3", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 07f4, 10de, 0x00, ATA_SA300, "nVidia nForce MCP73 A4", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 07f5, 10de, 0x00, ATA_SA300, "nVidia nForce MCP73 A5", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 07f6, 10de, 0x00, ATA_SA300, "nVidia nForce MCP73 A6", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 07f7, 10de, 0x00, ATA_SA300, "nVidia nForce MCP73 A7", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 07f8, 10de, 0x00, ATA_SA300, "nVidia nForce MCP73 A8", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 07f9, 10de, 0x00, ATA_SA300, "nVidia nForce MCP73 A9", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 07fa, 10de, 0x00, ATA_SA300, "nVidia nForce MCP73 AA", UNIATA_SATA | UNIATA_AHCI ), + + PCI_DEV_HW_SPEC_BM( 07fb, 10de, 0x00, ATA_SA300, "nVidia nForce MCP73 AB", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0759, 10de, 0x00, ATA_UDMA6, "nVidia nForce MCP77", 0 ), + PCI_DEV_HW_SPEC_BM( 0ad0, 10de, 0x00, ATA_SA300, "nVidia nForce MCP77 A0", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ad1, 10de, 0x00, ATA_SA300, "nVidia nForce MCP77 A1", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ad2, 10de, 0x00, ATA_SA300, "nVidia nForce MCP77 A2", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ad3, 10de, 0x00, ATA_SA300, "nVidia nForce MCP77 A3", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ad4, 10de, 0x00, ATA_SA300, "nVidia nForce MCP77 A4", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ad5, 10de, 0x00, ATA_SA300, "nVidia nForce MCP77 A5", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ad6, 10de, 0x00, ATA_SA300, "nVidia nForce MCP77 A6", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ad7, 10de, 0x00, ATA_SA300, "nVidia nForce MCP77 A7", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ad8, 10de, 0x00, ATA_SA300, "nVidia nForce MCP77 A8", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ad9, 10de, 0x00, ATA_SA300, "nVidia nForce MCP77 A9", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ada, 10de, 0x00, ATA_SA300, "nVidia nForce MCP77 AA", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0adb, 10de, 0x00, ATA_SA300, "nVidia nForce MCP77 AB", UNIATA_SATA | UNIATA_AHCI ), + + PCI_DEV_HW_SPEC_BM( 0ab4, 10de, 0x00, ATA_SA300, "nVidia nForce MCP79 A0", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ab5, 10de, 0x00, ATA_SA300, "nVidia nForce MCP79 A1", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ab6, 10de, 0x00, ATA_SA300, "nVidia nForce MCP79 A2", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ab7, 10de, 0x00, ATA_SA300, "nVidia nForce MCP79 A3", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ab8, 10de, 0x00, ATA_SA300, "nVidia nForce MCP79 A4", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0ab9, 10de, 0x00, ATA_SA300, "nVidia nForce MCP79 A5", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0aba, 10de, 0x00, ATA_SA300, "nVidia nForce MCP79 A6", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0abb, 10de, 0x00, ATA_SA300, "nVidia nForce MCP79 A7", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0abc, 10de, 0x00, ATA_SA300, "nVidia nForce MCP79 A8", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0abd, 10de, 0x00, ATA_SA300, "nVidia nForce MCP79 A9", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0abe, 10de, 0x00, ATA_SA300, "nVidia nForce MCP79 AA", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0abf, 10de, 0x00, ATA_SA300, "nVidia nForce MCP79 AB", UNIATA_SATA | UNIATA_AHCI ), + + PCI_DEV_HW_SPEC_BM( 0d84, 10de, 0x00, ATA_SA300, "nVidia nForce MCP89 A0", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0d85, 10de, 0x00, ATA_SA300, "nVidia nForce MCP89 A1", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0d86, 10de, 0x00, ATA_SA300, "nVidia nForce MCP89 A2", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0d87, 10de, 0x00, ATA_SA300, "nVidia nForce MCP89 A3", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0d88, 10de, 0x00, ATA_SA300, "nVidia nForce MCP89 A4", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0d89, 10de, 0x00, ATA_SA300, "nVidia nForce MCP89 A5", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0d8a, 10de, 0x00, ATA_SA300, "nVidia nForce MCP89 A6", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0d8b, 10de, 0x00, ATA_SA300, "nVidia nForce MCP89 A7", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0d8c, 10de, 0x00, ATA_SA300, "nVidia nForce MCP89 A8", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0d8d, 10de, 0x00, ATA_SA300, "nVidia nForce MCP89 A9", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0d8e, 10de, 0x00, ATA_SA300, "nVidia nForce MCP89 AA", UNIATA_SATA | UNIATA_AHCI ), + PCI_DEV_HW_SPEC_BM( 0d8f, 10de, 0x00, ATA_SA300, "nVidia nForce MCP89 AB", UNIATA_SATA | UNIATA_AHCI ),
PCI_DEV_HW_SPEC_BM( 0502, 100b, 0x00, ATA_UDMA2, "National Geode SC1100", 0 ),
@@ -913,18 +1054,28 @@ PCI_DEV_HW_SPEC_BM( 7275, 105a, 0x00, ATA_UDMA6, "Promise PDC20277" , PRTX | 0x00 | UNIATA_RAID_CONTROLLER), PCI_DEV_HW_SPEC_BM( 3318, 105a, 0x00, ATA_SA150, "Promise PDC20318" , PRMIO | PRSATA | UNIATA_RAID_CONTROLLER | UNIATA_SATA), PCI_DEV_HW_SPEC_BM( 3319, 105a, 0x00, ATA_SA150, "Promise PDC20319" , PRMIO | PRSATA | UNIATA_RAID_CONTROLLER | UNIATA_SATA), - PCI_DEV_HW_SPEC_BM( 3371, 105a, 0x00, ATA_SA150, "Promise PDC20371" , PRMIO | PRSATA | UNIATA_RAID_CONTROLLER | UNIATA_SATA), - PCI_DEV_HW_SPEC_BM( 3375, 105a, 0x00, ATA_SA150, "Promise PDC20375" , PRMIO | PRSATA | UNIATA_RAID_CONTROLLER | UNIATA_SATA), - PCI_DEV_HW_SPEC_BM( 3376, 105a, 0x00, ATA_SA150, "Promise PDC20376" , PRMIO | PRSATA | UNIATA_RAID_CONTROLLER | UNIATA_SATA), - PCI_DEV_HW_SPEC_BM( 3377, 105a, 0x00, ATA_SA150, "Promise PDC20377" , PRMIO | PRSATA | UNIATA_RAID_CONTROLLER | UNIATA_SATA), - PCI_DEV_HW_SPEC_BM( 3373, 105a, 0x00, ATA_SA150, "Promise PDC20378" , PRMIO | PRSATA | UNIATA_RAID_CONTROLLER | UNIATA_SATA), - PCI_DEV_HW_SPEC_BM( 3372, 105a, 0x00, ATA_SA150, "Promise PDC20379" , PRMIO | PRSATA | UNIATA_RAID_CONTROLLER | UNIATA_SATA), - PCI_DEV_HW_SPEC_BM( 6617, 105a, 0x00, ATA_UDMA6, "Promise PDC20617" , PRMIO | PRDUAL | UNIATA_RAID_CONTROLLER), - PCI_DEV_HW_SPEC_BM( 6626, 105a, 0x00, ATA_UDMA6, "Promise PDC20618" , PRMIO | PRDUAL | UNIATA_RAID_CONTROLLER), - PCI_DEV_HW_SPEC_BM( 6629, 105a, 0x00, ATA_UDMA6, "Promise PDC20619" , PRMIO | PRDUAL | UNIATA_RAID_CONTROLLER), - PCI_DEV_HW_SPEC_BM( 6620, 105a, 0x00, ATA_UDMA6, "Promise PDC20620" , PRMIO | PRDUAL | UNIATA_RAID_CONTROLLER), + PCI_DEV_HW_SPEC_BM( 3371, 105a, 0x00, ATA_SA150, "Promise PDC20371" , PRMIO | PRCMBO | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3375, 105a, 0x00, ATA_SA150, "Promise PDC20375" , PRMIO | PRCMBO | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3376, 105a, 0x00, ATA_SA150, "Promise PDC20376" , PRMIO | PRCMBO | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3377, 105a, 0x00, ATA_SA150, "Promise PDC20377" , PRMIO | PRCMBO | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3373, 105a, 0x00, ATA_SA150, "Promise PDC20378" , PRMIO | PRCMBO | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3372, 105a, 0x00, ATA_SA150, "Promise PDC20379" , PRMIO | PRCMBO | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3571, 105a, 0x00, ATA_SA150, "Promise PDC20571" , PRMIO | PRCMBO2 | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3d75, 105a, 0x00, ATA_SA150, "Promise PDC20575" , PRMIO | PRCMBO2 | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3574, 105a, 0x00, ATA_SA150, "Promise PDC20579" , PRMIO | PRCMBO2 | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3570, 105a, 0x00, ATA_SA300, "Promise PDC20771" , PRMIO | PRCMBO2 | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3d73, 105a, 0x00, ATA_SA300, "Promise PDC40775" , PRMIO | PRCMBO2 | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 6617, 105a, 0x00, ATA_UDMA6, "Promise PDC20617" , PRMIO | 0x00 | UNIATA_RAID_CONTROLLER), + PCI_DEV_HW_SPEC_BM( 6626, 105a, 0x00, ATA_UDMA6, "Promise PDC20618" , PRMIO | 0x00 | UNIATA_RAID_CONTROLLER), + PCI_DEV_HW_SPEC_BM( 6629, 105a, 0x00, ATA_UDMA6, "Promise PDC20619" , PRMIO | 0x00 | UNIATA_RAID_CONTROLLER), + PCI_DEV_HW_SPEC_BM( 6620, 105a, 0x00, ATA_UDMA6, "Promise PDC20620" , PRMIO | 0x00 | UNIATA_RAID_CONTROLLER), /* PCI_DEV_HW_SPEC_BM( 6621, 105a, 0x00, ATA_UDMA6, "Promise PDC20621" , PRMIO | PRSX4X | UNIATA_RAID_CONTROLLER), PCI_DEV_HW_SPEC_BM( 6622, 105a, 0x00, ATA_UDMA6, "Promise PDC20622" , PRMIO | PRSX4X | UNIATA_RAID_CONTROLLER),*/ + PCI_DEV_HW_SPEC_BM( 3571, 105a, 0x00, ATA_SA150, "Promise PDC40518" , PRMIO | PRSATA2 | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3d75, 105a, 0x00, ATA_SA150, "Promise PDC40519" , PRMIO | PRSATA2 | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3574, 105a, 0x00, ATA_SA150, "Promise PDC40718" , PRMIO | PRSATA2 | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3570, 105a, 0x00, ATA_SA300, "Promise PDC40719" , PRMIO | PRSATA2 | UNIATA_RAID_CONTROLLER | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 3d73, 105a, 0x00, ATA_SA300, "Promise PDC40779" , PRMIO | PRSATA2 | UNIATA_RAID_CONTROLLER | UNIATA_SATA),
PCI_DEV_HW_SPEC_BM( 0211, 1166, 0x00, ATA_UDMA2, "ServerWorks ROSB4", SWKS33 | UNIATA_NO_DPC ), PCI_DEV_HW_SPEC_BM( 0212, 1166, 0x92, ATA_UDMA5, "ServerWorks CSB5" , SWKS100 ), @@ -989,6 +1140,13 @@ PCI_DEV_HW_SPEC_BM( 5513, 1039, 0xc2, ATA_UDMA2, "SiS ATA-xxx" , 0 ), PCI_DEV_HW_SPEC_BM( 5513, 1039, 0x00, ATA_WDMA2, "SiS ATA-xxx" , 0 ), PCI_DEV_HW_SPEC_BM( 0601, 1039, 0x00, ATA_WDMA2, "SiS ATA-xxx" , 0 ), + + PCI_DEV_HW_SPEC_BM( 1183, 1039, 0x00, ATA_UDMA6, "SiS PATA-1183" , SIS133NEW), + PCI_DEV_HW_SPEC_BM( 1182, 1039, 0x00, ATA_SA150, "SiS SATA 1182" , SISSATA | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 0183, 1039, 0x00, ATA_SA150, "SiS SATA 183" , SISSATA | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 0182, 1039, 0x00, ATA_SA150, "SiS SATA 182" , SISSATA | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 0181, 1039, 0x00, ATA_SA150, "SiS SATA 181" , SISSATA | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 0180, 1039, 0x00, ATA_SA150, "SiS SATA 180" , SISSATA | UNIATA_SATA),
/* PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x41, ATA_UDMA2, "VIA 82C586B" , VIA33 | 0x00 ), PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x40, ATA_UDMA2, "VIA 82C586B" , VIA33 | VIAPRQ ), @@ -1016,7 +1174,7 @@ PCI_DEV_HW_SPEC_BM( 5337, 1106, 0x00, ATA_SA150, "VIA 8237S" , 0 | UNIATA_SATA ), PCI_DEV_HW_SPEC_BM( 5372, 1106, 0x00, ATA_SA300, "VIA 8237" , 0 | UNIATA_SATA ), PCI_DEV_HW_SPEC_BM( 7372, 1106, 0x00, ATA_SA300, "VIA 8237" , 0 | UNIATA_SATA ), - //PCI_DEV_HW_SPEC_BM( 3349, 1106, 0x00, ATA_SA150, "VIA 8251" , VIAAHCI| UNIATA_SATA ), + PCI_DEV_HW_SPEC_BM( 3349, 1106, 0x00, ATA_SA150, "VIA 8251" , 0 | UNIATA_SATA | UNIATA_AHCI ),
PCI_DEV_HW_SPEC_BM( c693, 1080, 0x00, ATA_WDMA2, "Cypress 82C693" ,0 ),
@@ -1045,7 +1203,8 @@
PCI_DEV_HW_SPEC_BM( 0102, 1078, 0x00, ATA_UDMA2, "Cyrix 5530" , 0 ),
- PCI_DEV_HW_SPEC_BM( 0102, 1042, 0x00, ATA_PIO4, "RZ 100x" , 0 ), + PCI_DEV_HW_SPEC_BM( 1000, 1042, 0x00, ATA_PIO4, "RZ 100x" , 0 ), + PCI_DEV_HW_SPEC_BM( 1001, 1042, 0x00, ATA_PIO4, "RZ 100x" , 0 ),
PCI_DEV_HW_SPEC_BM( 8172, 1283, 0x00, ATA_UDMA2, "IT8172" , 0 ), PCI_DEV_HW_SPEC_BM( 8213, 1283, 0x00, ATA_UDMA6, "IT8213F" , ITE_133_NEW ),
Modified: trunk/reactos/drivers/storage/ide/uniata/bsmaster.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/drivers/storage/ide/uniata/... ============================================================================== --- trunk/reactos/drivers/storage/ide/uniata/bsmaster.h [iso-8859-1] (original) +++ trunk/reactos/drivers/storage/ide/uniata/bsmaster.h [iso-8859-1] Thu Mar 13 18:54:06 2014 @@ -1,6 +1,6 @@ /*++
-Copyright (c) 2002-2012 Alexandr A. Telyatnikov (Alter) +Copyright (c) 2002-2014 Alexandr A. Telyatnikov (Alter)
Module Name: bsmaster.h @@ -31,10 +31,10 @@ Revision History:
Code was created by - Alter, Copyright (c) 2002-2008 - - Some definitions were taken from FreeBSD 4.3-4.6 ATA driver by - Søren Schmidt, Copyright (c) 1998,1999,2000,2001 + Alter, Copyright (c) 2002-2014 + + Some definitions were taken from FreeBSD 4.3-9.2 ATA driver by + Søren Schmidt, Copyright (c) 1998-2014
--*/
@@ -245,6 +245,12 @@ ULONG Reserved:27; } BOHC;
+#define AHCI_BOHC_BB 0x00000001 +#define AHCI_BOHC_OOC 0x00000002 +#define AHCI_BOHC_SOOE 0x00000004 +#define AHCI_BOHC_OOS 0x00000008 +#define AHCI_BOHC_BOS 0x00000010 + UCHAR Reserved2[0x74];
UCHAR VendorSpec[0x60]; @@ -289,6 +295,22 @@
} SATA_SSTATUS_REG, *PSATA_SSTATUS_REG;
+#define ATA_SS_DET_MASK 0x0000000f +#define ATA_SS_DET_NO_DEVICE 0x00000000 +#define ATA_SS_DET_DEV_PRESENT 0x00000001 +#define ATA_SS_DET_PHY_ONLINE 0x00000003 +#define ATA_SS_DET_PHY_OFFLINE 0x00000004 + +#define ATA_SS_SPD_MASK 0x000000f0 +#define ATA_SS_SPD_NO_SPEED 0x00000000 +#define ATA_SS_SPD_GEN1 0x00000010 +#define ATA_SS_SPD_GEN2 0x00000020 + +#define ATA_SS_IPM_MASK 0x00000f00 +#define ATA_SS_IPM_NO_DEVICE 0x00000000 +#define ATA_SS_IPM_ACTIVE 0x00000100 +#define ATA_SS_IPM_PARTIAL 0x00000200 +#define ATA_SS_IPM_SLUMBER 0x00000600
typedef union _SATA_SCONTROL_REG {
@@ -322,6 +344,21 @@
} SATA_SCONTROL_REG, *PSATA_SCONTROL_REG;
+#define ATA_SC_DET_MASK 0x0000000f +#define ATA_SC_DET_IDLE 0x00000000 +#define ATA_SC_DET_RESET 0x00000001 +#define ATA_SC_DET_DISABLE 0x00000004 + +#define ATA_SC_SPD_MASK 0x000000f0 +#define ATA_SC_SPD_NO_SPEED 0x00000000 +#define ATA_SC_SPD_SPEED_GEN1 0x00000010 +#define ATA_SC_SPD_SPEED_GEN2 0x00000020 +#define ATA_SC_SPD_SPEED_GEN3 0x00000040 + +#define ATA_SC_IPM_MASK 0x00000f00 +#define ATA_SC_IPM_NONE 0x00000000 +#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 +#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
typedef union _SATA_SERROR_REG {
@@ -358,6 +395,22 @@
} SATA_SERROR_REG, *PSATA_SERROR_REG;
+#define ATA_SE_DATA_CORRECTED 0x00000001 +#define ATA_SE_COMM_CORRECTED 0x00000002 +#define ATA_SE_DATA_ERR 0x00000100 +#define ATA_SE_COMM_ERR 0x00000200 +#define ATA_SE_PROT_ERR 0x00000400 +#define ATA_SE_HOST_ERR 0x00000800 +#define ATA_SE_PHY_CHANGED 0x00010000 +#define ATA_SE_PHY_IERROR 0x00020000 +#define ATA_SE_COMM_WAKE 0x00040000 +#define ATA_SE_DECODE_ERR 0x00080000 +#define ATA_SE_PARITY_ERR 0x00100000 +#define ATA_SE_CRC_ERR 0x00200000 +#define ATA_SE_HANDSHAKE_ERR 0x00400000 +#define ATA_SE_LINKSEQ_ERR 0x00800000 +#define ATA_SE_TRANSPORT_ERR 0x01000000 +#define ATA_SE_UNKNOWN_FIS 0x02000000
typedef struct _IDE_SATA_REGISTERS { union { @@ -842,6 +895,7 @@ PIDE_AHCI_CMD ahci_cmd_ptr; ULONG in_bcount; ULONG in_status; + ULONG in_serror; USHORT io_cmd_flags; // out UCHAR in_error; } ahci; @@ -1032,6 +1086,7 @@ ULONG AhciPrevCI; ULONG AhciCompleteCI; ULONG AhciLastIS; + ULONG AhciLastSError; //PVOID AHCI_FIS; // is not actually used by UniATA now, but is required by AHCI controller //ULONGLONG AHCI_FIS_PhAddr; // Note: in contrast to FBSD, we keep PRD and CMD item in AtaReq structure
Modified: trunk/reactos/drivers/storage/ide/uniata/id_ata.cpp URL: http://svn.reactos.org/svn/reactos/trunk/reactos/drivers/storage/ide/uniata/... ============================================================================== --- trunk/reactos/drivers/storage/ide/uniata/id_ata.cpp [iso-8859-1] (original) +++ trunk/reactos/drivers/storage/ide/uniata/id_ata.cpp [iso-8859-1] Thu Mar 13 18:54:06 2014 @@ -1,6 +1,6 @@ /*++
-Copyright (c) 2002-2012 Alexandr A. Telyatnikov (Alter) +Copyright (c) 2002-2014 Alexandr A. Telyatnikov (Alter)
Module Name: id_ata.cpp @@ -37,8 +37,8 @@ Some parts of code were taken from FreeBSD 4.3-6.1 ATA driver by Søren Schmidt, Copyright (c) 1998-2007
- All parts of code are greatly changed/updated by - Alter, Copyright (c) 2002-2007: + All parts of code are significantly changed/updated by + Alter, Copyright (c) 2002-2014:
1. Internal command queueing/reordering 2. Drive identification @@ -4182,23 +4182,41 @@ return INTERRUPT_REASON_IGNORE; } break; - case PRMIO: - status = AtapiReadPortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x0040); - if(ChipFlags & PRSATA) { - pr_status = AtapiReadPortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x006c); - AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x006c, pr_status & 0x000000ff); - } + case PRMIO: { + ULONG stat_reg = (ChipFlags & PRG2) ? 0x60 : 0x6c; + status = AtapiReadPortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x40); + AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x40, status); + + if(status & (1 << (Channel+1))) { + // our + } else { + KdPrint2((PRINT_PREFIX " Promise mio unexpected\n")); + return INTERRUPT_REASON_IGNORE; + } + + if(!(ChipFlags & UNIATA_SATA)) + break; + + pr_status = AtapiReadPortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),stat_reg); + AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),stat_reg, (pr_status & (0x11 << Channel))); if(pr_status & (0x11 << Channel)) { // TODO: reset channel KdPrint2((PRINT_PREFIX " Promise mio unexpected + reset req\n")); + UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_DETACH, 0); + } + if(!(status & (0x01 << Channel))) { + // Connect event + KdPrint2((PRINT_PREFIX " Promise mio unexpected attach\n")); + UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_ATTACH, 0); + } + if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) { + OurInterrupt = INTERRUPT_REASON_UNEXPECTED; + } else { return INTERRUPT_REASON_IGNORE; } - if(!(status & (0x01 << Channel))) { - KdPrint2((PRINT_PREFIX " Promise mio unexpected\n")); - return INTERRUPT_REASON_IGNORE; - } + AtapiWritePort4(chan, IDX_BM_DeviceSpecific0, 0x00000001); - break; + break; } } break; } case ATA_NVIDIA_ID: { @@ -4551,6 +4569,7 @@ // BOOLEAN RestoreUseDpc = FALSE; BOOLEAN DataOverrun = FALSE; BOOLEAN NoStartIo = TRUE; + BOOLEAN NoRetry = FALSE;
KdPrint2((PRINT_PREFIX "AtapiInterrupt:\n")); if(InDpc) { @@ -4763,12 +4782,19 @@ statusByte = (UCHAR)(AtaReq->ahci.in_status & IDE_STATUS_MASK);
if(chan->AhciLastIS & ~(ATA_AHCI_P_IX_DHR | ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DS | ATA_AHCI_P_IX_SDB)) { - KdPrint3((PRINT_PREFIX "Err intr (%#x)\n", chan->AhciLastIS & ~(ATA_AHCI_P_IX_DHR | ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DS | ATA_AHCI_P_IX_SDB))); + KdPrint3((PRINT_PREFIX "Err intr (%#x), SE (%#x)\n", + chan->AhciLastIS & ~(ATA_AHCI_P_IX_DHR | ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DS | ATA_AHCI_P_IX_SDB), + chan->AhciLastSError)); if(chan->AhciLastIS & ~ATA_AHCI_P_IX_OF) { //KdPrint3((PRINT_PREFIX "Err mask (%#x)\n", chan->AhciLastIS & ~ATA_AHCI_P_IX_OF)); // We have some other error except Overflow // Just signal ERROR, operation will be aborted in ERROR branch. statusByte |= IDE_STATUS_ERROR; + AtaReq->ahci.in_serror = chan->AhciLastSError; + if(chan->AhciLastSError & (ATA_SE_HANDSHAKE_ERR | ATA_SE_LINKSEQ_ERR | ATA_SE_TRANSPORT_ERR | ATA_SE_UNKNOWN_FIS)) { + KdPrint2((PRINT_PREFIX "Unrecoverable\n")); + NoRetry = TRUE; + } } else { // We have only Overflow. Abort operation and continue #ifdef _DEBUG @@ -4960,6 +4986,13 @@ UniataDumpAhciPortRegs(chan); #endif UniataAhciStatus(HwDeviceExtension, lChannel, DEVNUM_NOT_SPECIFIED); + if(NoRetry) { + AtaReq->retry += MAX_RETRIES; + if(!error && (statusByte & IDE_STATUS_ERROR)) { + KdPrint2((PRINT_PREFIX "AtapiInterrupt: force error status\n")); + error |= IDE_STATUS_ERROR; + } + } #ifdef _DEBUG UniataDumpAhciPortRegs(chan); #endif @@ -4980,7 +5013,9 @@ KdPrint2((PRINT_PREFIX " Bad Lba unknown\n")); }
- + if(deviceExtension->HwFlags & UNIATA_AHCI) { + KdPrint2((PRINT_PREFIX " no wait ready after error\n")); + } else if(!atapiDev) { KdPrint2((PRINT_PREFIX " wait 100 ready after IDE error\n")); AtapiStallExecution(100); @@ -5012,11 +5047,14 @@ #endif //IO_STATISTICS if(DmaTransfer /*&& (error & IDE_ERROR_ICRC)*/) { + KdPrint2((PRINT_PREFIX "Errors in DMA mode\n")); if(AtaReq->retry < MAX_RETRIES) { //fallback_pio: - AtaReq->Flags &= ~REQ_FLAG_DMA_OPERATION; - AtaReq->Flags |= REQ_FLAG_FORCE_DOWNRATE; + if(!(deviceExtension->HwFlags & UNIATA_AHCI)) { + AtaReq->Flags &= ~REQ_FLAG_DMA_OPERATION; + AtaReq->Flags |= REQ_FLAG_FORCE_DOWNRATE; // LunExt->DeviceFlags |= DFLAGS_FORCE_DOWNRATE; + } AtaReq->ReqState = REQ_STATE_QUEUED; goto reenqueue_req; } @@ -10671,8 +10709,8 @@ // KdPrint(( "AtapiCheckRegValue: RegistryPath %ws\n", RegistryPath->Buffer));
paramPath.Length = 0; - paramPath.MaximumLength = (USHORT)(RegistryPath->Length + - (wcslen(PathSuffix)+2)*sizeof(WCHAR)); + paramPath.MaximumLength = RegistryPath->Length + + (wcslen(PathSuffix)+2)*sizeof(WCHAR); paramPath.Buffer = (PWCHAR)ExAllocatePool(NonPagedPool, paramPath.MaximumLength); if(!paramPath.Buffer) { KdPrint(("AtapiCheckRegValue: couldn't allocate paramPath\n"));
Modified: trunk/reactos/drivers/storage/ide/uniata/id_dma.cpp URL: http://svn.reactos.org/svn/reactos/trunk/reactos/drivers/storage/ide/uniata/... ============================================================================== --- trunk/reactos/drivers/storage/ide/uniata/id_dma.cpp [iso-8859-1] (original) +++ trunk/reactos/drivers/storage/ide/uniata/id_dma.cpp [iso-8859-1] Thu Mar 13 18:54:06 2014 @@ -1,6 +1,6 @@ /*++
-Copyright (c) 2002-2012 Alexander A. Telyatnikov (Alter) +Copyright (c) 2002-2014 Alexander A. Telyatnikov (Alter)
Module Name: id_dma.cpp @@ -296,7 +296,7 @@ KdPrint2((PRINT_PREFIX " get Phys(PRD=%x)\n", &(AtaReq->dma_tab) )); dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)&(AtaReq->dma_tab) /*chan->dma_tab*/, &i, &dma_baseu); } - if(dma_baseu) { + if(dma_baseu && i) { KdPrint2((PRINT_PREFIX "AtapiDmaSetup: SRB built-in PRD above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base)); if(!deviceExtension->Host64) { dma_base = chan->DB_PRD_PhAddr; @@ -312,8 +312,8 @@
KdPrint2((PRINT_PREFIX " get Phys(data[0]=%x)\n", data )); dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, Srb, data, &dma_count, &dma_baseu); - if(dma_baseu) { - KdPrint2((PRINT_PREFIX "AtapiDmaSetup: 1st block of buffer above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base)); + if(dma_baseu && dma_count) { + KdPrint2((PRINT_PREFIX "AtapiDmaSetup: 1st block of buffer above 4Gb: %8.8x%8.8x cnt=%x\n", dma_baseu, dma_base, dma_count)); if(!deviceExtension->Host64) { retry_DB_IO: use_DB_IO = TRUE; @@ -378,8 +378,8 @@ } KdPrint2((PRINT_PREFIX " get Phys(data[n=%d]=%x)\n", i, data )); dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, Srb, data, &dma_count, &dma_baseu); - if(dma_baseu) { - KdPrint2((PRINT_PREFIX "AtapiDmaSetup: block of buffer above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base)); + if(dma_baseu && dma_count) { + KdPrint2((PRINT_PREFIX "AtapiDmaSetup: block of buffer above 4Gb: %8.8x%8.8x, cnt=%x\n", dma_baseu, dma_base, dma_count)); if(!deviceExtension->Host64) { if(use_DB_IO) { KdPrint2((PRINT_PREFIX "AtapiDmaSetup: *ERROR* special buffer above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
Modified: trunk/reactos/drivers/storage/ide/uniata/id_init.cpp URL: http://svn.reactos.org/svn/reactos/trunk/reactos/drivers/storage/ide/uniata/... ============================================================================== --- trunk/reactos/drivers/storage/ide/uniata/id_init.cpp [iso-8859-1] (original) +++ trunk/reactos/drivers/storage/ide/uniata/id_init.cpp [iso-8859-1] Thu Mar 13 18:54:06 2014 @@ -42,6 +42,12 @@ --*/
#include "stdafx.h" + +static BUSMASTER_CONTROLLER_INFORMATION const AtiSouthAdapters[] = { + PCI_DEV_HW_SPEC_BM( 4385, 1002, 0x00, ATA_MODE_NOT_SPEC, "ATI South", 0 ), + PCI_DEV_HW_SPEC_BM( ffff, ffff, 0xff, BMLIST_TERMINATOR, NULL , BMLIST_TERMINATOR ) + }; +
BOOLEAN NTAPI @@ -54,7 +60,7 @@ { PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension; //ULONG slotNumber = deviceExtension->slotNumber; - //ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber; + ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber; ULONG VendorID = deviceExtension->DevID & 0xffff; //ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff; //ULONG RevID = deviceExtension->RevID; @@ -97,16 +103,26 @@ if(ChipType != PRMIO) { break; } - deviceExtension->NumberChannels = 4; - KdPrint2((PRINT_PREFIX "Promise 4 chan\n")); + if(!(ChipFlags & UNIATA_SATA)) { + deviceExtension->NumberChannels = 4; + KdPrint2((PRINT_PREFIX "Promise up to 4 chan\n")); + } else + if(ChipFlags & PRCMBO) { + deviceExtension->NumberChannels = 3; + KdPrint2((PRINT_PREFIX "Promise 3 chan\n")); + } else { + deviceExtension->NumberChannels = 4; + KdPrint2((PRINT_PREFIX "Promise 4 chan\n")); + } break; case ATA_MARVELL_ID: KdPrint2((PRINT_PREFIX "Marvell\n")); + /* AHCI part has own DevID-based workaround */ switch(deviceExtension->DevID) { case 0x610111ab: /* 88SX6101 only have 1 PATA channel */ if(BMList[deviceExtension->DevIndex].channel) { - KdPrint2((PRINT_PREFIX "88SX6101 has no 2nd PATA chan\n")); + KdPrint2((PRINT_PREFIX "88SX6101/11 has no 2nd PATA chan\n")); return FALSE; } deviceExtension->NumberChannels = 1; @@ -118,8 +134,8 @@ KdPrint2((PRINT_PREFIX "ATI\n")); switch(deviceExtension->DevID) { case ATA_ATI_IXP600: - case ATA_ATI_IXP700: - /* IXP600 & IXP700 only have 1 PATA channel */ + KdPrint2((PRINT_PREFIX " IXP600\n")); + /* IXP600 only have 1 PATA channel */ if(BMList[deviceExtension->DevIndex].channel) { KdPrint2((PRINT_PREFIX "New ATI no 2nd PATA chan\n")); return FALSE; @@ -127,6 +143,52 @@ deviceExtension->NumberChannels = 1; KdPrint2((PRINT_PREFIX "New ATI PATA 1 chan\n")); break; + + case ATA_ATI_IXP700: { + UCHAR satacfg = 0; + PCI_SLOT_NUMBER slotData; + ULONG i, slotNumber; + + KdPrint2((PRINT_PREFIX " IXP700\n")); + /* + * When "combined mode" is enabled, an additional PATA channel is + * emulated with two SATA ports and appears on this device. + * This mode can only be detected via SMB controller. + */ + i = AtapiFindListedDev((BUSMASTER_CONTROLLER_INFORMATION*)&AtiSouthAdapters[0], -1, HwDeviceExtension, SystemIoBusNumber, PCISLOTNUM_NOT_SPECIFIED, &slotData); + if(i != BMLIST_TERMINATOR) { + slotNumber = slotData.u.AsULONG; + + GetPciConfig1(0xad, satacfg); + KdPrint(("SATA controller %s (%s%s channel)\n", + (satacfg & 0x01) == 0 ? "disabled" : "enabled", + (satacfg & 0x08) == 0 ? "" : "combined mode, ", + (satacfg & 0x10) == 0 ? "primary" : "secondary")); + /* + * If SATA controller is enabled but combined mode is disabled, + * we have only one PATA channel. Ignore a non-existent channel. + */ + if ((satacfg & 0x09) == 0x01) { + if(BMList[deviceExtension->DevIndex].channel) { + KdPrint2((PRINT_PREFIX "New ATI no 2nd PATA chan\n")); + return FALSE; + } + deviceExtension->NumberChannels = 1; + KdPrint2((PRINT_PREFIX "New ATI PATA 1 chan\n")); + break; + } else { + KdPrint2((PRINT_PREFIX "New ATI 2 chan\n")); + deviceExtension->NumberChannels = 2; + /* + if (BMList[deviceExtension->DevIndex].channel != ((satacfg & 0x10) >> 4)) { + ; + } + */ + + } + } + + break; } } /* FALLTHROUGH */ case ATA_SILICON_IMAGE_ID: @@ -241,6 +303,7 @@ ULONG BaseIoAddress2; ULONG BaseIoAddressBM; BOOLEAN MemIo = FALSE; + BOOLEAN IsPata = FALSE;
KdPrint2((PRINT_PREFIX "UniataChipDetect:\n" )); KdPrint2((PRINT_PREFIX "HwFlags: %#x\n", deviceExtension->HwFlags)); @@ -292,6 +355,9 @@ }
static BUSMASTER_CONTROLLER_INFORMATION const SiSAdapters[] = { + PCI_DEV_HW_SPEC_BM( 1183, 1039, 0x00, ATA_UDMA6, "SiS 1183" , SIS133NEW), + PCI_DEV_HW_SPEC_BM( 1182, 1039, 0x00, ATA_SA150, "SiS 1182" , SISSATA | UNIATA_SATA), + PCI_DEV_HW_SPEC_BM( 0183, 1039, 0x00, ATA_SA150, "SiS 183" , SISSATA | UNIATA_SATA), PCI_DEV_HW_SPEC_BM( 0182, 1039, 0x00, ATA_SA150, "SiS 182" , SISSATA | UNIATA_SATA), PCI_DEV_HW_SPEC_BM( 0181, 1039, 0x00, ATA_SA150, "SiS 181" , SISSATA | UNIATA_SATA), PCI_DEV_HW_SPEC_BM( 0180, 1039, 0x00, ATA_SA150, "SiS 180" , SISSATA | UNIATA_SATA), @@ -371,6 +437,10 @@ switch(VendorID) {
case ATA_SIS_ID: + /* + We shall get here for all SIS controllers, even unlisted. + Then perform bus scan to find SIS bridge and decide what to do with controller + */ KdPrint2((PRINT_PREFIX "ATA_SIS_ID\n")); DevTypeInfo = (BUSMASTER_CONTROLLER_INFORMATION*)&SiSAdapters[0]; i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber, PCISLOTNUM_NOT_SPECIFIED, NULL); @@ -505,6 +575,7 @@ if(deviceExtension->MaxTransferMode >= ATA_SA150) { deviceExtension->HwFlags |= UNIATA_SATA; } + /* ConfigInfo->MaximumTransferLength = DEV_BSIZE*256; deviceExtension->MaximumDmaTransferLength = ConfigInfo->MaximumTransferLength; @@ -512,6 +583,25 @@ ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK; ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
+ /* for even more ugly AHCI-capable chips */ + if(ChipFlags & UNIATA_AHCI) { + /* + Seems, some chips may have inoperable/alternative BAR5 in SATA mode + This can be detected via PCI SubClass + */ + switch(VendorID) { + case ATA_NVIDIA_ID: + case ATA_ATI_ID: + KdPrint2((PRINT_PREFIX "ATA_xxx_ID check AHCI subclass\n")); + if((pciData)->SubClass == PCI_DEV_SUBCLASS_IDE) { + KdPrint2((PRINT_PREFIX "Non-AHCI mode\n")); + ChipFlags &= ~UNIATA_AHCI; + deviceExtension->HwFlags &= ~UNIATA_AHCI; + } + break; + } + } + if(ChipFlags & UNIATA_AHCI) { deviceExtension->NumberChannels = 0; if(!UniataAhciDetect(HwDeviceExtension, pciData, ConfigInfo)) { @@ -525,9 +615,6 @@ // UniataAhciDetect() sets proper number of channels if(!UniataAllocateLunExt(deviceExtension, UNIATA_ALLOCATE_NEW_LUNS)) { return STATUS_UNSUCCESSFUL; - } - - if(ChipFlags & UNIATA_AHCI) { }
switch(VendorID) { @@ -571,6 +658,9 @@ BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, 5, 0, ((ChipFlags & NV4OFF) ? 0x400 : 0) + 0x40*2); KdPrint2((PRINT_PREFIX "BaseMemAddress %x\n", BaseMemAddress)); + if(!BaseMemAddress) { + return STATUS_UNSUCCESSFUL; + } if((*ConfigInfo->AccessRanges)[5].RangeInMemory) { KdPrint2((PRINT_PREFIX "MemIo\n")); MemIo = TRUE; @@ -600,26 +690,57 @@ break; } deviceExtension->AltRegMap = TRUE; // inform generic resource allocator + + /* BAR4 -> res1 */ BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, 4, 0, 0x4000); - KdPrint2((PRINT_PREFIX "BaseMemAddress %x\n", BaseMemAddress)); + KdPrint2((PRINT_PREFIX "BaseMemAddress[4] %x\n", BaseMemAddress)); + if(!BaseMemAddress) { + return STATUS_UNSUCCESSFUL; + } if((*ConfigInfo->AccessRanges)[4].RangeInMemory) { KdPrint2((PRINT_PREFIX "MemIo\n")); MemIo = TRUE; } + deviceExtension->BaseIoAddressSATA_0.Addr = BaseMemAddress; + deviceExtension->BaseIoAddressSATA_0.MemIo = MemIo; + + /* BAR3 -> res2 */ + BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, + 3, 0, 0xd0000); + KdPrint2((PRINT_PREFIX "BaseMemAddress[3] %x\n", BaseMemAddress)); + if(!BaseMemAddress) { + return STATUS_UNSUCCESSFUL; + } + if((*ConfigInfo->AccessRanges)[3].RangeInMemory) { + KdPrint2((PRINT_PREFIX "MemIo\n")); + MemIo = TRUE; + } deviceExtension->BaseIoAddressBM_0.Addr = BaseMemAddress; deviceExtension->BaseIoAddressBM_0.MemIo = MemIo; + + if(!(ChipFlags & UNIATA_SATA)) { + UCHAR reg48; + + reg48 = AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48); + deviceExtension->NumberChannels = ((reg48 & 0x01) ? 1 : 0) + + ((reg48 & 0x02) ? 1 : 0) + + 2; + KdPrint2((PRINT_PREFIX "Channels -> %d\n", deviceExtension->NumberChannels)); + } + for(c=0; c<deviceExtension->NumberChannels; c++) {
- ULONG offs12, offs7; + /* res2-based */ + ULONG offs8, offs7;
chan = &deviceExtension->chan[c];
- offs12 = c << 12; - offs7 = c << 7; + offs8 = c << 8; + offs7 = c << 7;
for (i=0; i<=IDX_IO1_SZ; i++) { - chan->RegTranslation[IDX_IO1+i].Addr = BaseMemAddress + 0x200 + (i << 2) + offs12; + chan->RegTranslation[IDX_IO1+i].Addr = BaseMemAddress + 0x200 + (i << 2) + offs7; chan->RegTranslation[IDX_IO1+i].MemIo = MemIo; } chan->RegTranslation[IDX_IO2_AltStatus].Addr = BaseMemAddress + 0x238 + offs7; @@ -633,11 +754,37 @@ chan->RegTranslation[IDX_BM_PRD_Table].MemIo = MemIo; chan->RegTranslation[IDX_BM_DeviceSpecific0].Addr = BaseMemAddress + (c << 2); chan->RegTranslation[IDX_BM_DeviceSpecific0].MemIo = MemIo; + + if((ChipFlags & PRSATA) || + ((ChipFlags & PRCMBO) && c<2)) { + KdPrint2((PRINT_PREFIX "Promise SATA\n")); + + chan->RegTranslation[IDX_SATA_SStatus].Addr = BaseMemAddress + 0x400 + offs7; + chan->RegTranslation[IDX_SATA_SStatus].MemIo = MemIo; + chan->RegTranslation[IDX_SATA_SError].Addr = BaseMemAddress + 0x404 + offs7; + chan->RegTranslation[IDX_SATA_SError].MemIo = MemIo; + chan->RegTranslation[IDX_SATA_SControl].Addr = BaseMemAddress + 0x408 + offs7; + chan->RegTranslation[IDX_SATA_SControl].MemIo = MemIo; + + chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE; + } else { + KdPrint2((PRINT_PREFIX "Promise PATA\n")); + chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA6); + } } break;
case ATA_ATI_ID: KdPrint2((PRINT_PREFIX "ATI\n")); + if(ChipType == ATI700) { + KdPrint2((PRINT_PREFIX "ATI700\n")); + if(!(ChipFlags & UNIATA_AHCI)) { + KdPrint2((PRINT_PREFIX "IXP700 PATA\n")); + chan = &deviceExtension->chan[0]; + chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5); + } + break; + } /* FALLTHROUGH */ case ATA_SILICON_IMAGE_ID: {
@@ -661,6 +808,9 @@ BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, 5, 0, 0x800); KdPrint2((PRINT_PREFIX "BaseMemAddress %x\n", BaseMemAddress)); + if(!BaseMemAddress) { + return STATUS_UNSUCCESSFUL; + } if((*ConfigInfo->AccessRanges)[5].RangeInMemory) { KdPrint2((PRINT_PREFIX "MemIo\n")); MemIo = TRUE; @@ -697,6 +847,10 @@ chan->RegTranslation[IDX_BM_DeviceSpecific1].MemIo = MemIo; }
+ if(chan->MaxTransferMode < ATA_SA150) { + // do nothing for PATA part + KdPrint2((PRINT_PREFIX "No SATA regs for PATA part\n")); + } else if(ChipFlags & UNIATA_SATA) { chan->RegTranslation[IDX_SATA_SStatus].Addr = BaseMemAddress + 0x104 + (unit01 << 7) + (unit10 << 8); chan->RegTranslation[IDX_SATA_SStatus].MemIo = MemIo; @@ -725,6 +879,9 @@ BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, 5, 0, 0x400); KdPrint2((PRINT_PREFIX "BaseMemAddress %x\n", BaseMemAddress)); + if(!BaseMemAddress) { + return STATUS_UNSUCCESSFUL; + } if((*ConfigInfo->AccessRanges)[5].RangeInMemory) { KdPrint2((PRINT_PREFIX "MemIo\n")); MemIo = TRUE; @@ -802,7 +959,8 @@ //deviceExtension->MaxTransferMode = SiSSouthAdapters[i].MaxTransferMode; if(SiSSouthAdapters[i].RaidFlags & UNIATA_SATA) { deviceExtension->HwFlags |= UNIATA_SATA; - if(SiSSouthAdapters[i].nDeviceId == 0x1182) { + if(SiSSouthAdapters[i].nDeviceId == 0x1182 || + SiSSouthAdapters[i].nDeviceId == 0x1183) { SIS_182 = TRUE; } } @@ -827,25 +985,27 @@ BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, 5, 0, 0x400); KdPrint2((PRINT_PREFIX "BaseMemAddress %x\n", BaseMemAddress)); - if((*ConfigInfo->AccessRanges)[5].RangeInMemory) { - KdPrint2((PRINT_PREFIX "MemIo\n")); - MemIo = TRUE; - } - deviceExtension->BaseIoAddressSATA_0.Addr = BaseMemAddress; - deviceExtension->BaseIoAddressSATA_0.MemIo = MemIo; - - for(c=0; c<deviceExtension->NumberChannels; c++) { - ULONG offs = c << (SIS_182 ? 5 : 6); - - chan = &deviceExtension->chan[c]; - chan->RegTranslation[IDX_SATA_SStatus].Addr = BaseMemAddress + 0 + offs; - chan->RegTranslation[IDX_SATA_SStatus].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SError].Addr = BaseMemAddress + 4 + offs; - chan->RegTranslation[IDX_SATA_SError].MemIo = MemIo; - chan->RegTranslation[IDX_SATA_SControl].Addr = BaseMemAddress + 8 + offs; - chan->RegTranslation[IDX_SATA_SControl].MemIo = MemIo; - - chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE; + if(BaseMemAddress) { + if((*ConfigInfo->AccessRanges)[5].RangeInMemory) { + KdPrint2((PRINT_PREFIX "MemIo\n")); + MemIo = TRUE; + } + deviceExtension->BaseIoAddressSATA_0.Addr = BaseMemAddress; + deviceExtension->BaseIoAddressSATA_0.MemIo = MemIo; + + for(c=0; c<deviceExtension->NumberChannels; c++) { + ULONG offs = c << (SIS_182 ? 5 : 6); + + chan = &deviceExtension->chan[c]; + chan->RegTranslation[IDX_SATA_SStatus].Addr = BaseMemAddress + 0 + offs; + chan->RegTranslation[IDX_SATA_SStatus].MemIo = MemIo; + chan->RegTranslation[IDX_SATA_SError].Addr = BaseMemAddress + 4 + offs; + chan->RegTranslation[IDX_SATA_SError].MemIo = MemIo; + chan->RegTranslation[IDX_SATA_SControl].Addr = BaseMemAddress + 8 + offs; + chan->RegTranslation[IDX_SATA_SControl].MemIo = MemIo; + + chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE; + } } } } @@ -941,7 +1101,6 @@ break; } case ATA_INTEL_ID: {
- BOOLEAN IsPata; if(!(ChipFlags & UNIATA_SATA)) { break; } @@ -953,6 +1112,9 @@ KdPrint2((PRINT_PREFIX "UniataChipDetect: Intel 31244, DPA mode\n")); BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, 0, 0, 0x0c00); + if(!BaseMemAddress) { + return STATUS_UNSUCCESSFUL; + } if((*ConfigInfo->AccessRanges)[0].RangeInMemory) { KdPrint2((PRINT_PREFIX "MemIo\n")); MemIo = TRUE; @@ -1527,7 +1689,7 @@ memcpy(LunExt->IdentifyData.FirmwareRevision, ".10", 4); if(!LunExt->IdentifyData.SectorsPerTrack || !LunExt->IdentifyData.NumberOfCylinders || - !LunExt->IdentifyData.SectorsPerTrack) { + !LunExt->IdentifyData.NumberOfHeads) { // ERROR KdPrint2((PRINT_PREFIX "Wrong CHS\n")); LunExt->opt_GeomType = GEOM_AUTO; @@ -2037,8 +2199,13 @@ break; case PRMIO: if(c == CHAN_NOT_SPECIFIED) { - if(ChipFlags & PRSATA) { - AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x6c, 0x000000ff); + /* clear SATA status and unmask interrupts */ + AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), + (ChipFlags & PRG2) ? 0x60 : 0x6c, 0x000000ff); + if(ChipFlags & UNIATA_SATA) { + /* enable "long burst length" on gen2 chips */ + AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), 0x44, + AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), 0x44) | 0x2000); } } else { chan = &deviceExtension->chan[c]; @@ -2072,6 +2239,7 @@ KdPrint2((PRINT_PREFIX "ATI\n")); break; } + /* FALLTHROUGH */ case ATA_SILICON_IMAGE_ID: /* if(ChipFlags & SIIENINTR) { SetPciConfig1(0x71, 0x01); @@ -2190,7 +2358,15 @@ }
break; } - } + case ATI700: + KdPrint2((PRINT_PREFIX "ATI700\n")); + if(c == 0 && !(ChipFlags & UNIATA_AHCI)) { + KdPrint2((PRINT_PREFIX "IXP700 PATA\n")); + chan = &deviceExtension->chan[c]; + chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5); + } + break; + } /* switch(ChipType) */ break; case ATA_SIS_ID: if(c == CHAN_NOT_SPECIFIED) { @@ -2211,6 +2387,7 @@ break; case SISSATA: ChangePciConfig2(0x04, (a & ~0x0400)); + break; } } if(ChipType == SIS133NEW) {
Modified: trunk/reactos/drivers/storage/ide/uniata/id_sata.cpp URL: http://svn.reactos.org/svn/reactos/trunk/reactos/drivers/storage/ide/uniata/... ============================================================================== --- trunk/reactos/drivers/storage/ide/uniata/id_sata.cpp [iso-8859-1] (original) +++ trunk/reactos/drivers/storage/ide/uniata/id_sata.cpp [iso-8859-1] Thu Mar 13 18:54:06 2014 @@ -1,6 +1,6 @@ /*++
-Copyright (c) 2008-2012 Alexandr A. Telyatnikov (Alter) +Copyright (c) 2008-2014 Alexandr A. Telyatnikov (Alter)
Module Name: id_probe.cpp @@ -649,6 +649,8 @@ ULONG PI; #endif //DBG ULONG CAP; + ULONG CAP2; + ULONG BOHC; ULONG GHC; BOOLEAN MemIo = FALSE;
@@ -657,6 +659,37 @@ #ifdef DBG UniataDumpAhciRegs(deviceExtension); #endif //DBG + + CAP2 = UniataAhciReadHostPort4(deviceExtension, IDX_AHCI_CAP2); + if(CAP2 & AHCI_CAP2_BOH) { + BOHC = UniataAhciReadHostPort4(deviceExtension, IDX_AHCI_BOHC); + KdPrint2((PRINT_PREFIX " stage 1 BOHC %#x\n", BOHC)); + UniataAhciWriteHostPort4(deviceExtension, IDX_AHCI_BOHC, + BOHC | AHCI_BOHC_OOS); + for(i=0; i<50; i++) { + AtapiStallExecution(500); + BOHC = UniataAhciReadHostPort4(deviceExtension, IDX_AHCI_BOHC); + KdPrint2((PRINT_PREFIX " BOHC %#x\n", BOHC)); + if(BOHC & AHCI_BOHC_BB) { + break; + } + if(!(BOHC & AHCI_BOHC_BOS)) { + break; + } + } + KdPrint2((PRINT_PREFIX " stage 2 BOHC %#x\n", BOHC)); + if(BOHC & AHCI_BOHC_BB) { + for(i=0; i<2000; i++) { + AtapiStallExecution(1000); + BOHC = UniataAhciReadHostPort4(deviceExtension, IDX_AHCI_BOHC); + KdPrint2((PRINT_PREFIX " BOHC %#x\n", BOHC)); + if(!(BOHC & AHCI_BOHC_BOS)) { + break; + } + } + } + KdPrint2((PRINT_PREFIX " final BOHC %#x\n", BOHC)); + }
/* disable AHCI interrupts, for MSI compatibility issue see http://www.intel.com/Assets/PDF/specupdate/307014.pdf @@ -729,7 +762,14 @@ PI = UniataAhciReadHostPort4(deviceExtension, IDX_AHCI_PI); KdPrint2((PRINT_PREFIX " AHCI PI %#x\n", PI)); #endif //DBG - + CAP2 = UniataAhciReadHostPort4(deviceExtension, IDX_AHCI_CAP2); + if(CAP2 & AHCI_CAP2_BOH) { + KdPrint2((PRINT_PREFIX " retry BOHC\n")); + BOHC = UniataAhciReadHostPort4(deviceExtension, IDX_AHCI_BOHC); + KdPrint2((PRINT_PREFIX " BOHC %#x\n", BOHC)); + UniataAhciWriteHostPort4(deviceExtension, IDX_AHCI_BOHC, + BOHC | AHCI_BOHC_OOS); + } /* clear interrupts */ UniataAhciWriteHostPort4(deviceExtension, IDX_AHCI_IS, UniataAhciReadHostPort4(deviceExtension, IDX_AHCI_IS)); @@ -1061,6 +1101,7 @@ } chan->AhciCompleteCI = (chan->AhciPrevCI ^ CI) & chan->AhciPrevCI; // only 1->0 states chan->AhciPrevCI = CI; + chan->AhciLastSError = SError.Reg; KdPrint((" AHCI: complete mask %#x\n", chan->AhciCompleteCI)); chan->AhciLastIS = IS.Reg; if(CI & (1 << tag)) {
Modified: trunk/reactos/drivers/storage/ide/uniata/uniata_ver.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/drivers/storage/ide/uniata/... ============================================================================== --- trunk/reactos/drivers/storage/ide/uniata/uniata_ver.h [iso-8859-1] (original) +++ trunk/reactos/drivers/storage/ide/uniata/uniata_ver.h [iso-8859-1] Thu Mar 13 18:54:06 2014 @@ -1,10 +1,10 @@ -#define UNIATA_VER_STR "44b1" -#define UNIATA_VER_DOT 0.44.2.1 +#define UNIATA_VER_STR "45a3" +#define UNIATA_VER_DOT 0.45.1.3 #define UNIATA_VER_MJ 0 -#define UNIATA_VER_MN 44 -#define UNIATA_VER_SUB_MJ 2 -#define UNIATA_VER_SUB_MN 1 -#define UNIATA_VER_DOT_COMMA 0,44,2,1 -#define UNIATA_VER_DOT_STR "0.44.2.1" -#define UNIATA_VER_YEAR 2013 -#define UNIATA_VER_YEAR_STR "2013" +#define UNIATA_VER_MN 45 +#define UNIATA_VER_SUB_MJ 1 +#define UNIATA_VER_SUB_MN 3 +#define UNIATA_VER_DOT_COMMA 0,45,1,3 +#define UNIATA_VER_DOT_STR "0.45.1.3" +#define UNIATA_VER_YEAR 2014 +#define UNIATA_VER_YEAR_STR "2014"
-
cwittich＠svn.reactos.org