Ros-diffs February 2010

ros-diffs@reactos.org

22 participants
365 discussions

[sir_richard] 45521: [FREELDR]: Do not build Disk/Partition support for ARM, we use ram disks.

by sir_richard＠svn.reactos.org

Author: sir_richard Date: Tue Feb 9 03:33:31 2010 New Revision: 45521 URL: http://svn.reactos.org/svn/reactos?rev=45521&view=rev Log: [FREELDR]: Do not build Disk/Partition support for ARM, we use ram disks. Modified: trunk/reactos/boot/freeldr/freeldr/disk/disk.c trunk/reactos/boot/freeldr/freeldr/disk/partition.c Modified: trunk/reactos/boot/freeldr/freeldr/disk/disk.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/disk/… ===========================… [View More]

15 years, 4 months

[sir_richard] 45520: [FREELDR]: Do not build EXT2, ISO or NTFS support for ARM targets.

by sir_richard＠svn.reactos.org

Author: sir_richard Date: Tue Feb 9 03:32:59 2010 New Revision: 45520 URL: http://svn.reactos.org/svn/reactos?rev=45520&view=rev Log: [FREELDR]: Do not build EXT2, ISO or NTFS support for ARM targets. Modified: trunk/reactos/boot/freeldr/freeldr/fs/ext2.c trunk/reactos/boot/freeldr/freeldr/fs/fs.c trunk/reactos/boot/freeldr/freeldr/fs/iso.c trunk/reactos/boot/freeldr/freeldr/fs/ntfs.c Modified: trunk/reactos/boot/freeldr/freeldr/fs/ext2.c URL: http://svn.reactos.org/svn/… [View More]reactos/trunk/reactos/boot/freeldr/freeldr/fs/ex… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/fs/ext2.c [iso-8859-1] (original) +++ trunk/reactos/boot/freeldr/freeldr/fs/ext2.c [iso-8859-1] Tue Feb 9 03:32:59 2010 @@ -17,6 +17,7 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ +#ifndef _M_ARM #include <freeldr.h> #include <debug.h> @@ -1308,3 +1309,6 @@ else return NULL; } + +#endif + Modified: trunk/reactos/boot/freeldr/freeldr/fs/fs.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/fs/fs… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/fs/fs.c [iso-8859-1] (original) +++ trunk/reactos/boot/freeldr/freeldr/fs/fs.c [iso-8859-1] Tue Feb 9 03:32:59 2010 @@ -321,13 +321,17 @@ } /* Try to detect the file system */ +#ifndef _M_ARM FileData[DeviceId].FileFuncTable = IsoMount(DeviceId); if (!FileData[DeviceId].FileFuncTable) +#endif FileData[DeviceId].FileFuncTable = FatMount(DeviceId); +#ifndef _M_ARM if (!FileData[DeviceId].FileFuncTable) FileData[DeviceId].FileFuncTable = NtfsMount(DeviceId); if (!FileData[DeviceId].FileFuncTable) FileData[DeviceId].FileFuncTable = Ext2Mount(DeviceId); +#endif if (!FileData[DeviceId].FileFuncTable) { /* Error, unable to detect file system */ Modified: trunk/reactos/boot/freeldr/freeldr/fs/iso.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/fs/is… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/fs/iso.c [iso-8859-1] (original) +++ trunk/reactos/boot/freeldr/freeldr/fs/iso.c [iso-8859-1] Tue Feb 9 03:32:59 2010 @@ -18,6 +18,7 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ +#ifndef _M_ARM #include <freeldr.h> #include <debug.h> @@ -510,3 +511,6 @@ else return NULL; } + +#endif + Modified: trunk/reactos/boot/freeldr/freeldr/fs/ntfs.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/fs/nt… ============================================================================== --- trunk/reactos/boot/freeldr/freeldr/fs/ntfs.c [iso-8859-1] (original) +++ trunk/reactos/boot/freeldr/freeldr/fs/ntfs.c [iso-8859-1] Tue Feb 9 03:32:59 2010 @@ -23,6 +23,7 @@ * - May crash on corrupted filesystem. */ +#ifndef _M_ARM #include <freeldr.h> #include <debug.h> @@ -957,3 +958,5 @@ // return &NtfsFuncTable; } + +#endif [View Less]

15 years, 4 months

[sir_richard] 45519: [FREELDR]: The WinLDR code forgot to update the File Path of boot driver entries from PA to VA as well, not just the registry path. It also tried to touch the PA LoaderBlock right after enabling the MMU. It should touch the VA LoaderBlock instead, since there is no guarantee that the address has been identity mapped (and hence the PA address interpreted as a VA address by the MMU is bogus).

by sir_richard＠svn.reactos.org

Author: sir_richard Date: Tue Feb 9 03:26:46 2010 New Revision: 45519 URL: http://svn.reactos.org/svn/reactos?rev=45519&view=rev Log: [FREELDR]: The WinLDR code forgot to update the File Path of boot driver entries from PA to VA as well, not just the registry path. It also tried to touch the PA LoaderBlock right after enabling the MMU. It should touch the VA LoaderBlock instead, since there is no guarantee that the address has been identity mapped (and hence the PA address interpreted as … [View More]

15 years, 4 months

[evb] 45518: - New ARM HAL after 2 nights in the company of a madman. - Many fixes, more implemented routines, support for ARMv7. - Some Linux code, marked as GPL, from ARM Ltd in cache.s. All OS use this code.

by evb＠svn.reactos.org

Author: evb Date: Tue Feb 9 03:26:28 2010 New Revision: 45518 URL: http://svn.reactos.org/svn/reactos?rev=45518&view=rev Log: - New ARM HAL after 2 nights in the company of a madman. - Many fixes, more implemented routines, support for ARMv7. - Some Linux code, marked as GPL, from ARM Ltd in cache.s. All OS use this code. Added: trunk/reactos/hal/halarm/generic/beep.c (with props) trunk/reactos/hal/halarm/generic/bus.c (with props) trunk/reactos/hal/halarm/generic/cache.S … [View More]

15 years, 4 months

[sir_richard] 45517: [FREELDR]: The hack to set pages from 0x100 to 0x1FF as busy so that the heap allocator wouldn't use them always restored the pages back to Free (since they usually were free on x86). However, if the pages were already being used in the first place, this made them appear free and corrupted existing memory. Fixed the hack so that it restores the previous state of the memory pages.

by sir_richard＠svn.reactos.org

Author: sir_richard Date: Tue Feb 9 03:22:08 2010 New Revision: 45517 URL: http://svn.reactos.org/svn/reactos?rev=45517&view=rev Log: [FREELDR]: The hack to set pages from 0x100 to 0x1FF as busy so that the heap allocator wouldn't use them always restored the pages back to Free (since they usually were free on x86). However, if the pages were already being used in the first place, this made them appear free and corrupted existing memory. Fixed the hack so that it restores the previous … [View More]

15 years, 4 months

[sir_richard] 45516: [NDK]: Use new ARMv6 PTE structures.

by sir_richard＠svn.reactos.org

Author: sir_richard Date: Tue Feb 9 03:14:58 2010 New Revision: 45516 URL: http://svn.reactos.org/svn/reactos?rev=45516&view=rev Log: [NDK]: Use new ARMv6 PTE structures. Modified: trunk/reactos/include/ndk/arm/mmtypes.h Modified: trunk/reactos/include/ndk/arm/mmtypes.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/include/ndk/arm/mmtypes.h?… ============================================================================== --- trunk/reactos/include/ndk/arm/mmtypes.h [iso-8859-… [View More]1] (original) +++ trunk/reactos/include/ndk/arm/mmtypes.h [iso-8859-1] Tue Feb 9 03:14:58 2010 @@ -47,90 +47,56 @@ // // Page Table Entry Definitions // -typedef struct _HARDWARE_PTE_ARM +typedef struct _HARDWARE_PDE_ARMV6 { - union - { - union - { - struct - { - ULONG Type:2; - ULONG Unused:30; - } Fault; - struct - { - ULONG Type:2; - ULONG Ignored:2; - ULONG Reserved:1; - ULONG Domain:4; - ULONG Ignored1:1; - ULONG BaseAddress:22; - } Coarse; - struct - { - ULONG Type:2; - ULONG Buffered:1; - ULONG Cached:1; - ULONG Reserved:1; - ULONG Domain:4; - ULONG Ignored:1; - ULONG Access:2; - ULONG Ignored1:8; - ULONG BaseAddress:12; - } Section; - struct - { - ULONG Type:2; - ULONG Reserved:3; - ULONG Domain:4; - ULONG Ignored:3; - ULONG BaseAddress:20; - } Fine; - } L1; - union - { - struct - { - ULONG Type:2; - ULONG Unused:30; - } Fault; - struct - { - ULONG Type:2; - ULONG Buffered:1; - ULONG Cached:1; - ULONG Access0:2; - ULONG Access1:2; - ULONG Access2:2; - ULONG Access3:2; - ULONG Ignored:4; - ULONG BaseAddress:16; - } Large; - struct - { - ULONG Type:2; - ULONG Buffered:1; - ULONG Cached:1; - ULONG Access0:2; - ULONG Access1:2; - ULONG Access2:2; - ULONG Access3:2; - ULONG BaseAddress:20; - } Small; - struct - { - ULONG Type:2; - ULONG Buffered:1; - ULONG Cached:1; - ULONG Access0:2; - ULONG Ignored:4; - ULONG BaseAddress:22; - } Tiny; - } L2; - ULONG AsUlong; - }; -} HARDWARE_PTE_ARM, *PHARDWARE_PTE_ARM; + ULONG Valid:1; // Only for small pages + ULONG LargePage:1; // Note, if large then Valid = 0 + ULONG Buffered:1; + ULONG Cached:1; + ULONG NoExecute:1; + ULONG Domain:4; + ULONG Ecc:1; + ULONG PageFrameNumber:22; +} HARDWARE_PDE_ARMV6, *PHARDWARE_PDE_ARMV6; + +typedef struct _HARDWARE_LARGE_PTE_ARMV6 +{ + ULONG Valid:1; // Only for small pages + ULONG LargePage:1; // Note, if large then Valid = 0 + ULONG Buffered:1; + ULONG Cached:1; + ULONG NoExecute:1; + ULONG Domain:4; + ULONG Ecc:1; + ULONG Accessed:1; + ULONG Owner:1; + ULONG CacheAttributes:3; + ULONG ReadOnly:1; + ULONG Shared:1; + ULONG NonGlobal:1; + ULONG SuperLagePage:1; + ULONG Reserved:1; + ULONG PageFrameNumber:12; +} HARDWARE_LARGE_PTE_ARMV6, *PHARDWARE_LARGE_PTE_ARMV6; + +typedef struct _HARDWARE_PTE_ARMV6 +{ + ULONG NoExecute:1; + ULONG Valid:1; + ULONG Buffered:1; + ULONG Cached:1; + ULONG Accessed:1; + ULONG Owner:1; + ULONG CacheAttributes:3; + ULONG ReadOnly:1; + ULONG Shared:1; + ULONG NonGlobal:1; + ULONG PageFrameNumber:20; +} HARDWARE_PTE_ARMV6, *PHARDWARE_PTE_ARMV6; + +C_ASSERT(sizeof(HARDWARE_PDE_ARMV6) == sizeof(ULONG)); +C_ASSERT(sizeof(HARDWARE_LARGE_PTE_ARMV6) == sizeof(ULONG)); +C_ASSERT(sizeof(HARDWARE_PTE_ARMV6) == sizeof(ULONG)); typedef struct _MMPTE_SOFTWARE { @@ -185,53 +151,18 @@ ULONG filler1:1; } MMPTE_LIST; -typedef struct _MMPDE_HARDWARE // FIXFIX: Find a way to make this more portable -{ - union - { - union - { - struct - { - ULONG Valid:1; - ULONG Section:1; - ULONG Sbz:3; - ULONG Domain:4; - ULONG EccEnabled:1; - ULONG PageFrameNumber:22; - } Coarse; - struct - { - ULONG Coarse:1; - ULONG Valid:1; - ULONG Buffered:1; - ULONG Cached:1; - ULONG Reserved:1; - ULONG Domain:4; - ULONG EccEnabled:1; - ULONG Access:2; - ULONG ExtendedAccess:3; - ULONG Sbz:3; - ULONG SuperSection:1; - ULONG Sbz1:1; - ULONG PageFrameNumber:12; - } Section; - ULONG AsUlong; - } Hard; - } u; -} MMPDE_HARDWARE, *PMMPDE_HARDWARE; - typedef union _MMPTE_HARDWARE { struct { - ULONG ExecuteNever:1; + ULONG NoExecute:1; ULONG Valid:1; ULONG Buffered:1; ULONG Cached:1; - ULONG Access:2; - ULONG TypeExtension:3; - ULONG ExtendedAccess:1; + ULONG Access:1; + ULONG Owner:1; + ULONG CacheAttributes:3; + ULONG ReadOnly:1; ULONG Shared:1; ULONG NonGlobal:1; ULONG PageFrameNumber:20; @@ -242,7 +173,7 @@ // // Use the right PTE structure // -#define HARDWARE_PTE HARDWARE_PTE_ARM -#define PHARDWARE_PTE PHARDWARE_PTE_ARM +#define HARDWARE_PTE HARDWARE_PTE_ARMV6 +#define PHARDWARE_PTE PHARDWARE_PTE_ARMV6 #endif [View Less]

15 years, 4 months

[sir_richard] 45515: [NTOS]: Tabula rasa (clean slate) on the old-MM page routines for ARM. Get rid of all of them for now. [NTOS]: Implement MmInitGlobalKernelPageDirectory as the first ARM page function in the new file. That's it for the kernel.

by sir_richard＠svn.reactos.org

Author: sir_richard Date: Tue Feb 9 03:14:20 2010 New Revision: 45515 URL: http://svn.reactos.org/svn/reactos?rev=45515&view=rev Log: [NTOS]: Tabula rasa (clean slate) on the old-MM page routines for ARM. Get rid of all of them for now. [NTOS]: Implement MmInitGlobalKernelPageDirectory as the first ARM page function in the new file. That's it for the kernel. Added: trunk/reactos/ntoskrnl/mm/arm/page.c (with props) Modified: trunk/reactos/ntoskrnl/ntoskrnl-generic.rbuild Added: … [View More]trunk/reactos/ntoskrnl/mm/arm/page.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/mm/arm/page.c?rev… ============================================================================== --- trunk/reactos/ntoskrnl/mm/arm/page.c (added) +++ trunk/reactos/ntoskrnl/mm/arm/page.c [iso-8859-1] Tue Feb 9 03:14:20 2010 @@ -1,0 +1,285 @@ +/* + * PROJECT: ReactOS Kernel + * LICENSE: BSD - See COPYING.ARM in the top level directory + * FILE: ntoskrnl/mm/arm/page.c + * PURPOSE: Old-school Page Management + * PROGRAMMERS: ReactOS Portable Systems Group + */ + +/* INCLUDES *******************************************************************/ + +#include <ntoskrnl.h> +#define NDEBUG +#include <debug.h> + +/* GLOBALS ********************************************************************/ + +ULONG MmGlobalKernelPageDirectory[4096]; +//MMPTE MiArmTemplatePte, MiArmTemplatePde; + +/* PRIVATE FUNCTIONS **********************************************************/ + +VOID +NTAPI +MiFlushTlb(IN PMMPTE PointerPte, + IN PVOID Address) +{ + UNIMPLEMENTED; + while (TRUE); +} + +BOOLEAN +NTAPI +MmCreateProcessAddressSpace(IN ULONG MinWs, + IN PEPROCESS Process, + IN PULONG DirectoryTableBase) +{ + UNIMPLEMENTED; + while (TRUE); + return FALSE; +} + +VOID +NTAPI +MmUpdatePageDir(IN PEPROCESS Process, + IN PVOID Address, + IN ULONG Size) +{ + /* Nothing to do */ + return; +} + +NTSTATUS +NTAPI +Mmi386ReleaseMmInfo(IN PEPROCESS Process) +{ + UNIMPLEMENTED; + while (TRUE); + return 0; +} + +NTSTATUS +NTAPI +MmInitializeHandBuiltProcess(IN PEPROCESS Process, + IN PULONG DirectoryTableBase) +{ + UNIMPLEMENTED; + while (TRUE); + return STATUS_SUCCESS; +} + +PULONG +NTAPI +MmGetPageDirectory(VOID) +{ + /* Return the TTB */ + return (PULONG)KeArmTranslationTableRegisterGet().AsUlong; +} + +VOID +NTAPI +MmDisableVirtualMapping(IN PEPROCESS Process, + IN PVOID Address, + OUT PBOOLEAN WasDirty, + OUT PPFN_TYPE Page) +{ + UNIMPLEMENTED; + while (TRUE); +} + +VOID +NTAPI +MmEnableVirtualMapping(IN PEPROCESS Process, + IN PVOID Address) +{ + UNIMPLEMENTED; + while (TRUE); +} + +NTSTATUS +NTAPI +MmCreateVirtualMappingUnsafe(IN PEPROCESS Process, + IN PVOID Address, + IN ULONG Protection, + IN PPFN_TYPE Pages, + IN ULONG PageCount) +{ + UNIMPLEMENTED; + while (TRUE); + return STATUS_SUCCESS; +} + +NTSTATUS +NTAPI +MmCreateVirtualMapping(IN PEPROCESS Process, + IN PVOID Address, + IN ULONG Protection, + IN PPFN_TYPE Pages, + IN ULONG PageCount) +{ + UNIMPLEMENTED; + while (TRUE); + return STATUS_SUCCESS; +} + +VOID +NTAPI +MmRawDeleteVirtualMapping(IN PVOID Address) +{ + UNIMPLEMENTED; + while (TRUE); +} + +VOID +NTAPI +MmDeleteVirtualMapping(IN PEPROCESS Process, + IN PVOID Address, + IN BOOLEAN FreePage, + OUT PBOOLEAN WasDirty, + OUT PPFN_TYPE Page) +{ + UNIMPLEMENTED; + while (TRUE); +} + +VOID +NTAPI +MmDeletePageFileMapping(IN PEPROCESS Process, + IN PVOID Address, + IN SWAPENTRY *SwapEntry) +{ + UNIMPLEMENTED; + while (TRUE); +} + +NTSTATUS +NTAPI +MmCreatePageFileMapping(IN PEPROCESS Process, + IN PVOID Address, + IN SWAPENTRY SwapEntry) +{ + UNIMPLEMENTED; + while (TRUE); + return 0; +} + +PFN_TYPE +NTAPI +MmGetPfnForProcess(IN PEPROCESS Process, + IN PVOID Address) +{ + UNIMPLEMENTED; + while (TRUE); + return 0; +} + +BOOLEAN +NTAPI +MmIsDirtyPage(IN PEPROCESS Process, + IN PVOID Address) +{ + UNIMPLEMENTED; + while (TRUE); + return 0; +} + +VOID +NTAPI +MmSetCleanPage(IN PEPROCESS Process, + IN PVOID Address) +{ + UNIMPLEMENTED; + while (TRUE); +} + +VOID +NTAPI +MmSetDirtyPage(IN PEPROCESS Process, + IN PVOID Address) +{ + UNIMPLEMENTED; + while (TRUE); +} + +BOOLEAN +NTAPI +MmIsPagePresent(IN PEPROCESS Process, + IN PVOID Address) +{ + UNIMPLEMENTED; + while (TRUE); + return FALSE; +} + +BOOLEAN +NTAPI +MmIsPageSwapEntry(IN PEPROCESS Process, + IN PVOID Address) +{ + UNIMPLEMENTED; + while (TRUE); + return FALSE; +} + +ULONG +NTAPI +MmGetPageProtect(IN PEPROCESS Process, + IN PVOID Address) +{ + /* We don't enforce any protection on the pages -- they are all RWX */ + return PAGE_READWRITE; +} + +VOID +NTAPI +MmSetPageProtect(IN PEPROCESS Process, + IN PVOID Address, + IN ULONG Protection) +{ + /* We don't enforce any protection on the pages -- they are all RWX */ + return; +} + +VOID +NTAPI +MmInitGlobalKernelPageDirectory(VOID) +{ + ULONG i; + PULONG CurrentPageDirectory = (PULONG)PDE_BASE; + extern MMPTE HyperTemplatePte; + + /* Setup template */ + HyperTemplatePte.u.Hard.Valid = HyperTemplatePte.u.Hard.Access = 1; + + /* Loop the 2GB of address space which belong to the kernel */ + for (i = MiGetPdeOffset(MmSystemRangeStart); i < 2048; i++) + { + /* Check if we have an entry for this already */ + if ((i != MiGetPdeOffset(PTE_BASE)) && + (i != MiGetPdeOffset(HYPER_SPACE)) && + (!MmGlobalKernelPageDirectory[i]) && + (CurrentPageDirectory[i])) + { + /* We don't, link it in our global page directory */ + MmGlobalKernelPageDirectory[i] = CurrentPageDirectory[i]; + } + } +} + +/* PUBLIC FUNCTIONS ***********************************************************/ + +/* + * @implemented + */ +PHYSICAL_ADDRESS +NTAPI +MmGetPhysicalAddress(IN PVOID Address) +{ + PHYSICAL_ADDRESS PhysicalAddress; + PhysicalAddress.QuadPart = 0; + + UNIMPLEMENTED; + while (TRUE); + + return PhysicalAddress; +} Propchange: trunk/reactos/ntoskrnl/mm/arm/page.c ------------------------------------------------------------------------------ svn:eol-style = native Modified: trunk/reactos/ntoskrnl/ntoskrnl-generic.rbuild URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ntoskrnl-generic.… ============================================================================== --- trunk/reactos/ntoskrnl/ntoskrnl-generic.rbuild [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/ntoskrnl-generic.rbuild [iso-8859-1] Tue Feb 9 03:14:20 2010 @@ -365,7 +365,7 @@ </if> <if property="ARCH" value="arm"> <directory name="arm"> - <file>stubs.c</file> + <file>page.c</file> </directory> </if> <if property="ARCH" value="powerpc"> [View Less]

15 years, 4 months

[sir_richard] 45514: [NTOS]: All calls to DbgPrint will go to DbgPrintEarly for now. [NTOS]: More header fixes to match new definitions.

by sir_richard＠svn.reactos.org

Author: sir_richard Date: Tue Feb 9 03:12:27 2010 New Revision: 45514 URL: http://svn.reactos.org/svn/reactos?rev=45514&view=rev Log: [NTOS]: All calls to DbgPrint will go to DbgPrintEarly for now. [NTOS]: More header fixes to match new definitions. Modified: trunk/reactos/ntoskrnl/include/internal/arm/ke.h trunk/reactos/ntoskrnl/include/internal/arm/mm.h trunk/reactos/ntoskrnl/include/precomp.h Modified: trunk/reactos/ntoskrnl/include/internal/arm/ke.h URL: http://svn.… [View More]reactos.org/svn/reactos/trunk/reactos/ntoskrnl/include/internal/… ============================================================================== --- trunk/reactos/ntoskrnl/include/internal/arm/ke.h [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/include/internal/arm/ke.h [iso-8859-1] Tue Feb 9 03:12:27 2010 @@ -54,7 +54,7 @@ // All architectures but x86 have it in the PRCB's KeContextSwitches // #define KeGetContextSwitches(Prcb) \ - Prcb->KeContextSwitches + CONTAINING_RECORD(Prcb, KIPCR, PrcbData)->ContextSwitches // // Returns the Interrupt State from a Trap Frame. @@ -108,13 +108,6 @@ #include "mm.h" VOID -KeFillFixedEntryTb( - IN ARM_PTE Pte, - IN PVOID Virtual, - IN ULONG Index -); - -VOID KeFlushTb( VOID ); Modified: trunk/reactos/ntoskrnl/include/internal/arm/mm.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/include/internal/… ============================================================================== --- trunk/reactos/ntoskrnl/include/internal/arm/mm.h [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/include/internal/arm/mm.h [iso-8859-1] Tue Feb 9 03:12:27 2010 @@ -27,6 +27,7 @@ #define PDE_BASE 0xC0400000 #define HYPER_SPACE 0xC0404000 +#if 0 typedef struct _HARDWARE_PDE_ARMV6 { ULONG Valid:1; // Only for small pages @@ -77,6 +78,7 @@ C_ASSERT(sizeof(HARDWARE_PDE_ARMV6) == sizeof(ULONG)); C_ASSERT(sizeof(HARDWARE_LARGE_PTE_ARMV6) == sizeof(ULONG)); C_ASSERT(sizeof(HARDWARE_PTE_ARMV6) == sizeof(ULONG)); +#endif /* For FreeLDR */ typedef struct _PAGE_TABLE_ARM Modified: trunk/reactos/ntoskrnl/include/precomp.h URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/include/precomp.h… ============================================================================== --- trunk/reactos/ntoskrnl/include/precomp.h [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/include/precomp.h [iso-8859-1] Tue Feb 9 03:12:27 2010 @@ -7,6 +7,11 @@ */ /* INCLUDES ******************************************************************/ + +/* ARM Bringup Hack */ +#ifdef _M_ARM +#define DbgPrint DbgPrintEarly +#endif /* Version Data */ #undef __MSVCRT__ [View Less]

15 years, 4 months

[sir_richard] 45513: [NTOS]: Make system startup match x86 code as closely as possible, instead of mixing MIPS/PPC code. Only rip out parts that are obviously x86-specific. Also fix code to use new KPCR definitions. [NTOS]: Implement a DbgPrintEarly function that directly uses KDCOM to print to the serial console, instead of going through the Debug Service Interrupt.

by sir_richard＠svn.reactos.org

Author: sir_richard Date: Tue Feb 9 03:11:18 2010 New Revision: 45513 URL: http://svn.reactos.org/svn/reactos?rev=45513&view=rev Log: [NTOS]: Make system startup match x86 code as closely as possible, instead of mixing MIPS/PPC code. Only rip out parts that are obviously x86-specific. Also fix code to use new KPCR definitions. [NTOS]: Implement a DbgPrintEarly function that directly uses KDCOM to print to the serial console, instead of going through the Debug Service Interrupt. Modified: … [View More] trunk/reactos/ntoskrnl/ke/arm/kiinit.c Modified: trunk/reactos/ntoskrnl/ke/arm/kiinit.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ke/arm/kiinit.c?r… ============================================================================== --- trunk/reactos/ntoskrnl/ke/arm/kiinit.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/ke/arm/kiinit.c [iso-8859-1] Tue Feb 9 03:11:18 2010 @@ -28,9 +28,7 @@ NTAPI KiInitMachineDependent(VOID) { - // - // There is nothing to do on ARM - // + /* There is nothing to do on ARM */ return; } @@ -43,169 +41,55 @@ IN CCHAR Number, IN PLOADER_PARAMETER_BLOCK LoaderBlock) { + PKIPCR Pcr = (PKIPCR)KeGetPcr(); ULONG PageDirectory[2]; - PKPCR Pcr; ULONG i; - - // - // Initialize the platform - // - HalInitializeProcessor(Number, LoaderBlock); - - // - // Save loader block - // - KeLoaderBlock = LoaderBlock; - - // - // Setup KPRCB - // - Prcb->MajorVersion = 1; - Prcb->MinorVersion = 1; - Prcb->BuildType = 0; -#ifndef CONFIG_SMP - Prcb->BuildType |= PRCB_BUILD_UNIPROCESSOR; -#endif -#if DBG - Prcb->BuildType |= PRCB_BUILD_DEBUG; -#endif - Prcb->CurrentThread = InitThread; - Prcb->NextThread = NULL; - Prcb->IdleThread = InitThread; - Prcb->Number = Number; - Prcb->SetMember = 1 << Number; - Prcb->PcrPage = LoaderBlock->u.Arm.PcrPage; - - // - // Initialize spinlocks and DPC data - // + + /* Set the default NX policy (opt-in) */ + SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_OPTIN; + + /* Initialize spinlocks and DPC data */ KiInitSpinLocks(Prcb, Number); - - // - // Set the PRCB in the processor block - // - KiProcessorBlock[(ULONG)Number] = Prcb; - Pcr = (PKPCR)KeGetPcr(); - - // - // Set processor information - // - KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_ARM; - KeFeatureBits = 0; - KeProcessorLevel = (USHORT)(Pcr->ProcessorId >> 8); - KeProcessorRevision = (USHORT)(Pcr->ProcessorId & 0xFF); - - // - // Set stack pointers - // + + /* Set stack pointers */ Pcr->InitialStack = IdleStack; - Pcr->StackLimit = (PVOID)((ULONG_PTR)IdleStack - KERNEL_STACK_SIZE); - - // - // Check if this is the Boot CPU - // + + /* Check if this is the Boot CPU */ if (!Number) { - // - // Setup the unexpected interrupt - // + /* Setup the unexpected interrupt */ KxUnexpectedInterrupt.DispatchAddress = KiUnexpectedInterrupt; for (i = 0; i < 4; i++) { - // - // Copy the template code - // + /* Copy the template code */ KxUnexpectedInterrupt.DispatchCode[i] = ((PULONG)KiInterruptTemplate)[i]; } - // - // Set DMA coherency - // + /* Set DMA coherency */ KiDmaIoCoherency = 0; - // - // Sweep D-Cache - // + /* Sweep D-Cache */ HalSweepDcache(); - } - - // - // Set all interrupt routines to unexpected interrupts as well - // - for (i = 0; i < MAXIMUM_VECTOR; i++) - { - // - // Point to the same template - // - Pcr->InterruptRoutine[i] = (PVOID)&KxUnexpectedInterrupt.DispatchCode; - } - - // - // Setup profiling - // - Pcr->ProfileCount = 0; - Pcr->ProfileInterval = 0x200000; - Pcr->StallScaleFactor = 50; - - // - // Setup software interrupts - // - Pcr->InterruptRoutine[PASSIVE_LEVEL] = KiPassiveRelease; - Pcr->InterruptRoutine[APC_LEVEL] = KiApcInterrupt; - Pcr->InterruptRoutine[DISPATCH_LEVEL] = KiDispatchInterrupt; - Pcr->ReservedVectors = (1 << PASSIVE_LEVEL) | - (1 << APC_LEVEL) | - (1 << DISPATCH_LEVEL) | - (1 << IPI_LEVEL); - - // - // Set IRQL and prcessor member/number - // - Pcr->CurrentIrql = APC_LEVEL; - Pcr->SetMember = 1 << Number; - Pcr->NotMember = -Pcr->SetMember; - Pcr->Number = Number; - - // - // Remember our parent - // - InitThread->ApcState.Process = InitProcess; - - // - // Setup the active processor numbers - // - KeActiveProcessors |= 1 << Number; - KeNumberProcessors = Number + 1; - - // - // Check if this is the boot CPU - // - if (!Number) - { - // - // Setup KD - // - KdInitSystem(0, LoaderBlock); - - // - // Check for break-in - // - if (KdPollBreakIn()) DbgBreakPointWithStatus(DBG_STATUS_CONTROL_C); - - // - // Cleanup the rest of the processor block array - // - for (i = 1; i < MAXIMUM_PROCESSORS; i++) KiProcessorBlock[i] = NULL; - - // - // Initialize portable parts of the OS - // + + /* Set boot-level flags */ + KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_ARM; + KeFeatureBits = 0; + KeProcessorLevel = (USHORT)(Pcr->ProcessorId >> 8); + KeProcessorRevision = (USHORT)(Pcr->ProcessorId & 0xFF); + + /* Set the current MP Master KPRCB to the Boot PRCB */ + Prcb->MultiThreadSetMaster = Prcb; + + /* Lower to APC_LEVEL */ + KeLowerIrql(APC_LEVEL); + + /* Initialize portable parts of the OS */ KiInitSystem(); - // - // Initialize the Idle Process and the Process Listhead - // + /* Initialize the Idle Process and the Process Listhead */ InitializeListHead(&KiProcessListHead); + PageDirectory[0] = 0; + PageDirectory[1] = 0; KeInitializeProcess(InitProcess, 0, 0xFFFFFFFF, @@ -215,15 +99,11 @@ } else { - // - // FIXME-V6: See if we want to support MP - // + /* FIXME-V6: See if we want to support MP */ DPRINT1("ARM MPCore not supported\n"); } - - // - // Setup the Idle Thread - // + + /* Setup the Idle Thread */ KeInitializeThread(InitProcess, InitThread, NULL, @@ -239,253 +119,310 @@ InitThread->WaitIrql = DISPATCH_LEVEL; InitProcess->ActiveProcessors = 1 << Number; - // - // HACK for MmUpdatePageDir - // + /* HACK for MmUpdatePageDir */ ((PETHREAD)InitThread)->ThreadsProcess = (PEPROCESS)InitProcess; - // - // Initialize the Kernel Executive - // + /* Set up the thread-related fields in the PRCB */ + Prcb->CurrentThread = InitThread; + Prcb->NextThread = NULL; + Prcb->IdleThread = InitThread; + + /* Initialize the Kernel Executive */ ExpInitializeExecutive(Number, LoaderBlock); - - // - // Only do this on the boot CPU - // + + /* Only do this on the boot CPU */ if (!Number) { - // - // Calculate the time reciprocal - // + /* Calculate the time reciprocal */ KiTimeIncrementReciprocal = - KiComputeReciprocal(KeMaximumIncrement, - &KiTimeIncrementShiftCount); - - // - // Update DPC Values in case they got updated by the executive - // + KiComputeReciprocal(KeMaximumIncrement, + &KiTimeIncrementShiftCount); + + /* Update DPC Values in case they got updated by the executive */ Prcb->MaximumDpcQueueDepth = KiMaximumDpcQueueDepth; Prcb->MinimumDpcRate = KiMinimumDpcRate; Prcb->AdjustDpcThreshold = KiAdjustDpcThreshold; } - - // - // Raise to Dispatch - // + + /* Raise to Dispatch */ KfRaiseIrql(DISPATCH_LEVEL); - - // - // Set the Idle Priority to 0. This will jump into Phase 1 - // + + /* Set the Idle Priority to 0. This will jump into Phase 1 */ KeSetPriorityThread(InitThread, 0); - - // - // If there's no thread scheduled, put this CPU in the Idle summary - // + + /* If there's no thread scheduled, put this CPU in the Idle summary */ KiAcquirePrcbLock(Prcb); if (!Prcb->NextThread) KiIdleSummary |= 1 << Number; KiReleasePrcbLock(Prcb); - - // - // Raise back to HIGH_LEVEL - // + + /* Raise back to HIGH_LEVEL and clear the PRCB for the loader block */ KfRaiseIrql(HIGH_LEVEL); -} + LoaderBlock->Prcb = 0; +} + +C_ASSERT((PKIPCR)KeGetPcr() == (PKIPCR)0xFFDFF000); +C_ASSERT((FIELD_OFFSET(KIPCR, FirstLevelDcacheSize) & 4) == 0); +C_ASSERT(sizeof(KIPCR) <= PAGE_SIZE); VOID -KiInitializeSystem(IN ULONG Magic, - IN PLOADER_PARAMETER_BLOCK LoaderBlock) -{ - ARM_PTE Pte; - PKPCR Pcr; - ARM_CONTROL_REGISTER ControlRegister; - - // - // Detect ARM version (Architecture 6 is the ARMv5TE-J, go figure!) - // - KeIsArmV6 = KeArmIdCodeRegisterGet().Architecture == 7; - - // - // Set the number of TLB entries and ASIDs - // +NTAPI +KiInitializePcr(IN ULONG ProcessorNumber, + IN PKIPCR Pcr, + IN PKTHREAD IdleThread, + IN PVOID PanicStack, + IN PVOID InterruptStack) +{ + ULONG i; + + /* Set the Current Thread */ + Pcr->PrcbData.CurrentThread = IdleThread; + + /* Set pointers to ourselves */ + Pcr->Self = (PKPCR)Pcr; + Pcr->Prcb = &Pcr->PrcbData; + + /* Set the PCR Version */ + Pcr->MajorVersion = PCR_MAJOR_VERSION; + Pcr->MinorVersion = PCR_MINOR_VERSION; + + /* Set the PCRB Version */ + Pcr->PrcbData.MajorVersion = 1; + Pcr->PrcbData.MinorVersion = 1; + + /* Set the Build Type */ + Pcr->PrcbData.BuildType = 0; +#ifndef CONFIG_SMP + Pcr->PrcbData.BuildType |= PRCB_BUILD_UNIPROCESSOR; +#endif +#if DBG + Pcr->PrcbData.BuildType |= PRCB_BUILD_DEBUG; +#endif + + /* Set the Processor Number and current Processor Mask */ + Pcr->PrcbData.Number = (UCHAR)ProcessorNumber; + Pcr->PrcbData.SetMember = 1 << ProcessorNumber; + + /* Set the PRCB for this Processor */ + KiProcessorBlock[ProcessorNumber] = Pcr->Prcb; + + /* Start us out at PASSIVE_LEVEL */ + Pcr->Irql = PASSIVE_LEVEL; + + /* Set the stacks */ + Pcr->PanicStack = PanicStack; + Pcr->InterruptStack = InterruptStack; + + /* Setup the processor set */ + Pcr->PrcbData.MultiThreadProcessorSet = Pcr->PrcbData.SetMember; + + /* Copy cache information from the loader block */ + Pcr->FirstLevelDcacheSize = KeLoaderBlock->u.Arm.FirstLevelDcacheSize; + Pcr->SecondLevelDcacheSize = KeLoaderBlock->u.Arm.SecondLevelDcacheSize; + Pcr->FirstLevelIcacheSize = KeLoaderBlock->u.Arm.FirstLevelIcacheSize; + Pcr->SecondLevelIcacheSize = KeLoaderBlock->u.Arm.SecondLevelIcacheSize; + Pcr->FirstLevelDcacheFillSize = KeLoaderBlock->u.Arm.FirstLevelDcacheFillSize; + Pcr->SecondLevelDcacheFillSize = KeLoaderBlock->u.Arm.SecondLevelDcacheFillSize; + Pcr->FirstLevelIcacheFillSize = KeLoaderBlock->u.Arm.FirstLevelIcacheFillSize; + Pcr->SecondLevelIcacheFillSize = KeLoaderBlock->u.Arm.SecondLevelIcacheFillSize; + + /* Set global d-cache fill and alignment values */ + if (!Pcr->SecondLevelDcacheSize) + { + /* Use the first level */ + Pcr->DcacheFillSize = Pcr->FirstLevelDcacheSize; + } + else + { + /* Use the second level */ + Pcr->DcacheFillSize = Pcr->SecondLevelDcacheSize; + } + + /* Set the alignment */ + Pcr->DcacheAlignment = Pcr->DcacheFillSize - 1; + + /* Set global i-cache fill and alignment values */ + if (!Pcr->SecondLevelIcacheSize) + { + /* Use the first level */ + Pcr->IcacheFillSize = Pcr->FirstLevelIcacheSize; + } + else + { + /* Use the second level */ + Pcr->IcacheFillSize = Pcr->SecondLevelIcacheSize; + } + + /* Set the alignment */ + Pcr->IcacheAlignment = Pcr->IcacheFillSize - 1; + + /* Set processor information */ + Pcr->ProcessorId = KeArmIdCodeRegisterGet().AsUlong; + + /* Set all interrupt routines to unexpected interrupts as well */ + for (i = 0; i < MAXIMUM_VECTOR; i++) + { + /* Point to the same template */ + Pcr->InterruptRoutine[i] = (PVOID)&KxUnexpectedInterrupt.DispatchCode; + } + + /* Set default stall factor */ + Pcr->StallScaleFactor = 50; + + /* Setup software interrupts */ + Pcr->InterruptRoutine[PASSIVE_LEVEL] = KiPassiveRelease; + Pcr->InterruptRoutine[APC_LEVEL] = KiApcInterrupt; + Pcr->InterruptRoutine[DISPATCH_LEVEL] = KiDispatchInterrupt; + Pcr->ReservedVectors = (1 << PASSIVE_LEVEL) | + (1 << APC_LEVEL) | + (1 << DISPATCH_LEVEL) | + (1 << IPI_LEVEL); +} + +VOID +KiInitializeMachineType(VOID) +{ + /* Detect ARM version */ + KeIsArmV6 = KeArmIdCodeRegisterGet().Architecture >= 7; + + /* Set the number of TLB entries and ASIDs */ KeNumberTbEntries = 64; if (__ARMV6__) { - // - // 256 ASIDs on v6/v7 - // + /* 256 ASIDs on v6/v7 */ KeNumberProcessIds = 256; } else { - // - // The TLB is VIVT on v4/v5 - // + /* The TLB is VIVT on v4/v5 */ KeNumberProcessIds = 0; } - - // - // Flush the TLB - // +} + +VOID +KiInitializeSystem(IN PLOADER_PARAMETER_BLOCK LoaderBlock) +{ + ULONG Cpu; + PKTHREAD InitialThread; + PKPROCESS InitialProcess; + ARM_CONTROL_REGISTER ControlRegister; + PKIPCR Pcr = (PKIPCR)KeGetPcr(); + PKTHREAD Thread; + + /* Flush the TLB */ KeFlushTb(); - // - // Build the KIPCR pte - // - Pte.L1.Section.Type = SectionPte; - Pte.L1.Section.Buffered = FALSE; - Pte.L1.Section.Cached = FALSE; - Pte.L1.Section.Reserved = 1; // ARM926EJ-S manual recommends setting to 1 - Pte.L1.Section.Domain = Domain0; - Pte.L1.Section.Access = SupervisorAccess; - Pte.L1.Section.BaseAddress = LoaderBlock->u.Arm.PcrPage; - Pte.L1.Section.Ignored = Pte.L1.Section.Ignored1 = 0; - - // - // Map it into kernel address space by locking it into the TLB - // - KeFillFixedEntryTb(Pte, (PVOID)KIPCR, PCR_ENTRY); - - // - // Now map the PCR into user address space as well (read-only) - // - Pte.L1.Section.Access = SharedAccess; - KeFillFixedEntryTb(Pte, (PVOID)USPCR, PCR_ENTRY + 1); - - // - // Now we should be able to use the PCR... - // - Pcr = (PKPCR)KeGetPcr(); - - // - // Set the cache policy (HACK) - // - Pcr->CachePolicy = 0; - Pcr->AlignedCachePolicy = 0; - - // - // Copy cache information from the loader block - // - Pcr->FirstLevelDcacheSize = LoaderBlock->u.Arm.FirstLevelDcacheSize; - Pcr->SecondLevelDcacheSize = LoaderBlock->u.Arm.SecondLevelDcacheSize; - Pcr->FirstLevelIcacheSize = LoaderBlock->u.Arm.FirstLevelIcacheSize; - Pcr->SecondLevelIcacheSize = LoaderBlock->u.Arm.SecondLevelIcacheSize; - Pcr->FirstLevelDcacheFillSize = LoaderBlock->u.Arm.FirstLevelDcacheFillSize; - Pcr->SecondLevelDcacheFillSize = LoaderBlock->u.Arm.SecondLevelDcacheFillSize; - Pcr->FirstLevelIcacheFillSize = LoaderBlock->u.Arm.FirstLevelIcacheFillSize; - Pcr->SecondLevelIcacheFillSize = LoaderBlock->u.Arm.SecondLevelIcacheFillSize; - - // - // Set global d-cache fill and alignment values - // - if (!Pcr->SecondLevelDcacheSize) - { - // - // Use the first level - // - Pcr->DcacheFillSize = Pcr->FirstLevelDcacheSize; - } - else - { - // - // Use the second level - // - Pcr->DcacheFillSize = Pcr->SecondLevelDcacheSize; - } - - // - // Set the alignment - // - Pcr->DcacheAlignment = Pcr->DcacheFillSize - 1; - - // - // Set global i-cache fill and alignment values - // - if (!Pcr->SecondLevelIcacheSize) - { - // - // Use the first level - // - Pcr->IcacheFillSize = Pcr->FirstLevelIcacheSize; - } - else - { - // - // Use the second level - // - Pcr->IcacheFillSize = Pcr->SecondLevelIcacheSize; - } - - // - // Set the alignment - // - Pcr->IcacheAlignment = Pcr->IcacheFillSize - 1; - - // - // Now sweep caches - // + /* Save the loader block and get the current CPU */ + KeLoaderBlock = LoaderBlock; + Cpu = KeNumberProcessors; + + /* Save the initial thread and process */ + InitialThread = (PKTHREAD)LoaderBlock->Thread; + InitialProcess = (PKPROCESS)LoaderBlock->Process; + + /* Clean the APC List Head */ + InitializeListHead(&InitialThread->ApcState.ApcListHead[KernelMode]); + + /* Initialize the machine type */ + KiInitializeMachineType(); + + /* Skip initial setup if this isn't the Boot CPU */ + if (Cpu) goto AppCpuInit; + + /* Initialize the PCR */ + RtlZeroMemory(Pcr, PAGE_SIZE); + KiInitializePcr(Cpu, + Pcr, + InitialThread, + (PVOID)LoaderBlock->u.Arm.PanicStack, + (PVOID)LoaderBlock->u.Arm.InterruptStack); + + /* Now sweep caches */ HalSweepIcache(); HalSweepDcache(); - // - // Set PCR version - // - Pcr->MinorVersion = PCR_MINOR_VERSION; - Pcr->MajorVersion = PCR_MAJOR_VERSION; - - // - // Set boot PRCB - // - Pcr->Prcb = (PKPRCB)LoaderBlock->Prcb; - - // - // Set the different stacks - // - Pcr->InitialStack = (PVOID)LoaderBlock->KernelStack; - Pcr->PanicStack = (PVOID)LoaderBlock->u.Arm.PanicStack; - Pcr->InterruptStack = (PVOID)LoaderBlock->u.Arm.InterruptStack; - - // - // Set the current thread - // - Pcr->CurrentThread = (PKTHREAD)LoaderBlock->Thread; - - // - // Set the current IRQL to high - // - Pcr->CurrentIrql = HIGH_LEVEL; - - // - // Set processor information - // - Pcr->ProcessorId = KeArmIdCodeRegisterGet().AsUlong; - Pcr->SystemReserved[0] = KeArmControlRegisterGet().AsUlong; - - // - // Set the exception address to high - // + /* Set us as the current process */ + InitialThread->ApcState.Process = InitialProcess; + +AppCpuInit: + /* Setup CPU-related fields */ + Pcr->Number = Cpu; + Pcr->SetMember = 1 << Cpu; + Pcr->SetMemberCopy = 1 << Cpu; + Pcr->PrcbData.SetMember = 1 << Cpu; + + /* Initialize the Processor with HAL */ + HalInitializeProcessor(Cpu, KeLoaderBlock); + + /* Set active processors */ + KeActiveProcessors |= Pcr->SetMember; + KeNumberProcessors++; + + /* Check if this is the boot CPU */ + if (!Cpu) + { + /* Initialize debugging system */ + KdInitSystem(0, KeLoaderBlock); + + /* Check for break-in */ + if (KdPollBreakIn()) DbgBreakPointWithStatus(DBG_STATUS_CONTROL_C); + } + + /* Raise to HIGH_LEVEL */ + KfRaiseIrql(HIGH_LEVEL); + + /* Set the exception address to high */ ControlRegister = KeArmControlRegisterGet(); ControlRegister.HighVectors = TRUE; KeArmControlRegisterSet(ControlRegister); - // - // Setup the exception vector table - // + /* Setup the exception vector table */ RtlCopyMemory((PVOID)0xFFFF0000, &KiArmVectorTable, 14 * sizeof(PVOID)); - // - // Initialize the rest of the kernel now - // + /* Initialize the rest of the kernel now */ KiInitializeKernel((PKPROCESS)LoaderBlock->Process, (PKTHREAD)LoaderBlock->Thread, (PVOID)LoaderBlock->KernelStack, - (PKPRCB)LoaderBlock->Prcb, + Pcr->Prcb, Pcr->Prcb->Number, - LoaderBlock); - - - // - // Jump to idle loop - // + KeLoaderBlock); + + /* Set the priority of this thread to 0 */ + Thread = KeGetCurrentThread(); + Thread->Priority = 0; + + /* Force interrupts enabled and lower IRQL back to DISPATCH_LEVEL */ + _enable(); + KfLowerIrql(DISPATCH_LEVEL); + + /* Set the right wait IRQL */ + Thread->WaitIrql = DISPATCH_LEVEL; + + /* Jump into the idle loop */ KiIdleLoop(); } + +ULONG +DbgPrintEarly(const char *fmt, ...) +{ + va_list args; + unsigned int i; + char Buffer[1024]; + PCHAR String = Buffer; + + va_start(args, fmt); + i = vsprintf(Buffer, fmt, args); + va_end(args); + + /* Output the message */ + while (*String != 0) + { + if (*String == '\n') + { + KdPortPutByteEx(NULL, '\r'); + } + KdPortPutByteEx(NULL, *String); + String++; + } + + return STATUS_SUCCESS; +} [View Less]

15 years, 4 months

[sir_richard] 45512: [NTOS]: Update code to use new KPCR structure. [NTOS]: Make all trap code currently spin forever, because it has not been reviewed yet.

by sir_richard＠svn.reactos.org

Author: sir_richard Date: Tue Feb 9 03:09:34 2010 New Revision: 45512 URL: http://svn.reactos.org/svn/reactos?rev=45512&view=rev Log: [NTOS]: Update code to use new KPCR structure. [NTOS]: Make all trap code currently spin forever, because it has not been reviewed yet. Modified: trunk/reactos/ntoskrnl/ke/arm/trapc.c trunk/reactos/ntoskrnl/ke/arm/usercall.c Modified: trunk/reactos/ntoskrnl/ke/arm/trapc.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ke/arm/trapc.… [View More]c?re… ============================================================================== --- trunk/reactos/ntoskrnl/ke/arm/trapc.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/ke/arm/trapc.c [iso-8859-1] Tue Feb 9 03:09:34 2010 @@ -25,6 +25,9 @@ // // Loop forever... that's why this is an idle loop // + DPRINT1("[IDLE LOOP]\n"); + while (TRUE); + while (TRUE) { // @@ -117,9 +120,12 @@ KiSwapContextInternal(IN PKTHREAD OldThread, IN PKTHREAD NewThread) { - PKPCR Pcr = (PKPCR)KeGetPcr(); + PKIPCR Pcr = (PKIPCR)KeGetPcr(); PKPRCB Prcb = Pcr->Prcb; PKPROCESS OldProcess, NewProcess; + + DPRINT1("SWAP\n"); + while (TRUE); // // Increase context switch count @@ -163,7 +169,7 @@ // Increase thread context switches // NewThread->ContextSwitches++; - +#if 0 // I don't buy this // // Set us as the current thread // NOTE: On RISC Platforms, there is both a KPCR CurrentThread, and a @@ -175,7 +181,7 @@ // there as well. // Pcr->CurrentThread = NewThread; - +#endif // // DPCs shouldn't be active // @@ -221,7 +227,9 @@ KPROCESSOR_MODE PreviousMode; KEXCEPTION_FRAME ExceptionFrame; PKTRAP_FRAME TrapFrame = KeGetCurrentThread()->TrapFrame; - //DPRINT1("[APC]\n"); + + DPRINT1("[APC TRAP]\n"); + while (TRUE); // // Isolate previous mode @@ -257,14 +265,17 @@ VOID KiDispatchInterrupt(VOID) { - PKPCR Pcr; + PKIPCR Pcr; PKPRCB Prcb; PKTHREAD NewThread, OldThread; + DPRINT1("[DPC TRAP]\n"); + while (TRUE); + // // Get the PCR and disable interrupts // - Pcr = (PKPCR)KeGetPcr(); + Pcr = (PKIPCR)KeGetPcr(); Prcb = Pcr->Prcb; _disable(); @@ -339,14 +350,14 @@ { KIRQL OldIrql, Irql; ULONG InterruptCause, InterruptMask; - PKPCR Pcr; + PKIPCR Pcr; PKTRAP_FRAME OldTrapFrame; ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00); // // Increment interrupt count // - Pcr = (PKPCR)KeGetPcr(); + Pcr = (PKIPCR)KeGetPcr(); Pcr->Prcb->InterruptCount++; // @@ -359,7 +370,7 @@ // Get the interrupt source // InterruptCause = HalGetInterruptSource(); -// DPRINT1("[INT] (%x) @ %p %p\n", InterruptCause, TrapFrame->SvcLr, TrapFrame->Pc); + //DPRINT1("[INT] (%x) @ %p %p\n", InterruptCause, TrapFrame->SvcLr, TrapFrame->Pc); // // Get the new IRQL and Interrupt Mask @@ -421,6 +432,10 @@ ULONG DebugType, Parameter0; EXCEPTION_RECORD ExceptionRecord; + DPRINT1("[PREFETCH ABORT] (%x) @ %p/%p/%p\n", + KeArmInstructionFaultStatusRegisterGet(), Address, TrapFrame->SvcLr, TrapFrame->Pc); + while (TRUE); + // // What we *SHOULD* do is look at the instruction fault status register // and see if it's equal to 2 (debug trap). Unfortunately QEMU doesn't seem @@ -483,8 +498,6 @@ // // Unhandled // - DPRINT1("[PREFETCH ABORT] (%x) @ %p/%p/%p\n", - KeArmInstructionFaultStatusRegisterGet(), Address, TrapFrame->SvcLr, TrapFrame->Pc); UNIMPLEMENTED; ASSERT(FALSE); return STATUS_SUCCESS; @@ -497,6 +510,10 @@ PVOID Address = (PVOID)KeArmFaultAddressRegisterGet(); ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00); + DPRINT1("[ABORT] (%x) @ %p/%p/%p\n", + KeArmFaultStatusRegisterGet(), Address, TrapFrame->SvcLr, TrapFrame->Pc); + while (TRUE); + // // Check if this is a page fault // @@ -512,8 +529,6 @@ // // Unhandled // - DPRINT1("[ABORT] (%x) @ %p/%p/%p\n", - KeArmFaultStatusRegisterGet(), Address, TrapFrame->SvcLr, TrapFrame->Pc); UNIMPLEMENTED; ASSERT(FALSE); return STATUS_SUCCESS; @@ -527,6 +542,9 @@ ULONG Instruction; ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00); + DPRINT1("[SWI] @ %p/%p\n", TrapFrame->SvcLr, TrapFrame->Pc); + while (TRUE); + // // Get the current thread // Modified: trunk/reactos/ntoskrnl/ke/arm/usercall.c URL: http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ke/arm/usercall.c… ============================================================================== --- trunk/reactos/ntoskrnl/ke/arm/usercall.c [iso-8859-1] (original) +++ trunk/reactos/ntoskrnl/ke/arm/usercall.c [iso-8859-1] Tue Feb 9 03:09:34 2010 @@ -226,7 +226,7 @@ // // Forcibly put us in a sane state // - KeGetPcr()->CurrentIrql = 0; + KeGetPcr()->Irql = 0; _disable(); // [View Less]

15 years, 4 months

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