Author: aandrejevic
Date: Fri Jun 21 01:44:56 2013
New Revision: 59272
URL: http://svn.reactos.org/svn/reactos?rev=59272&view=rev
Log:
[NTVDM]
Fix the PIC IRQ code. Interrupt requests only occur when no higher-priority IRQ is busy.
Modified:
branches/ntvdm/subsystems/ntvdm/hardware.c
Modified: branches/ntvdm/subsystems/ntvdm/hardware.c
URL: http://svn.reactos.org/svn/reactos/branches/ntvdm/subsystems/ntvdm/hardware…
==============================================================================
--- branches/ntvdm/subsystems/ntvdm/hardware.c [iso-8859-1] (original)
+++ branches/ntvdm/subsystems/ntvdm/hardware.c [iso-8859-1] Fri Jun 21 01:44:56 2013
@@ -219,17 +219,21 @@
}
VOID PicInterruptRequest(BYTE Number)
-{
+{
+ BYTE i;
+
if (Number >= 0 && Number < 8)
{
- /* Check if the interrupt is busy, in a cascade or masked */
- if (MasterPic.CascadeRegister & (1 << Number)
- || MasterPic.InServiceRegister & (1 << Number)
- || MasterPic.MaskRegister & (1 << Number))
- {
- return;
- }
-
+ /* Check if any of the higher-priorirty interrupts are busy */
+ for (i = 0; i <= Number ; i++)
+ {
+ if (MasterPic.InServiceRegister & (1 << Number)) return;
+ }
+
+ /* Check if the interrupt is masked */
+ if (MasterPic.MaskRegister & (1 << Number)) return;
+
+ /* Set the appropriate bit in the ISR and interrupt the CPU */
if (!MasterPic.AutoEoi) MasterPic.InServiceRegister |= 1 << Number;
EmulatorInterrupt(MasterPic.IntOffset + Number);
}
@@ -246,22 +250,21 @@
{
return;
}
-
- /* Check the if the slave PIC is busy or masked */
- if (MasterPic.InServiceRegister & (1 << 2)
- || MasterPic.MaskRegister & (1 << 2)) return;
+
+ /* Check if any of the higher-priorirty interrupts are busy */
+ if (MasterPic.InServiceRegister != 0) return;
+ for (i = 0; i <= Number ; i++)
+ {
+ if (SlavePic.InServiceRegister & (1 << Number)) return;
+ }
+
+ /* Check if the interrupt is masked */
+ if (SlavePic.MaskRegister & (1 << Number)) return;
/* Set the IRQ 2 bit in the master ISR */
if (!MasterPic.AutoEoi) MasterPic.InServiceRegister |= 1 << 2;
-
- /* Check if the interrupt is busy, in a cascade or masked */
- if (SlavePic.CascadeRegister & (1 << Number)
- || SlavePic.InServiceRegister & (1 << Number)
- || SlavePic.MaskRegister & (1 << Number))
- {
- return;
- }
-
+
+ /* Set the appropriate bit in the ISR and interrupt the CPU */
if (!SlavePic.AutoEoi) SlavePic.InServiceRegister |= 1 << Number;
EmulatorInterrupt(SlavePic.IntOffset + Number);
}
Author: aandrejevic
Date: Thu Jun 20 19:43:29 2013
New Revision: 59269
URL: http://svn.reactos.org/svn/reactos?rev=59269&view=rev
Log:
[NTVDM]
Make sure bit 2 in the ISR of the master PIC is set when an IRQ in the slave PIC occurs.
Modified:
branches/ntvdm/subsystems/ntvdm/hardware.c
Modified: branches/ntvdm/subsystems/ntvdm/hardware.c
URL: http://svn.reactos.org/svn/reactos/branches/ntvdm/subsystems/ntvdm/hardware…
==============================================================================
--- branches/ntvdm/subsystems/ntvdm/hardware.c [iso-8859-1] (original)
+++ branches/ntvdm/subsystems/ntvdm/hardware.c [iso-8859-1] Thu Jun 20 19:43:29 2013
@@ -188,6 +188,12 @@
{
return;
}
+
+ /* Check the if the slave PIC is busy */
+ if (MasterPic.InServiceRegister & (1 << 2)) return;
+
+ /* Set the IRQ 2 bit in the master ISR */
+ MasterPic.InServiceRegister |= 1 << 2;
/* Check if the interrupt is busy or in a cascade */
if (SlavePic.CascadeRegister & (1 << Number)