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[reactos] 03/05: [NTDLL_APITEST] Write NtAccessCheck testcase that tests for empty generic mapping scenario

by George Bișoc

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=fefb1b77458f05ecdc4e0… commit fefb1b77458f05ecdc4e0956c1b69c109f51142e Author: George Bișoc <george.bisoc(a)reactos.org> AuthorDate: Sat Sep 30 21:05:18 2023 +0200 Commit: George Bișoc <george.bisoc(a)reactos.org> CommitDate: Wed Oct 4 18:04:29 2023 +0200 [NTDLL_APITEST] Write NtAccessCheck testcase that tests for empty generic mapping scenario See b79aadd50bb7d5d6f08532284941c0334514c477 for further information. --- modules/rostests/apitests/ntdll/CMakeLists.txt | 1 + modules/rostests/apitests/ntdll/NtAccessCheck.c | 188 ++++++++++++++++++++++++ modules/rostests/apitests/ntdll/testlist.c | 2 + 3 files changed, 191 insertions(+) diff --git a/modules/rostests/apitests/ntdll/CMakeLists.txt b/modules/rostests/apitests/ntdll/CMakeLists.txt index 85515a2efaf..b6ce3a1cf4d 100644 --- a/modules/rostests/apitests/ntdll/CMakeLists.txt +++ b/modules/rostests/apitests/ntdll/CMakeLists.txt @@ -10,6 +10,7 @@ list(APPEND SOURCE load_notifications.c locale.c NtAcceptConnectPort.c + NtAccessCheck.c NtAccessCheckByType.c NtAccessCheckByTypeResultList.c NtAdjustGroupsToken.c diff --git a/modules/rostests/apitests/ntdll/NtAccessCheck.c b/modules/rostests/apitests/ntdll/NtAccessCheck.c new file mode 100644 index 00000000000..c987a445b13 --- /dev/null +++ b/modules/rostests/apitests/ntdll/NtAccessCheck.c @@ -0,0 +1,188 @@ +/* + * PROJECT: ReactOS API tests + * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later) + * PURPOSE: Tests for the NtAccessCheck API + * COPYRIGHT: Copyright 2023 George Bișoc <george.bisoc(a)reactos.org> + */ + +#include "precomp.h" + +static +HANDLE +GetToken(VOID) +{ + NTSTATUS Status; + HANDLE Token; + HANDLE DuplicatedToken; + OBJECT_ATTRIBUTES ObjectAttributes; + SECURITY_QUALITY_OF_SERVICE Sqos; + + Status = NtOpenProcessToken(NtCurrentProcess(), + TOKEN_QUERY | TOKEN_DUPLICATE, + &Token); + if (!NT_SUCCESS(Status)) + { + trace("Failed to get current process token (Status 0x%08lx)\n", Status); + return NULL; + } + + Sqos.Length = sizeof(SECURITY_QUALITY_OF_SERVICE); + Sqos.ImpersonationLevel = SecurityImpersonation; + Sqos.ContextTrackingMode = 0; + Sqos.EffectiveOnly = FALSE; + + InitializeObjectAttributes(&ObjectAttributes, + NULL, + 0, + NULL, + NULL); + ObjectAttributes.SecurityQualityOfService = &Sqos; + + Status = NtDuplicateToken(Token, + TOKEN_QUERY | TOKEN_DUPLICATE, + &ObjectAttributes, + FALSE, + TokenImpersonation, + &DuplicatedToken); + if (!NT_SUCCESS(Status)) + { + trace("Failed to duplicate token (Status 0x%08lx)\n", Status); + NtClose(Token); + return NULL; + } + + return DuplicatedToken; +} + +static +VOID +AccessCheckEmptyMappingTest(VOID) +{ + NTSTATUS Status; + NTSTATUS AccessStatus; + ACCESS_MASK GrantedAccess; + PPRIVILEGE_SET PrivilegeSet = NULL; + ULONG PrivilegeSetLength; + HANDLE Token = NULL; + PACL Dacl = NULL; + ULONG DaclSize; + SECURITY_DESCRIPTOR Sd; + PSID WorldSid = NULL; + static SID_IDENTIFIER_AUTHORITY WorldAuthority = {SECURITY_WORLD_SID_AUTHORITY}; + static GENERIC_MAPPING EmptyMapping = {0, 0, 0, 0}; + + /* Allocate all the stuff we need */ + PrivilegeSetLength = FIELD_OFFSET(PRIVILEGE_SET, Privilege[16]); + PrivilegeSet = RtlAllocateHeap(RtlGetProcessHeap(), 0, PrivilegeSetLength); + if (PrivilegeSet == NULL) + { + skip("Failed to allocate PrivilegeSet, skipping tests\n"); + return; + } + + Status = RtlAllocateAndInitializeSid(&WorldAuthority, + 1, + SECURITY_WORLD_RID, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + &WorldSid); + if (!NT_SUCCESS(Status)) + { + skip("Failed to create World SID, skipping tests\n"); + goto Quit; + } + + Token = GetToken(); + if (Token == NULL) + { + skip("Failed to get token, skipping tests\n"); + goto Quit; + } + + Status = RtlCreateSecurityDescriptor(&Sd, SECURITY_DESCRIPTOR_REVISION); + if (!NT_SUCCESS(Status)) + { + skip("Failed to create a security descriptor, skipping tests\n"); + goto Quit; + } + + DaclSize = sizeof(ACL) + + sizeof(ACCESS_ALLOWED_OBJECT_ACE) + RtlLengthSid(WorldSid); + Dacl = RtlAllocateHeap(RtlGetProcessHeap(), + HEAP_ZERO_MEMORY, + DaclSize); + if (Dacl == NULL) + { + skip("Failed to allocate memory for DACL, skipping tests\n"); + goto Quit; + } + + /* Setup a ACL and give full access to everyone */ + Status = RtlCreateAcl(Dacl, + DaclSize, + ACL_REVISION); + if (!NT_SUCCESS(Status)) + { + skip("Failed to create DACL, skipping tests\n"); + goto Quit; + } + + Status = RtlAddAccessAllowedAce(Dacl, + ACL_REVISION, + GENERIC_ALL, + WorldSid); + if (!NT_SUCCESS(Status)) + { + skip("Failed to add allowed ACE for World SID, skipping tests\n"); + goto Quit; + } + + /* Setup the descriptor */ + RtlSetGroupSecurityDescriptor(&Sd, WorldSid, FALSE); + RtlSetOwnerSecurityDescriptor(&Sd, WorldSid, FALSE); + RtlSetDaclSecurityDescriptor(&Sd, TRUE, Dacl, FALSE); + + /* Do an access check with empty mapping */ + Status = NtAccessCheck(&Sd, + Token, + MAXIMUM_ALLOWED, + &EmptyMapping, + PrivilegeSet, + &PrivilegeSetLength, + &GrantedAccess, + &AccessStatus); + ok_hex(Status, STATUS_SUCCESS); + ok(AccessStatus == STATUS_SUCCESS, "Expected a success status but got 0x%08lx\n", AccessStatus); + trace("GrantedAccess == 0x%08lx\n", GrantedAccess); + +Quit: + if (Dacl) + { + RtlFreeHeap(RtlGetProcessHeap(), 0, Dacl); + } + + if (Token) + { + NtClose(Token); + } + + if (WorldSid) + { + RtlFreeSid(WorldSid); + } + + if (PrivilegeSet) + { + RtlFreeHeap(RtlGetProcessHeap(), 0, PrivilegeSet); + } +} + +START_TEST(NtAccessCheck) +{ + AccessCheckEmptyMappingTest(); +} diff --git a/modules/rostests/apitests/ntdll/testlist.c b/modules/rostests/apitests/ntdll/testlist.c index 2be58938238..438cc56a172 100644 --- a/modules/rostests/apitests/ntdll/testlist.c +++ b/modules/rostests/apitests/ntdll/testlist.c @@ -6,6 +6,7 @@ extern void func_LdrEnumResources(void); extern void func_load_notifications(void); extern void func_NtAcceptConnectPort(void); +extern void func_NtAccessCheck(void); extern void func_NtAccessCheckByType(void); extern void func_NtAccessCheckByTypeResultList(void); extern void func_NtAdjustGroupsToken(void); @@ -102,6 +103,7 @@ const struct test winetest_testlist[] = { "LdrEnumResources", func_LdrEnumResources }, { "load_notifications", func_load_notifications }, { "NtAcceptConnectPort", func_NtAcceptConnectPort }, + { "NtAccessCheck", func_NtAccessCheck }, { "NtAccessCheckByType", func_NtAccessCheckByType }, { "NtAccessCheckByTypeResultList", func_NtAccessCheckByTypeResultList }, { "NtAdjustGroupsToken", func_NtAdjustGroupsToken },

1 year, 3 months

[reactos] 02/05: [NTOS:SE] HACK: Temporarily grant access to the client if empty generic mapping was passed

by George Bișoc

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=4b4638dc5599d5061a01a… commit 4b4638dc5599d5061a01a21ed04a1ce9b68e732d Author: George Bișoc <george.bisoc(a)reactos.org> AuthorDate: Sat Sep 30 20:51:12 2023 +0200 Commit: George Bișoc <george.bisoc(a)reactos.org> CommitDate: Wed Oct 4 18:04:29 2023 +0200 [NTOS:SE] HACK: Temporarily grant access to the client if empty generic mapping was passed Certain apps such as AIM installer passes an empty generic mapping (this can be understood with their generic masks set to 0) and our code tries to map the access right from an ACE with the mapping provided by AccessCheck. This can lead to a bug where we would not be able to decode the generic right from an ACE as we need a proper generic mapping in order to do so. A mask right that is not decoded it cannot be used to mask out the remaining rights, further resulting into a denied access right. What Windows does instead is they are mapping the ACE's rights in another place, presumably when setting security data to an object, and they are using the generic mapping passed by the kernel. What we can do for the time being is to temporarily grant access to the client, but only if they are an administrator. CORE-18576 --- ntoskrnl/se/accesschk.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/ntoskrnl/se/accesschk.c b/ntoskrnl/se/accesschk.c index eaf159f8ce1..858bfeef994 100644 --- a/ntoskrnl/se/accesschk.c +++ b/ntoskrnl/se/accesschk.c @@ -1058,6 +1058,34 @@ SepAccessCheckWorker( goto ReturnCommonStatus; } + /* + * HACK: Temporary hack that checks if the caller passed an empty + * generic mapping. In such cases we cannot mask out the remaining + * access rights without a proper mapping so the only option we + * can do is to check if the client is an administrator, + * since they are powerful users. + * + * See CORE-18576 for information. + */ + if (GenericMapping->GenericRead == 0 && + GenericMapping->GenericWrite == 0 && + GenericMapping->GenericExecute == 0 && + GenericMapping->GenericAll == 0) + { + if (SeTokenIsAdmin(Token)) + { + /* Grant him access */ + PreviouslyGrantedAccess |= RemainingAccess; + Status = STATUS_SUCCESS; + goto ReturnCommonStatus; + } + + /* It's not an admin so bail out */ + PreviouslyGrantedAccess = 0; + Status = STATUS_ACCESS_DENIED; + goto ReturnCommonStatus; + } + /* Get the DACL */ Status = RtlGetDaclSecurityDescriptor(SecurityDescriptor, &Present,

1 year, 3 months

[reactos] 01/05: [TCPIP] Setup a security descriptor for the IP and TCP device objects

by George Bișoc

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=95c104f29a45f4d959de9… commit 95c104f29a45f4d959de9342dcc63c0e8f3b5ae0 Author: George Bișoc <george.bisoc(a)reactos.org> AuthorDate: Mon Sep 25 20:18:11 2023 +0200 Commit: George Bișoc <george.bisoc(a)reactos.org> CommitDate: Wed Oct 4 18:04:17 2023 +0200 [TCPIP] Setup a security descriptor for the IP and TCP device objects Grant access to such objects to system, admins and network services. --- drivers/network/tcpip/include/tags.h | 1 + drivers/network/tcpip/tcpip/main.c | 218 +++++++++++++++++++++++++++++++++++ 2 files changed, 219 insertions(+) diff --git a/drivers/network/tcpip/include/tags.h b/drivers/network/tcpip/include/tags.h index 15c0b905dc2..8449afda7e0 100644 --- a/drivers/network/tcpip/include/tags.h +++ b/drivers/network/tcpip/include/tags.h @@ -44,3 +44,4 @@ #define KEY_VALUE_TAG 'vkCT' #define HEADER_TAG 'rhCT' #define REG_STR_TAG 'srCT' +#define DEVICE_OBJ_SECURITY_TAG 'eSeD' diff --git a/drivers/network/tcpip/tcpip/main.c b/drivers/network/tcpip/tcpip/main.c index b99a66f1092..543ffced94d 100644 --- a/drivers/network/tcpip/tcpip/main.c +++ b/drivers/network/tcpip/tcpip/main.c @@ -10,6 +10,10 @@ #include "precomp.h" +#include <ntifs.h> +#include <ndk/rtlfuncs.h> +#include <ndk/obfuncs.h> + #include <dispatch.h> #include <fileobjs.h> @@ -556,6 +560,212 @@ TiDispatch( return IRPFinish(Irp, Status); } +static +NTSTATUS TiCreateSecurityDescriptor( + _Out_ PSECURITY_DESCRIPTOR *SecurityDescriptor) +{ + NTSTATUS Status; + SECURITY_DESCRIPTOR AbsSD; + ULONG DaclSize, RelSDSize = 0; + PSECURITY_DESCRIPTOR RelSD = NULL; + PACL Dacl = NULL; + + /* Setup a SD */ + Status = RtlCreateSecurityDescriptor(&AbsSD, + SECURITY_DESCRIPTOR_REVISION); + if (!NT_SUCCESS(Status)) + { + TI_DbgPrint(MIN_TRACE, ("Failed to create the absolute SD (0x%X)\n", Status)); + goto Quit; + } + + /* Setup a DACL */ + DaclSize = sizeof(ACL) + + sizeof(ACCESS_ALLOWED_ACE) + RtlLengthSid(SeExports->SeLocalSystemSid) + + sizeof(ACCESS_ALLOWED_ACE) + RtlLengthSid(SeExports->SeAliasAdminsSid) + + sizeof(ACCESS_ALLOWED_ACE) + RtlLengthSid(SeExports->SeNetworkServiceSid); + Dacl = ExAllocatePoolWithTag(PagedPool, + DaclSize, + DEVICE_OBJ_SECURITY_TAG); + if (Dacl == NULL) + { + TI_DbgPrint(MIN_TRACE, ("Failed to allocate buffer heap for a DACL\n")); + Status = STATUS_INSUFFICIENT_RESOURCES; + goto Quit; + } + + Status = RtlCreateAcl(Dacl, + DaclSize, + ACL_REVISION); + if (!NT_SUCCESS(Status)) + { + TI_DbgPrint(MIN_TRACE, ("Failed to create a DACL (0x%X)\n", Status)); + goto Quit; + } + + /* Setup access */ + Status = RtlAddAccessAllowedAce(Dacl, + ACL_REVISION, + GENERIC_ALL, + SeExports->SeLocalSystemSid); + if (!NT_SUCCESS(Status)) + { + TI_DbgPrint(MIN_TRACE, ("Failed to add access allowed ACE for System SID (0x%X)\n", Status)); + goto Quit; + } + + Status = RtlAddAccessAllowedAce(Dacl, + ACL_REVISION, + GENERIC_ALL, + SeExports->SeAliasAdminsSid); + if (!NT_SUCCESS(Status)) + { + TI_DbgPrint(MIN_TRACE, ("Failed to add access allowed ACE for Admins SID (0x%X)\n", Status)); + goto Quit; + } + + Status = RtlAddAccessAllowedAce(Dacl, + ACL_REVISION, + GENERIC_ALL, + SeExports->SeNetworkServiceSid); + if (!NT_SUCCESS(Status)) + { + TI_DbgPrint(MIN_TRACE, ("Failed to add access allowed ACE for Network Service SID (0x%X)\n", Status)); + goto Quit; + } + + /* Assign security data to SD */ + Status = RtlSetDaclSecurityDescriptor(&AbsSD, + TRUE, + Dacl, + FALSE); + if (!NT_SUCCESS(Status)) + { + TI_DbgPrint(MIN_TRACE, ("Failed to set DACL to security descriptor (0x%X)\n", Status)); + goto Quit; + } + + Status = RtlSetGroupSecurityDescriptor(&AbsSD, + SeExports->SeLocalSystemSid, + FALSE); + if (!NT_SUCCESS(Status)) + { + TI_DbgPrint(MIN_TRACE, ("Failed to set group to security descriptor (0x%X)\n", Status)); + goto Quit; + } + + Status = RtlSetOwnerSecurityDescriptor(&AbsSD, + SeExports->SeAliasAdminsSid, + FALSE); + if (!NT_SUCCESS(Status)) + { + TI_DbgPrint(MIN_TRACE, ("Failed to set owner to security descriptor (0x%X)\n", Status)); + goto Quit; + } + + /* Get the required buffer size for the self-relative SD */ + Status = RtlAbsoluteToSelfRelativeSD(&AbsSD, + NULL, + &RelSDSize); + if (Status != STATUS_BUFFER_TOO_SMALL) + { + TI_DbgPrint(MIN_TRACE, ("Expected STATUS_BUFFER_TOO_SMALL but got something else (0x%X)\n", Status)); + goto Quit; + } + + RelSD = ExAllocatePoolWithTag(PagedPool, + RelSDSize, + DEVICE_OBJ_SECURITY_TAG); + if (RelSD == NULL) + { + TI_DbgPrint(MIN_TRACE, ("Failed to allocate buffer heap for relative SD\n")); + Status = STATUS_INSUFFICIENT_RESOURCES; + goto Quit; + } + + /* Convert it now */ + Status = RtlAbsoluteToSelfRelativeSD(&AbsSD, + RelSD, + &RelSDSize); + if (!NT_SUCCESS(Status)) + { + TI_DbgPrint(MIN_TRACE, ("Failed to convert absolute SD into a relative SD (0x%X)\n", Status)); + goto Quit; + } + + /* Give the buffer to caller */ + *SecurityDescriptor = RelSD; + +Quit: + if (!NT_SUCCESS(Status)) + { + if (RelSD != NULL) + { + ExFreePoolWithTag(RelSD, DEVICE_OBJ_SECURITY_TAG); + } + } + + if (Dacl != NULL) + { + ExFreePoolWithTag(Dacl, DEVICE_OBJ_SECURITY_TAG); + } + + return Status; +} + +static +NTSTATUS TiSetupTcpDeviceSD( + _In_ PDEVICE_OBJECT DeviceObject) +{ + NTSTATUS Status; + PSECURITY_DESCRIPTOR Sd; + SECURITY_INFORMATION Info = OWNER_SECURITY_INFORMATION | GROUP_SECURITY_INFORMATION | DACL_SECURITY_INFORMATION; + + /* Obtain a security descriptor */ + Status = TiCreateSecurityDescriptor(&Sd); + if (!NT_SUCCESS(Status)) + { + TI_DbgPrint(MIN_TRACE, ("Failed to create a security descriptor for the device object\n")); + return Status; + } + + /* Whack the new descriptor into the TCP device object */ + Status = ObSetSecurityObjectByPointer(DeviceObject, + Info, + Sd); + if (!NT_SUCCESS(Status)) + { + TI_DbgPrint(MIN_TRACE, ("Failed to set new security information to the device object\n")); + } + + ExFreePoolWithTag(Sd, DEVICE_OBJ_SECURITY_TAG); + return Status; +} + +static +NTSTATUS TiSecurityStartup( + VOID) +{ + NTSTATUS Status; + + /* Set security data for the TCP and IP device objects */ + Status = TiSetupTcpDeviceSD(TCPDeviceObject); + if (!NT_SUCCESS(Status)) + { + TI_DbgPrint(MIN_TRACE, ("Failed to set security data for TCP device object\n")); + return Status; + } + + Status = TiSetupTcpDeviceSD(IPDeviceObject); + if (!NT_SUCCESS(Status)) + { + TI_DbgPrint(MIN_TRACE, ("Failed to set security data for IP device object\n")); + return Status; + } + + return STATUS_SUCCESS; +} + VOID NTAPI TiUnload( PDRIVER_OBJECT DriverObject) @@ -761,6 +971,14 @@ DriverEntry( return Status; } + /* Initialize security */ + Status = TiSecurityStartup(); + if (!NT_SUCCESS(Status)) + { + TiUnload(DriverObject); + return Status; + } + /* Use direct I/O */ IPDeviceObject->Flags |= DO_DIRECT_IO; RawIPDeviceObject->Flags |= DO_DIRECT_IO;

1 year, 3 months

[reactos] 01/01: [NTDLL:LDR] SAL improvements and fixes

by Ratin Gao

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=be5c889cdf73080228f6f… commit be5c889cdf73080228f6f41c8bbb2fdac4dfb31c Author: Ratin Gao <ratin(a)knsoft.org> AuthorDate: Tue Oct 3 18:28:05 2023 +0800 Commit: Timo Kreuzer <timo.kreuzer(a)reactos.org> CommitDate: Wed Oct 4 12:26:18 2023 +0300 [NTDLL:LDR] SAL improvements and fixes - Convert some notations to SAL2 - "Name" parameter in LdrGetProcedureAddress/LdrpGetProcedureAddress should be optional - "DllCharacteristics" parameter in LdrGetDllHandle should be optional --- dll/ntdll/include/ntdllp.h | 14 +++++++------ dll/ntdll/ldr/ldrapi.c | 46 ++++++++++++++++++++++++------------------- dll/ntdll/ldr/ldrutils.c | 11 ++++++----- dll/win32/verifier/verifier.c | 21 +++++++++++++++++--- sdk/include/ndk/ldrfuncs.h | 4 ++-- sdk/include/ndk/umfuncs.h | 6 +++--- 6 files changed, 63 insertions(+), 39 deletions(-) diff --git a/dll/ntdll/include/ntdllp.h b/dll/ntdll/include/ntdllp.h index 418e4a394d2..42a164514b0 100644 --- a/dll/ntdll/include/ntdllp.h +++ b/dll/ntdll/include/ntdllp.h @@ -98,12 +98,14 @@ LdrpWalkImportDescriptor(IN LPWSTR DllPath OPTIONAL, /* ldrutils.c */ -NTSTATUS NTAPI -LdrpGetProcedureAddress(IN PVOID BaseAddress, - IN PANSI_STRING Name, - IN ULONG Ordinal, - OUT PVOID *ProcedureAddress, - IN BOOLEAN ExecuteInit); +NTSTATUS +NTAPI +LdrpGetProcedureAddress( + _In_ PVOID BaseAddress, + _In_opt_ _When_(Ordinal == 0, _Notnull_) PANSI_STRING Name, + _In_opt_ _When_(Name == NULL, _In_range_(>, 0)) ULONG Ordinal, + _Out_ PVOID *ProcedureAddress, + _In_ BOOLEAN ExecuteInit); PLDR_DATA_TABLE_ENTRY NTAPI LdrpAllocateDataTableEntry(IN PVOID BaseAddress); diff --git a/dll/ntdll/ldr/ldrapi.c b/dll/ntdll/ldr/ldrapi.c index de7c68d8053..f850ce6ddca 100644 --- a/dll/ntdll/ldr/ldrapi.c +++ b/dll/ntdll/ldr/ldrapi.c @@ -98,8 +98,9 @@ LdrpMakeCookie(VOID) */ NTSTATUS NTAPI -LdrUnlockLoaderLock(IN ULONG Flags, - IN ULONG Cookie OPTIONAL) +LdrUnlockLoaderLock( + _In_ ULONG Flags, + _In_opt_ ULONG Cookie) { NTSTATUS Status = STATUS_SUCCESS; @@ -170,9 +171,10 @@ LdrUnlockLoaderLock(IN ULONG Flags, */ NTSTATUS NTAPI -LdrLockLoaderLock(IN ULONG Flags, - OUT PULONG Disposition OPTIONAL, - OUT PULONG_PTR Cookie OPTIONAL) +LdrLockLoaderLock( + _In_ ULONG Flags, + _Out_opt_ PULONG Disposition, + _Out_opt_ PULONG_PTR Cookie) { NTSTATUS Status = STATUS_SUCCESS; BOOLEAN InInit = LdrpInLdrInit; @@ -440,8 +442,9 @@ LdrLoadDll(IN PWSTR SearchPath OPTIONAL, */ NTSTATUS NTAPI -LdrFindEntryForAddress(PVOID Address, - PLDR_DATA_TABLE_ENTRY *Module) +LdrFindEntryForAddress( + _In_ PVOID Address, + _Out_ PLDR_DATA_TABLE_ENTRY *Module) { PLIST_ENTRY ListHead, NextEntry; PLDR_DATA_TABLE_ENTRY LdrEntry; @@ -519,11 +522,12 @@ LdrFindEntryForAddress(PVOID Address, */ NTSTATUS NTAPI -LdrGetDllHandleEx(IN ULONG Flags, - IN PWSTR DllPath OPTIONAL, - IN PULONG DllCharacteristics OPTIONAL, - IN PUNICODE_STRING DllName, - OUT PVOID *DllHandle OPTIONAL) +LdrGetDllHandleEx( + _In_ ULONG Flags, + _In_opt_ PWSTR DllPath, + _In_opt_ PULONG DllCharacteristics, + _In_ PUNICODE_STRING DllName, + _Out_opt_ PVOID *DllHandle) { NTSTATUS Status; PLDR_DATA_TABLE_ENTRY LdrEntry; @@ -802,10 +806,11 @@ Quickie: */ NTSTATUS NTAPI -LdrGetDllHandle(IN PWSTR DllPath OPTIONAL, - IN PULONG DllCharacteristics OPTIONAL, - IN PUNICODE_STRING DllName, - OUT PVOID *DllHandle) +LdrGetDllHandle( + _In_opt_ PWSTR DllPath, + _In_opt_ PULONG DllCharacteristics, + _In_ PUNICODE_STRING DllName, + _Out_ PVOID *DllHandle) { /* Call the newer API */ return LdrGetDllHandleEx(LDR_GET_DLL_HANDLE_EX_UNCHANGED_REFCOUNT, @@ -820,10 +825,11 @@ LdrGetDllHandle(IN PWSTR DllPath OPTIONAL, */ NTSTATUS NTAPI -LdrGetProcedureAddress(IN PVOID BaseAddress, - IN PANSI_STRING Name, - IN ULONG Ordinal, - OUT PVOID *ProcedureAddress) +LdrGetProcedureAddress( + _In_ PVOID BaseAddress, + _In_opt_ _When_(Ordinal == 0, _Notnull_) PANSI_STRING Name, + _In_opt_ _When_(Name == NULL, _In_range_(>, 0)) ULONG Ordinal, + _Out_ PVOID *ProcedureAddress) { /* Call the internal routine and tell it to execute DllInit */ return LdrpGetProcedureAddress(BaseAddress, Name, Ordinal, ProcedureAddress, TRUE); diff --git a/dll/ntdll/ldr/ldrutils.c b/dll/ntdll/ldr/ldrutils.c index 37b2ecf44d2..632aa83df04 100644 --- a/dll/ntdll/ldr/ldrutils.c +++ b/dll/ntdll/ldr/ldrutils.c @@ -2249,11 +2249,12 @@ lookinhash: NTSTATUS NTAPI -LdrpGetProcedureAddress(IN PVOID BaseAddress, - IN PANSI_STRING Name, - IN ULONG Ordinal, - OUT PVOID *ProcedureAddress, - IN BOOLEAN ExecuteInit) +LdrpGetProcedureAddress( + _In_ PVOID BaseAddress, + _In_opt_ _When_(Ordinal == 0, _Notnull_) PANSI_STRING Name, + _In_opt_ _When_(Name == NULL, _In_range_(>, 0)) ULONG Ordinal, + _Out_ PVOID *ProcedureAddress, + _In_ BOOLEAN ExecuteInit) { NTSTATUS Status = STATUS_SUCCESS; UCHAR ImportBuffer[64]; diff --git a/dll/win32/verifier/verifier.c b/dll/win32/verifier/verifier.c index 5c24bd51048..e27f7846103 100644 --- a/dll/win32/verifier/verifier.c +++ b/dll/win32/verifier/verifier.c @@ -22,7 +22,13 @@ VOID NTAPI AVrfpNtdllHeapFreeCallback(PVOID AllocationBase, SIZE_T AllocationSiz // DPFLTR_VERIFIER_ID -NTSTATUS NTAPI AVrfpLdrGetProcedureAddress(IN PVOID BaseAddress, IN PANSI_STRING Name, IN ULONG Ordinal, OUT PVOID *ProcedureAddress); +NTSTATUS +NTAPI +AVrfpLdrGetProcedureAddress( + _In_ PVOID BaseAddress, + _In_opt_ _When_(Ordinal == 0, _Notnull_) PANSI_STRING Name, + _In_opt_ _When_(Name == NULL, _In_range_(>, 0)) ULONG Ordinal, + _Out_ PVOID *ProcedureAddress); static RTL_VERIFIER_THUNK_DESCRIPTOR AVrfpNtdllThunks[] = { @@ -116,9 +122,18 @@ PVOID AVrfpFindReplacementThunk(PVOID Proc) } -NTSTATUS NTAPI AVrfpLdrGetProcedureAddress(IN PVOID BaseAddress, IN PANSI_STRING Name, IN ULONG Ordinal, OUT PVOID *ProcedureAddress) +NTSTATUS NTAPI +AVrfpLdrGetProcedureAddress( + _In_ PVOID BaseAddress, + _In_opt_ _When_(Ordinal == 0, _Notnull_) PANSI_STRING Name, + _In_opt_ _When_(Name == NULL, _In_range_(>, 0)) ULONG Ordinal, + _Out_ PVOID *ProcedureAddress) { - NTSTATUS (NTAPI *oLdrGetProcedureAddress)(IN PVOID BaseAddress, IN PANSI_STRING Name, IN ULONG Ordinal, OUT PVOID *ProcedureAddress); + NTSTATUS(NTAPI *oLdrGetProcedureAddress)( + _In_ PVOID BaseAddress, + _In_opt_ _When_(Ordinal == 0, _Notnull_) PANSI_STRING Name, + _In_opt_ _When_(Name == NULL, _In_range_(>, 0)) ULONG Ordinal, + _Out_ PVOID *ProcedureAddress); NTSTATUS Status; PVOID Replacement; diff --git a/sdk/include/ndk/ldrfuncs.h b/sdk/include/ndk/ldrfuncs.h index 58859bcb351..9eb891928ca 100644 --- a/sdk/include/ndk/ldrfuncs.h +++ b/sdk/include/ndk/ldrfuncs.h @@ -89,8 +89,8 @@ NTSTATUS NTAPI LdrGetProcedureAddress( _In_ PVOID BaseAddress, - _In_ PANSI_STRING Name, - _In_ ULONG Ordinal, + _In_opt_ _When_(Ordinal == 0, _Notnull_) PANSI_STRING Name, + _In_opt_ _When_(Name == NULL, _In_range_(>, 0)) ULONG Ordinal, _Out_ PVOID *ProcedureAddress ); diff --git a/sdk/include/ndk/umfuncs.h b/sdk/include/ndk/umfuncs.h index 5a94eae4417..5fa85a1e978 100644 --- a/sdk/include/ndk/umfuncs.h +++ b/sdk/include/ndk/umfuncs.h @@ -115,7 +115,7 @@ NTSTATUS NTAPI LdrGetDllHandle( _In_opt_ PWSTR DllPath, - _In_ PULONG DllCharacteristics, + _In_opt_ PULONG DllCharacteristics, _In_ PUNICODE_STRING DllName, _Out_ PVOID *DllHandle ); @@ -140,8 +140,8 @@ NTSTATUS NTAPI LdrGetProcedureAddress( _In_ PVOID BaseAddress, - _In_ PANSI_STRING Name, - _In_ ULONG Ordinal, + _In_opt_ _When_(Ordinal == 0, _Notnull_) PANSI_STRING Name, + _In_opt_ _When_(Name == NULL, _In_range_(>, 0)) ULONG Ordinal, _Out_ PVOID *ProcedureAddress );

1 year, 3 months

[reactos] 01/01: [TASKMGR] Favor _countof(), no functional change intended (#5757)

by Joachim Henze

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=46b4b5581d1fc4c1b50cf… commit 46b4b5581d1fc4c1b50cfc0ee8b82b77be182dc6 Author: Joachim Henze <joachim.henze(a)reactos.org> AuthorDate: Tue Oct 3 21:00:10 2023 +0200 Commit: GitHub <noreply(a)github.com> CommitDate: Tue Oct 3 21:00:10 2023 +0200 [TASKMGR] Favor _countof(), no functional change intended (#5757) Taskmgr used a mixture: Sometimes _countof(), sometimes ARRAYSIZE() and sometimes it calculated the count plain by sizeof(var)/sizeof(TYPE). Harmonize everywhere to _countof() as it is the shortest solution. Fix some formatting sins, like placing comments before else-statement. Shorten the length of some very long line intentionally *without introducing additional linebreaks* ! Shorten vertical length of some functions to increase their chance to fit on the screen without scrolling. Fix wrong indentation level in TaskManagerWndProc(). *.rc: Remove superfluous and redundant comment in all langs No functional change intended. --- base/applications/taskmgr/about.c | 2 +- base/applications/taskmgr/applpage.c | 74 ++++++--------------------------- base/applications/taskmgr/applpage.h | 13 +++--- base/applications/taskmgr/column.c | 16 ++++--- base/applications/taskmgr/column.h | 2 +- base/applications/taskmgr/debug.c | 26 ++++++------ base/applications/taskmgr/graph.c | 28 +++++-------- base/applications/taskmgr/graph.h | 14 +++---- base/applications/taskmgr/lang/bg-BG.rc | 1 - base/applications/taskmgr/lang/cs-CZ.rc | 1 - base/applications/taskmgr/lang/da-DK.rc | 1 - base/applications/taskmgr/lang/de-DE.rc | 1 - base/applications/taskmgr/lang/el-GR.rc | 1 - base/applications/taskmgr/lang/en-US.rc | 1 - base/applications/taskmgr/lang/es-ES.rc | 1 - base/applications/taskmgr/lang/et-EE.rc | 1 - base/applications/taskmgr/lang/fr-FR.rc | 1 - base/applications/taskmgr/lang/he-IL.rc | 1 - base/applications/taskmgr/lang/hu-HU.rc | 1 - base/applications/taskmgr/lang/id-ID.rc | 1 - base/applications/taskmgr/lang/it-IT.rc | 1 - base/applications/taskmgr/lang/ja-JP.rc | 1 - base/applications/taskmgr/lang/ko-KR.rc | 1 - base/applications/taskmgr/lang/nl-NL.rc | 1 - base/applications/taskmgr/lang/no-NO.rc | 1 - base/applications/taskmgr/lang/pl-PL.rc | 1 - base/applications/taskmgr/lang/pt-BR.rc | 1 - base/applications/taskmgr/lang/pt-PT.rc | 1 - base/applications/taskmgr/lang/ro-RO.rc | 1 - base/applications/taskmgr/lang/ru-RU.rc | 1 - base/applications/taskmgr/lang/sk-SK.rc | 1 - base/applications/taskmgr/lang/sq-AL.rc | 1 - base/applications/taskmgr/lang/sv-SE.rc | 1 - base/applications/taskmgr/lang/tr-TR.rc | 1 - base/applications/taskmgr/lang/uk-UA.rc | 1 - base/applications/taskmgr/lang/zh-CN.rc | 1 - base/applications/taskmgr/lang/zh-HK.rc | 1 - base/applications/taskmgr/lang/zh-TW.rc | 1 - base/applications/taskmgr/perfdata.c | 10 ++--- base/applications/taskmgr/perfpage.c | 12 +++--- base/applications/taskmgr/procpage.c | 14 +++---- base/applications/taskmgr/run.c | 6 +-- base/applications/taskmgr/taskmgr.c | 38 ++++++----------- 43 files changed, 91 insertions(+), 194 deletions(-) diff --git a/base/applications/taskmgr/about.c b/base/applications/taskmgr/about.c index f97f6588550..46bc60e4d76 100644 --- a/base/applications/taskmgr/about.c +++ b/base/applications/taskmgr/about.c @@ -11,7 +11,7 @@ void OnAbout(void) { WCHAR szTaskmgr[128]; - LoadStringW(hInst, IDS_APP_TITLE, szTaskmgr, sizeof(szTaskmgr)/sizeof(WCHAR)); + LoadStringW(hInst, IDS_APP_TITLE, szTaskmgr, _countof(szTaskmgr)); ShellAboutW(hMainWnd, szTaskmgr, NULL, LoadIconW(hInst, MAKEINTRESOURCEW(IDI_TASKMANAGER))); } diff --git a/base/applications/taskmgr/applpage.c b/base/applications/taskmgr/applpage.c index 7db38c09c90..600592c10f8 100644 --- a/base/applications/taskmgr/applpage.c +++ b/base/applications/taskmgr/applpage.c @@ -1,7 +1,7 @@ /* * PROJECT: ReactOS Task Manager * LICENSE: LGPL-2.1-or-later (https://spdx.org/licenses/LGPL-2.1-or-later) - * PURPOSE: Applications Page. + * PURPOSE: Applications Page * COPYRIGHT: Copyright 1999-2001 Brian Palmer <brianp(a)reactos.org> * Copyright 2005 Klemens Friedl <frik85(a)reactos.at> * Copyright 2021 Katayama Hirofumi MZ <katayama.hirofumi.mz(a)gmail.com> @@ -97,7 +97,6 @@ ApplicationPageWndProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam) switch (message) { case WM_INITDIALOG: - /* Save the width and height */ GetClientRect(hDlg, &rc); nApplicationPageWidth = rc.right; @@ -151,7 +150,6 @@ ApplicationPageWndProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam) break; case WM_COMMAND: - /* Handle the button clicks */ switch (LOWORD(wParam)) { @@ -217,17 +215,16 @@ ApplicationPageWndProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam) if (wParam == VK_DELETE) ProcessPage_OnEndProcess(); break; - } - return 0; + return 0; } void RefreshApplicationPage(void) { #ifdef RUN_APPS_PAGE - /* Signal the event so that our refresh thread */ - /* will wake up and refresh the application page */ + /* Signal the event so that our refresh thread + * will wake up and refresh the application page */ PostThreadMessage(dwApplicationThread, WM_TIMER, 0, 0); #endif } @@ -267,11 +264,7 @@ DWORD WINAPI ApplicationPageRefreshThread(void *lpParameter) if (msg.message == WM_TIMER) { - /* - * FIXME: - * - * Should this be EnumDesktopWindows() instead? - */ + // FIXME: Should this be EnumDesktopWindows() instead? noApps = TRUE; EnumWindows(EnumWindowsProc, 0); if (noApps) @@ -450,9 +443,8 @@ void AddOrUpdateHwnd(HWND hWnd, WCHAR *szTitle, HICON hIcon, BOOL bHung) InvalidateRect(hApplicationPageListCtrl, NULL, 0); } } - /* It is not already in the list so add it */ else - { + { // It is not already in the list so add it pAPLI = (LPAPPLICATION_PAGE_LIST_ITEM)HeapAlloc(GetProcessHeap(), 0, sizeof(APPLICATION_PAGE_LIST_ITEM)); pAPLI->hWnd = hWnd; @@ -478,25 +470,16 @@ void AddOrUpdateHwnd(HWND hWnd, WCHAR *szTitle, HICON hIcon, BOOL bHung) ListView_SetItemState(hApplicationPageListCtrl, 0, LVIS_FOCUSED | LVIS_SELECTED, LVIS_FOCUSED | LVIS_SELECTED); bApplicationPageSelectionMade = TRUE; } - /* - else - { - bApplicationPageSelectionMade = FALSE; - } - */ } void ApplicationPageUpdate(void) { /* Enable or disable the "End Task" & "Switch To" buttons */ if (ListView_GetSelectedCount(hApplicationPageListCtrl)) - { EnableWindow(hApplicationPageEndTaskButton, TRUE); - } else - { EnableWindow(hApplicationPageEndTaskButton, FALSE); - } + /* Enable "Switch To" button only if only one app is selected */ EnableWindow(hApplicationPageSwitchToButton, (ListView_GetSelectedCount(hApplicationPageListCtrl) == 1)); @@ -510,9 +493,8 @@ void ApplicationPageUpdate(void) hMenu = GetMenu(hMainWnd); hWindowsMenu = GetSubMenu(hMenu, 3); - /* Only one item selected */ if (ListView_GetSelectedCount(hApplicationPageListCtrl) == 1) - { + { // Only one item selected EnableMenuItem(hWindowsMenu, ID_WINDOWS_TILEHORIZONTALLY, MF_BYCOMMAND|MF_DISABLED|MF_GRAYED); EnableMenuItem(hWindowsMenu, ID_WINDOWS_TILEVERTICALLY, MF_BYCOMMAND|MF_DISABLED|MF_GRAYED); EnableMenuItem(hWindowsMenu, ID_WINDOWS_MINIMIZE, MF_BYCOMMAND|MF_ENABLED); @@ -520,9 +502,8 @@ void ApplicationPageUpdate(void) EnableMenuItem(hWindowsMenu, ID_WINDOWS_CASCADE, MF_BYCOMMAND|MF_DISABLED|MF_GRAYED); EnableMenuItem(hWindowsMenu, ID_WINDOWS_BRINGTOFRONT, MF_BYCOMMAND|MF_ENABLED); } - /* More than one item selected */ else if (ListView_GetSelectedCount(hApplicationPageListCtrl) > 1) - { + { // More than one item selected EnableMenuItem(hWindowsMenu, ID_WINDOWS_TILEHORIZONTALLY, MF_BYCOMMAND|MF_ENABLED); EnableMenuItem(hWindowsMenu, ID_WINDOWS_TILEVERTICALLY, MF_BYCOMMAND|MF_ENABLED); EnableMenuItem(hWindowsMenu, ID_WINDOWS_MINIMIZE, MF_BYCOMMAND|MF_ENABLED); @@ -530,9 +511,8 @@ void ApplicationPageUpdate(void) EnableMenuItem(hWindowsMenu, ID_WINDOWS_CASCADE, MF_BYCOMMAND|MF_ENABLED); EnableMenuItem(hWindowsMenu, ID_WINDOWS_BRINGTOFRONT, MF_BYCOMMAND|MF_DISABLED|MF_GRAYED); } - /* No items selected */ else - { + { // No items selected EnableMenuItem(hWindowsMenu, ID_WINDOWS_TILEHORIZONTALLY, MF_BYCOMMAND|MF_DISABLED|MF_GRAYED); EnableMenuItem(hWindowsMenu, ID_WINDOWS_TILEVERTICALLY, MF_BYCOMMAND|MF_DISABLED|MF_GRAYED); EnableMenuItem(hWindowsMenu, ID_WINDOWS_MINIMIZE, MF_BYCOMMAND|MF_DISABLED|MF_GRAYED); @@ -564,52 +544,35 @@ void ApplicationPageOnNotify(WPARAM wParam, LPARAM lParam) /* Update the item text */ if (pnmdi->item.iSubItem == 0) - { wcsncpy(pnmdi->item.pszText, pAPLI->szTitle, pnmdi->item.cchTextMax); - } /* Update the item status */ else if (pnmdi->item.iSubItem == 1) { if (pAPLI->bHung) - { - LoadStringW( GetModuleHandleW(NULL), IDS_NOT_RESPONDING , szMsg, sizeof(szMsg) / sizeof(szMsg[0])); - } + LoadStringW(GetModuleHandleW(NULL), IDS_NOT_RESPONDING , szMsg, _countof(szMsg)); else - { - LoadStringW( GetModuleHandleW(NULL), IDS_RUNNING, (LPWSTR) szMsg, sizeof(szMsg) / sizeof(szMsg[0])); - } + LoadStringW(GetModuleHandleW(NULL), IDS_RUNNING, (LPWSTR) szMsg, _countof(szMsg)); wcsncpy(pnmdi->item.pszText, szMsg, pnmdi->item.cchTextMax); } break; case NM_RCLICK: - if (ListView_GetSelectedCount(hApplicationPageListCtrl) < 1) - { ApplicationPageShowContextMenu1(); - } else - { ApplicationPageShowContextMenu2(); - } - break; case NM_DBLCLK: - ApplicationPage_OnSwitchTo(); - break; case LVN_KEYDOWN: - if (((LPNMLVKEYDOWN)lParam)->wVKey == VK_DELETE) ApplicationPage_OnEndTask(); - break; - } } else if (pnmh->hwndFrom == ListView_GetHeader(hApplicationPageListCtrl)) @@ -617,27 +580,18 @@ void ApplicationPageOnNotify(WPARAM wParam, LPARAM lParam) switch (pnmh->code) { case NM_RCLICK: - if (ListView_GetSelectedCount(hApplicationPageListCtrl) < 1) - { ApplicationPageShowContextMenu1(); - } else - { ApplicationPageShowContextMenu2(); - } - break; case HDN_ITEMCLICK: - (void)ListView_SortItems(hApplicationPageListCtrl, ApplicationPageCompareFunc, 0); bSortAscending = !bSortAscending; - break; } } - } void ApplicationPageShowContextMenu1(void) @@ -929,9 +883,7 @@ void ApplicationPage_OnGotoProcess(void) i, LVIS_SELECTED | LVIS_FOCUSED, LVIS_SELECTED | LVIS_FOCUSED); - (void)ListView_EnsureVisible(hProcessPageListCtrl, - i, - FALSE); + (void)ListView_EnsureVisible(hProcessPageListCtrl, i, FALSE); } } } diff --git a/base/applications/taskmgr/applpage.h b/base/applications/taskmgr/applpage.h index e6bf69c21a1..04a57ffb0c5 100644 --- a/base/applications/taskmgr/applpage.h +++ b/base/applications/taskmgr/applpage.h @@ -1,7 +1,7 @@ /* * PROJECT: ReactOS Task Manager * LICENSE: LGPL-2.1-or-later (https://spdx.org/licenses/LGPL-2.1-or-later) - * PURPOSE: Applications Page. + * PURPOSE: Applications Page * COPYRIGHT: Copyright 1999-2001 Brian Palmer <brianp(a)reactos.org> * Copyright 2005 Klemens Friedl <frik85(a)reactos.at> * Copyright 2021 Katayama Hirofumi MZ <katayama.hirofumi.mz(a)gmail.com> @@ -9,12 +9,11 @@ #pragma once -extern HWND hApplicationPage; /* Application List Property Page */ - -extern HWND hApplicationPageListCtrl; /* Application ListCtrl Window */ -extern HWND hApplicationPageEndTaskButton; /* Application End Task button */ -extern HWND hApplicationPageSwitchToButton; /* Application Switch To button */ -extern HWND hApplicationPageNewTaskButton; /* Application New Task button */ +extern HWND hApplicationPage; /* Application List Property Page */ +extern HWND hApplicationPageListCtrl; /* Application ListCtrl Window */ +extern HWND hApplicationPageEndTaskButton; /* Application End Task button */ +extern HWND hApplicationPageSwitchToButton; /* Application Switch To button */ +extern HWND hApplicationPageNewTaskButton; /* Application New Task button */ INT_PTR CALLBACK ApplicationPageWndProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam); void RefreshApplicationPage(void); diff --git a/base/applications/taskmgr/column.c b/base/applications/taskmgr/column.c index 089e4044854..b6eec0f5ec8 100644 --- a/base/applications/taskmgr/column.c +++ b/base/applications/taskmgr/column.c @@ -42,8 +42,8 @@ const PresetColumnEntry ColumnPresets[COLUMN_NMAX] = { DECLARE_COLUMN_PRESET(COMMANDLINE, 450, FALSE) }; -static int InsertColumn(int nCol, LPCWSTR lpszColumnHeading, int nFormat, int nWidth, int nSubItem); -INT_PTR CALLBACK ColumnsDialogWndProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam); +static int InsertColumn(int nCol, LPCWSTR lpszColumnHeading, int nFormat, int nWidth, int nSubItem); +INT_PTR CALLBACK ColumnsDialogWndProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam); void AddColumns(void) { @@ -53,13 +53,13 @@ void AddColumns(void) for (n=0; n<COLUMN_NMAX; n++) { if (TaskManagerSettings.Columns[n]) { - LoadStringW(hInst, ColumnPresets[n].dwIdsName, szTemp, sizeof(szTemp)/sizeof(WCHAR)); + LoadStringW(hInst, ColumnPresets[n].dwIdsName, szTemp, _countof(szTemp)); InsertColumn(n, szTemp, LVCFMT_LEFT, TaskManagerSettings.ColumnSizeArray[n], -1); } } size = SendMessageW(hProcessPageHeaderCtrl, HDM_GETITEMCOUNT, 0, 0); - SendMessageW(hProcessPageHeaderCtrl, HDM_SETORDERARRAY, (WPARAM) size, (LPARAM) &TaskManagerSettings.ColumnOrderArray); + SendMessageW(hProcessPageHeaderCtrl, HDM_SETORDERARRAY, (WPARAM)size, (LPARAM)&TaskManagerSettings.ColumnOrderArray); UpdateColumnDataHints(); } @@ -104,7 +104,7 @@ void SaveColumnSettings(void) /* Get header order */ size = SendMessageW(hProcessPageHeaderCtrl, HDM_GETITEMCOUNT, 0, 0); - SendMessageW(hProcessPageHeaderCtrl, HDM_GETORDERARRAY, (WPARAM) size, (LPARAM) &TaskManagerSettings.ColumnOrderArray); + SendMessageW(hProcessPageHeaderCtrl, HDM_GETORDERARRAY, (WPARAM)size, (LPARAM)&TaskManagerSettings.ColumnOrderArray); /* Get visible columns */ for (i = 0; i < SendMessageW(hProcessPageHeaderCtrl, HDM_GETITEMCOUNT, 0, 0); i++) { @@ -117,7 +117,7 @@ void SaveColumnSettings(void) SendMessageW(hProcessPageHeaderCtrl, HDM_GETITEM, i, (LPARAM) &hditem); for (n = 0; n < COLUMN_NMAX; n++) { - LoadStringW(hInst, ColumnPresets[n].dwIdsName, szTemp, sizeof(szTemp)/sizeof(WCHAR)); + LoadStringW(hInst, ColumnPresets[n].dwIdsName, szTemp, _countof(szTemp)); if (_wcsicmp(text, szTemp) == 0) { TaskManagerSettings.Columns[n] = TRUE; @@ -155,7 +155,6 @@ ColumnsDialogWndProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam) switch (message) { case WM_INITDIALOG: - for (i=0; i<COLUMN_NMAX; i++) { if (TaskManagerSettings.Columns[i]) CheckDlgButton(hDlg, ColumnPresets[i].dwIdcCtrl, BST_CHECKED); @@ -163,7 +162,6 @@ ColumnsDialogWndProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam) return TRUE; case WM_COMMAND: - if (LOWORD(wParam) == IDCANCEL) { EndDialog(hDlg, LOWORD(wParam)); @@ -207,7 +205,7 @@ void UpdateColumnDataHints(void) SendMessageW(hProcessPageHeaderCtrl, HDM_GETITEM, Index, (LPARAM) &hditem); for (i=0; i<COLUMN_NMAX; i++) { - LoadStringW(hInst, ColumnPresets[i].dwIdsName, szTemp, sizeof(szTemp)/sizeof(WCHAR)); + LoadStringW(hInst, ColumnPresets[i].dwIdsName, szTemp, _countof(szTemp)); if (_wcsicmp(text, szTemp) == 0) ColumnDataHints[Index] = i; } diff --git a/base/applications/taskmgr/column.h b/base/applications/taskmgr/column.h index 615067104ad..4ccdf36d593 100644 --- a/base/applications/taskmgr/column.h +++ b/base/applications/taskmgr/column.h @@ -63,7 +63,7 @@ typedef struct { } PresetColumnEntry; -extern UINT ColumnDataHints[COLUMN_NMAX]; +extern UINT ColumnDataHints[COLUMN_NMAX]; extern const PresetColumnEntry ColumnPresets[COLUMN_NMAX]; #define Column_ImageName Columns[COLUMN_IMAGENAME] diff --git a/base/applications/taskmgr/debug.c b/base/applications/taskmgr/debug.c index 7e3e11f283e..678597a350c 100644 --- a/base/applications/taskmgr/debug.c +++ b/base/applications/taskmgr/debug.c @@ -1,7 +1,7 @@ /* * PROJECT: ReactOS Task Manager * LICENSE: LGPL-2.1-or-later (https://spdx.org/licenses/LGPL-2.1-or-later) - * PURPOSE: Process Debugging. + * PURPOSE: Process Debugging * COPYRIGHT: Copyright 1999-2001 Brian Palmer <brianp(a)reactos.org> * Copyright 2005 Klemens Friedl <frik85(a)reactos.at> */ @@ -27,21 +27,21 @@ void ProcessPage_OnDebug(void) if (dwProcessId == 0) return; - LoadStringW(hInst, IDS_MSG_WARNINGDEBUG, szTemp, ARRAYSIZE(szTemp)); - LoadStringW(hInst, IDS_MSG_TASKMGRWARNING, szTempA, ARRAYSIZE(szTempA)); + LoadStringW(hInst, IDS_MSG_WARNINGDEBUG, szTemp, _countof(szTemp)); + LoadStringW(hInst, IDS_MSG_TASKMGRWARNING, szTempA, _countof(szTempA)); if (MessageBoxW(hMainWnd, szTemp, szTempA, MB_YESNO | MB_ICONWARNING) != IDYES) { - GetLastErrorText(strErrorText, ARRAYSIZE(strErrorText)); - LoadStringW(hInst, IDS_MSG_UNABLEDEBUGPROCESS, szTemp, ARRAYSIZE(szTemp)); + GetLastErrorText(strErrorText, _countof(strErrorText)); + LoadStringW(hInst, IDS_MSG_UNABLEDEBUGPROCESS, szTemp, _countof(szTemp)); MessageBoxW(hMainWnd, strErrorText, szTemp, MB_OK | MB_ICONSTOP); return; } if (RegOpenKeyExW(HKEY_LOCAL_MACHINE, L"Software\\Microsoft\\Windows NT\\CurrentVersion\\AeDebug", 0, KEY_QUERY_VALUE, &hKey) != ERROR_SUCCESS) { - GetLastErrorText(strErrorText, ARRAYSIZE(strErrorText)); - LoadStringW(hInst, IDS_MSG_UNABLEDEBUGPROCESS, szTemp, ARRAYSIZE(szTemp)); + GetLastErrorText(strErrorText, _countof(strErrorText)); + LoadStringW(hInst, IDS_MSG_UNABLEDEBUGPROCESS, szTemp, _countof(szTemp)); MessageBoxW(hMainWnd, strErrorText, szTemp, MB_OK | MB_ICONSTOP); return; } @@ -49,8 +49,8 @@ void ProcessPage_OnDebug(void) dwDebuggerSize = sizeof(strDebugger); if (RegQueryValueExW(hKey, L"Debugger", NULL, NULL, (LPBYTE)strDebugger, &dwDebuggerSize) != ERROR_SUCCESS) { - GetLastErrorText(strErrorText, ARRAYSIZE(strErrorText)); - LoadStringW(hInst, IDS_MSG_UNABLEDEBUGPROCESS, szTemp, ARRAYSIZE(szTemp)); + GetLastErrorText(strErrorText, _countof(strErrorText)); + LoadStringW(hInst, IDS_MSG_UNABLEDEBUGPROCESS, szTemp, _countof(szTemp)); MessageBoxW(hMainWnd, strErrorText, szTemp, MB_OK | MB_ICONSTOP); RegCloseKey(hKey); return; @@ -61,8 +61,8 @@ void ProcessPage_OnDebug(void) hDebugEvent = CreateEventW(NULL, FALSE, FALSE, NULL); if (!hDebugEvent) { - GetLastErrorText(strErrorText, ARRAYSIZE(strErrorText)); - LoadStringW(hInst, IDS_MSG_UNABLEDEBUGPROCESS, szTemp, ARRAYSIZE(szTemp)); + GetLastErrorText(strErrorText, _countof(strErrorText)); + LoadStringW(hInst, IDS_MSG_UNABLEDEBUGPROCESS, szTemp, _countof(szTemp)); MessageBoxW(hMainWnd, strErrorText, szTemp, MB_OK | MB_ICONSTOP); return; } @@ -74,8 +74,8 @@ void ProcessPage_OnDebug(void) si.cb = sizeof(si); if (!CreateProcessW(NULL, strDebugPath, NULL, NULL, FALSE, 0, NULL, NULL, &si, &pi)) { - GetLastErrorText(strErrorText, ARRAYSIZE(strErrorText)); - LoadStringW(hInst, IDS_MSG_UNABLEDEBUGPROCESS, szTemp, ARRAYSIZE(szTemp)); + GetLastErrorText(strErrorText, _countof(strErrorText)); + LoadStringW(hInst, IDS_MSG_UNABLEDEBUGPROCESS, szTemp, _countof(szTemp)); MessageBoxW(hMainWnd, strErrorText, szTemp, MB_OK | MB_ICONSTOP); } else diff --git a/base/applications/taskmgr/graph.c b/base/applications/taskmgr/graph.c index aea347c47b6..f431bce46c9 100644 --- a/base/applications/taskmgr/graph.c +++ b/base/applications/taskmgr/graph.c @@ -28,7 +28,7 @@ Graph_WndProc(HWND hWnd, UINT message, WPARAM wParam, LPARAM lParam) return TRUE; /* - * Filter out mouse & keyboard messages + * Filter out mouse & keyboard messages */ /* case WM_APPCOMMAND: */ case WM_CAPTURECHANGED: @@ -84,7 +84,6 @@ Graph_WndProc(HWND hWnd, UINT message, WPARAM wParam, LPARAM lParam) return 0; case WM_PAINT: - hdc = BeginPaint(hWnd, &ps); WindowId = GetWindowLongPtrW(hWnd, GWLP_ID); @@ -103,13 +102,11 @@ Graph_WndProc(HWND hWnd, UINT message, WPARAM wParam, LPARAM lParam) } EndPaint(hWnd, &ps); - return 0; - } /* - * We pass on all non-handled messages + * Pass on all non-handled messages */ return CallWindowProcW(OldGraphWndProc, hWnd, message, wParam, lParam); } @@ -163,8 +160,7 @@ void Graph_DrawCpuUsageGraph(HDC hDC, HWND hWnd) SetTextColor(hDC, crPrevForeground); /* - * Now we have to draw the graph - * So first find out how many bars we can fit + * Draw the graph. So first find out how many bars we can fit */ nBars = ((rcClient.bottom - rcClient.top) - 25) / 3; nBarsUsed = (nBars * CpuUsage) / 100; @@ -185,7 +181,7 @@ void Graph_DrawCpuUsageGraph(HDC hDC, HWND hWnd) } /* - * Now draw the bar graph + * Draw the bar graph */ rcBarLeft.left = ((rcClient.right - rcClient.left) - 33) / 2; rcBarLeft.right = rcBarLeft.left + 16; @@ -266,7 +262,6 @@ void Graph_DrawCpuUsageGraph(HDC hDC, HWND hWnd) for (i=0; i<nBarsUsedKernel; i++) { - FillSolidRect(hDC, &rcBarLeft, RED); FillSolidRect(hDC, &rcBarRight, RED); @@ -275,7 +270,6 @@ void Graph_DrawCpuUsageGraph(HDC hDC, HWND hWnd) rcBarRight.top -=3; rcBarRight.bottom -=3; - } SelectObject(hDC, hOldFont); @@ -331,8 +325,7 @@ void Graph_DrawMemUsageGraph(HDC hDC, HWND hWnd) SetTextColor(hDC, crPrevForeground); /* - * Now we have to draw the graph - * So first find out how many bars we can fit + * Draw the graph. So first find out how many bars we can fit */ nBars = ((rcClient.bottom - rcClient.top) - 25) / 3; if (CommitChargeLimit) @@ -346,7 +339,7 @@ void Graph_DrawMemUsageGraph(HDC hDC, HWND hWnd) if (nBarsFree > nBars) nBarsFree = nBars; /* - * Now draw the bar graph + * Draw the bar graph */ rcBarLeft.left = ((rcClient.right - rcClient.left) - 33) / 2; rcBarLeft.right = rcBarLeft.left + 16; @@ -414,17 +407,16 @@ void Graph_DrawMemUsageHistoryGraph(HDC hDC, HWND hWnd) //CommitChargeLimit = (ULONGLONG)PerfDataGetCommitChargeLimitK(); /* - * Draw the graph background - * - * Draw the horizontal bars + * Draw the graph background and horizontal bars */ for (i=0; i<rcClient.bottom; i++) { if ((i % 11) == 0) { - /* FillSolidRect2(hDC, 0, i, rcClient.right, 1, DARK_GREEN); */ + //FillSolidRect2(hDC, 0, i, rcClient.right, 1, DARK_GREEN); } } + /* * Draw the vertical bars */ @@ -432,7 +424,7 @@ void Graph_DrawMemUsageHistoryGraph(HDC hDC, HWND hWnd) { if ((i % 11) == 0) { - /* FillSolidRect2(hDC, i - offset, 0, 1, rcClient.bottom, DARK_GREEN); */ + //FillSolidRect2(hDC, i - offset, 0, 1, rcClient.bottom, DARK_GREEN); } } diff --git a/base/applications/taskmgr/graph.h b/base/applications/taskmgr/graph.h index 27682b41c05..d2ada309b01 100644 --- a/base/applications/taskmgr/graph.h +++ b/base/applications/taskmgr/graph.h @@ -1,7 +1,7 @@ /* * PROJECT: ReactOS Task Manager * LICENSE: LGPL-2.1-or-later (https://spdx.org/licenses/LGPL-2.1-or-later) - * PURPOSE: Performance Graph Meters. + * PURPOSE: Performance Graph Meters * COPYRIGHT: Copyright 1999-2001 Brian Palmer <brianp(a)reactos.org> */ @@ -12,14 +12,14 @@ extern "C" { #endif -#define BRIGHT_GREEN RGB(0, 255, 0) -#define MEDIUM_GREEN RGB(0, 190, 0) -#define DARK_GREEN RGB(0, 130, 0) -#define RED RGB(255, 0, 0) +#define BRIGHT_GREEN RGB(0, 255, 0) +#define MEDIUM_GREEN RGB(0, 190, 0) +#define DARK_GREEN RGB(0, 130, 0) +#define RED RGB(255, 0, 0) -extern WNDPROC OldGraphWndProc; +extern WNDPROC OldGraphWndProc; -INT_PTR CALLBACK Graph_WndProc(HWND hWnd, UINT message, WPARAM wParam, LPARAM lParam); +INT_PTR CALLBACK Graph_WndProc(HWND hWnd, UINT message, WPARAM wParam, LPARAM lParam); #ifdef __cplusplus diff --git a/base/applications/taskmgr/lang/bg-BG.rc b/base/applications/taskmgr/lang/bg-BG.rc index 7f523d3833c..e8505c05b0e 100644 --- a/base/applications/taskmgr/lang/bg-BG.rc +++ b/base/applications/taskmgr/lang/bg-BG.rc @@ -177,7 +177,6 @@ BEGIN PUSHBUTTON "&Прекратяване на задачата", IDC_ENDPROCESS, 144, 203, 100, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/cs-CZ.rc b/base/applications/taskmgr/lang/cs-CZ.rc index 423155a957b..f15c3b3b7f5 100644 --- a/base/applications/taskmgr/lang/cs-CZ.rc +++ b/base/applications/taskmgr/lang/cs-CZ.rc @@ -177,7 +177,6 @@ BEGIN PUSHBUTTON "&Ukončit proces", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/da-DK.rc b/base/applications/taskmgr/lang/da-DK.rc index 27ea5d0f36c..42162b6c048 100644 --- a/base/applications/taskmgr/lang/da-DK.rc +++ b/base/applications/taskmgr/lang/da-DK.rc @@ -177,7 +177,6 @@ BEGIN PUSHBUTTON "&Afslut Proces", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/de-DE.rc b/base/applications/taskmgr/lang/de-DE.rc index aea8376cf63..519d3097edb 100644 --- a/base/applications/taskmgr/lang/de-DE.rc +++ b/base/applications/taskmgr/lang/de-DE.rc @@ -179,7 +179,6 @@ BEGIN PUSHBUTTON "&Prozess beenden", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/el-GR.rc b/base/applications/taskmgr/lang/el-GR.rc index 616f0de9115..f5a3a34598b 100644 --- a/base/applications/taskmgr/lang/el-GR.rc +++ b/base/applications/taskmgr/lang/el-GR.rc @@ -179,7 +179,6 @@ BEGIN PUSHBUTTON "&End Process", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/en-US.rc b/base/applications/taskmgr/lang/en-US.rc index 90b73950e6a..d6d45afc0e6 100644 --- a/base/applications/taskmgr/lang/en-US.rc +++ b/base/applications/taskmgr/lang/en-US.rc @@ -175,7 +175,6 @@ BEGIN PUSHBUTTON "&End Process", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/es-ES.rc b/base/applications/taskmgr/lang/es-ES.rc index 9a99ddebc89..6a0f4780a53 100644 --- a/base/applications/taskmgr/lang/es-ES.rc +++ b/base/applications/taskmgr/lang/es-ES.rc @@ -179,7 +179,6 @@ BEGIN PUSHBUTTON "&Finalizar proceso", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/et-EE.rc b/base/applications/taskmgr/lang/et-EE.rc index 4aba1b254f9..ed6eef05a74 100644 --- a/base/applications/taskmgr/lang/et-EE.rc +++ b/base/applications/taskmgr/lang/et-EE.rc @@ -181,7 +181,6 @@ BEGIN PUSHBUTTON "&Lõpeta protsess", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/fr-FR.rc b/base/applications/taskmgr/lang/fr-FR.rc index 204caaef666..d86362f1fec 100644 --- a/base/applications/taskmgr/lang/fr-FR.rc +++ b/base/applications/taskmgr/lang/fr-FR.rc @@ -179,7 +179,6 @@ BEGIN PUSHBUTTON "&Terminer le processus", IDC_ENDPROCESS, 165, 189, 75, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/he-IL.rc b/base/applications/taskmgr/lang/he-IL.rc index c9855c5ff30..dea754e3d91 100644 --- a/base/applications/taskmgr/lang/he-IL.rc +++ b/base/applications/taskmgr/lang/he-IL.rc @@ -179,7 +179,6 @@ BEGIN PUSHBUTTON "&סיים תהליך", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/hu-HU.rc b/base/applications/taskmgr/lang/hu-HU.rc index 51fa95242a6..99a18e3eba4 100644 --- a/base/applications/taskmgr/lang/hu-HU.rc +++ b/base/applications/taskmgr/lang/hu-HU.rc @@ -179,7 +179,6 @@ BEGIN PUSHBUTTON "&Folyamat befejezése", IDC_ENDPROCESS, 165, 189, 75, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/id-ID.rc b/base/applications/taskmgr/lang/id-ID.rc index 28427216fa3..2052bdd0891 100644 --- a/base/applications/taskmgr/lang/id-ID.rc +++ b/base/applications/taskmgr/lang/id-ID.rc @@ -179,7 +179,6 @@ BEGIN PUSHBUTTON "&Akhiri Proses", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/it-IT.rc b/base/applications/taskmgr/lang/it-IT.rc index ff44c4e27a8..2785ef8715d 100644 --- a/base/applications/taskmgr/lang/it-IT.rc +++ b/base/applications/taskmgr/lang/it-IT.rc @@ -177,7 +177,6 @@ BEGIN PUSHBUTTON "&Termina Processo", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/ja-JP.rc b/base/applications/taskmgr/lang/ja-JP.rc index bec1d437eaf..4565f6cc044 100644 --- a/base/applications/taskmgr/lang/ja-JP.rc +++ b/base/applications/taskmgr/lang/ja-JP.rc @@ -177,7 +177,6 @@ BEGIN PUSHBUTTON "プロセスの終了(&E)", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 9, "MS UI Gothic" diff --git a/base/applications/taskmgr/lang/ko-KR.rc b/base/applications/taskmgr/lang/ko-KR.rc index 1dc9dcb30b3..d3dd75b0c40 100644 --- a/base/applications/taskmgr/lang/ko-KR.rc +++ b/base/applications/taskmgr/lang/ko-KR.rc @@ -179,7 +179,6 @@ BEGIN PUSHBUTTON "작업 끝내기(&E)", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 9, "굴림" diff --git a/base/applications/taskmgr/lang/nl-NL.rc b/base/applications/taskmgr/lang/nl-NL.rc index 64f70a7d0df..06702663f7c 100644 --- a/base/applications/taskmgr/lang/nl-NL.rc +++ b/base/applications/taskmgr/lang/nl-NL.rc @@ -177,7 +177,6 @@ BEGIN PUSHBUTTON "&Proces beëindigen", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/no-NO.rc b/base/applications/taskmgr/lang/no-NO.rc index 86063df9bbf..7b1a2715f53 100644 --- a/base/applications/taskmgr/lang/no-NO.rc +++ b/base/applications/taskmgr/lang/no-NO.rc @@ -177,7 +177,6 @@ BEGIN PUSHBUTTON "&Avslutt prosess", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/pl-PL.rc b/base/applications/taskmgr/lang/pl-PL.rc index 160755b4e75..ab60fa53be0 100644 --- a/base/applications/taskmgr/lang/pl-PL.rc +++ b/base/applications/taskmgr/lang/pl-PL.rc @@ -184,7 +184,6 @@ BEGIN PUSHBUTTON "&Zakończ proces", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/pt-BR.rc b/base/applications/taskmgr/lang/pt-BR.rc index f2581fe758d..a63fd2319d1 100644 --- a/base/applications/taskmgr/lang/pt-BR.rc +++ b/base/applications/taskmgr/lang/pt-BR.rc @@ -177,7 +177,6 @@ BEGIN PUSHBUTTON "&Finalizar processo", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/pt-PT.rc b/base/applications/taskmgr/lang/pt-PT.rc index 1d6568e2d6d..0fe5288defd 100644 --- a/base/applications/taskmgr/lang/pt-PT.rc +++ b/base/applications/taskmgr/lang/pt-PT.rc @@ -179,7 +179,6 @@ BEGIN PUSHBUTTON "&Terminar processo", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/ro-RO.rc b/base/applications/taskmgr/lang/ro-RO.rc index 1b0d7df8a74..9cba5a635f4 100644 --- a/base/applications/taskmgr/lang/ro-RO.rc +++ b/base/applications/taskmgr/lang/ro-RO.rc @@ -182,7 +182,6 @@ BEGIN PUSHBUTTON "Opr&ește procesul", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/ru-RU.rc b/base/applications/taskmgr/lang/ru-RU.rc index da28e3bc231..989dec8a6c1 100644 --- a/base/applications/taskmgr/lang/ru-RU.rc +++ b/base/applications/taskmgr/lang/ru-RU.rc @@ -179,7 +179,6 @@ BEGIN PUSHBUTTON "&Завершить процесс", IDC_ENDPROCESS, 167, 189, 74, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/sk-SK.rc b/base/applications/taskmgr/lang/sk-SK.rc index 45567224455..75982e1f7f4 100644 --- a/base/applications/taskmgr/lang/sk-SK.rc +++ b/base/applications/taskmgr/lang/sk-SK.rc @@ -179,7 +179,6 @@ BEGIN PUSHBUTTON "&Ukončiť proces", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/sq-AL.rc b/base/applications/taskmgr/lang/sq-AL.rc index 06c4254a6e2..d0753d2889b 100644 --- a/base/applications/taskmgr/lang/sq-AL.rc +++ b/base/applications/taskmgr/lang/sq-AL.rc @@ -178,7 +178,6 @@ BEGIN PUSHBUTTON "Mbyll Procesin", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/sv-SE.rc b/base/applications/taskmgr/lang/sv-SE.rc index 5186e05c3ff..9e5315c58c1 100644 --- a/base/applications/taskmgr/lang/sv-SE.rc +++ b/base/applications/taskmgr/lang/sv-SE.rc @@ -179,7 +179,6 @@ BEGIN PUSHBUTTON "&Avsluta process", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/tr-TR.rc b/base/applications/taskmgr/lang/tr-TR.rc index 27a1272cd9e..201bc7c4498 100644 --- a/base/applications/taskmgr/lang/tr-TR.rc +++ b/base/applications/taskmgr/lang/tr-TR.rc @@ -177,7 +177,6 @@ BEGIN PUSHBUTTON "&İşlemi Sonlandır", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/uk-UA.rc b/base/applications/taskmgr/lang/uk-UA.rc index b7d630af65b..59372ae4607 100644 --- a/base/applications/taskmgr/lang/uk-UA.rc +++ b/base/applications/taskmgr/lang/uk-UA.rc @@ -177,7 +177,6 @@ BEGIN PUSHBUTTON "Зн&яти процес", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 8, "MS Shell Dlg" diff --git a/base/applications/taskmgr/lang/zh-CN.rc b/base/applications/taskmgr/lang/zh-CN.rc index 5afc17c975f..d81a7ce540f 100644 --- a/base/applications/taskmgr/lang/zh-CN.rc +++ b/base/applications/taskmgr/lang/zh-CN.rc @@ -184,7 +184,6 @@ BEGIN PUSHBUTTON "结束进程(&E)", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 9, "宋体" diff --git a/base/applications/taskmgr/lang/zh-HK.rc b/base/applications/taskmgr/lang/zh-HK.rc index d6abcc2aea5..e50b521c256 100644 --- a/base/applications/taskmgr/lang/zh-HK.rc +++ b/base/applications/taskmgr/lang/zh-HK.rc @@ -185,7 +185,6 @@ BEGIN PUSHBUTTON "結束處理程序(&E)", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 9, "新細明體" diff --git a/base/applications/taskmgr/lang/zh-TW.rc b/base/applications/taskmgr/lang/zh-TW.rc index c83bfea34ee..0c10bb3afd7 100644 --- a/base/applications/taskmgr/lang/zh-TW.rc +++ b/base/applications/taskmgr/lang/zh-TW.rc @@ -185,7 +185,6 @@ BEGIN PUSHBUTTON "結束處理程序(&E)", IDC_ENDPROCESS, 171, 189, 69, 14 END -/* IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 */ IDD_PERFORMANCE_PAGE DIALOGEX 0, 0, 247, 210 STYLE DS_SHELLFONT | DS_CONTROL | WS_CHILD | WS_CLIPCHILDREN FONT 9, "新細明體" diff --git a/base/applications/taskmgr/perfdata.c b/base/applications/taskmgr/perfdata.c index 0126285c98b..7f0869a5752 100644 --- a/base/applications/taskmgr/perfdata.c +++ b/base/applications/taskmgr/perfdata.c @@ -1,7 +1,7 @@ /* * PROJECT: ReactOS Task Manager * LICENSE: LGPL-2.1-or-later (https://spdx.org/licenses/LGPL-2.1-or-later) - * PURPOSE: Performance Counters. + * PURPOSE: Performance Counters * COPYRIGHT: Copyright 1999-2001 Brian Palmer <brianp(a)reactos.org> * Copyright 2014 Ismael Ferreras Morezuelas <swyterzone+ros(a)gmail.com> */ @@ -100,7 +100,7 @@ void PerfDataUninitialize(void) static void SidToUserName(PSID Sid, LPWSTR szBuffer, DWORD BufferSize) { static WCHAR szDomainNameUnused[255]; - DWORD DomainNameLen = sizeof(szDomainNameUnused) / sizeof(szDomainNameUnused[0]); + DWORD DomainNameLen = _countof(szDomainNameUnused); SID_NAME_USE Use; if (Sid != NULL) @@ -153,8 +153,6 @@ CachedGetUserFromSid( pEntry->List.Blink = SidToUserNameHead.Blink; SidToUserNameHead.Blink->Flink = &pEntry->List; SidToUserNameHead.Blink = &pEntry->List; - - return; } void PerfDataRefresh(void) @@ -324,7 +322,7 @@ void PerfDataRefresh(void) wcsncpy(pPerfData[Idx].ImageName, pSPI->ImageName.Buffer, len); } else { LoadStringW(hInst, IDS_IDLE_PROCESS, pPerfData[Idx].ImageName, - sizeof(pPerfData[Idx].ImageName) / sizeof(pPerfData[Idx].ImageName[0])); + _countof(pPerfData[Idx].ImageName)); } pPerfData[Idx].ProcessId = pSPI->UniqueProcessId; @@ -402,7 +400,7 @@ ClearInfo: ZeroMemory(&pPerfData[Idx].IOCounters, sizeof(IO_COUNTERS)); } - cwcUserName = sizeof(pPerfData[0].UserName) / sizeof(pPerfData[0].UserName[0]); + cwcUserName = _countof(pPerfData[0].UserName); CachedGetUserFromSid(ProcessUser, pPerfData[Idx].UserName, &cwcUserName); if (ProcessSD != NULL) diff --git a/base/applications/taskmgr/perfpage.c b/base/applications/taskmgr/perfpage.c index c9abb74cd15..005bc6e2e40 100644 --- a/base/applications/taskmgr/perfpage.c +++ b/base/applications/taskmgr/perfpage.c @@ -1,7 +1,7 @@ /* * PROJECT: ReactOS Task Manager * LICENSE: LGPL-2.1-or-later (https://spdx.org/licenses/LGPL-2.1-or-later) - * PURPOSE: Performance Page. + * PURPOSE: Performance Page * COPYRIGHT: Copyright 1999-2001 Brian Palmer <brianp(a)reactos.org> */ @@ -320,9 +320,9 @@ DWORD WINAPI PerformancePageRefreshThread(PVOID Parameter) WCHAR Text[260]; WCHAR szMemUsage[256], szCpuUsage[256], szProcesses[256]; - LoadStringW(hInst, IDS_STATUS_CPUUSAGE, szCpuUsage, ARRAYSIZE(szCpuUsage)); - LoadStringW(hInst, IDS_STATUS_MEMUSAGE, szMemUsage, ARRAYSIZE(szMemUsage)); - LoadStringW(hInst, IDS_STATUS_PROCESSES, szProcesses, ARRAYSIZE(szProcesses)); + LoadStringW(hInst, IDS_STATUS_CPUUSAGE, szCpuUsage, _countof(szCpuUsage)); + LoadStringW(hInst, IDS_STATUS_MEMUSAGE, szMemUsage, _countof(szMemUsage)); + LoadStringW(hInst, IDS_STATUS_PROCESSES, szProcesses, _countof(szProcesses)); while (1) { @@ -355,11 +355,11 @@ DWORD WINAPI PerformancePageRefreshThread(PVOID Parameter) StrFormatByteSizeW(CommitChargeTotal * 1024, szChargeTotalFormat, - ARRAYSIZE(szChargeTotalFormat)); + _countof(szChargeTotalFormat)); StrFormatByteSizeW(CommitChargeLimit * 1024, szChargeLimitFormat, - ARRAYSIZE(szChargeLimitFormat)); + _countof(szChargeLimitFormat)); if (!bTrackMenu) { diff --git a/base/applications/taskmgr/procpage.c b/base/applications/taskmgr/procpage.c index e3e791b6182..27b34947153 100644 --- a/base/applications/taskmgr/procpage.c +++ b/base/applications/taskmgr/procpage.c @@ -1,7 +1,7 @@ /* * PROJECT: ReactOS Task Manager * LICENSE: LGPL-2.1-or-later (https://spdx.org/licenses/LGPL-2.1-or-later) - * PURPOSE: Processes Page. + * PURPOSE: Processes Page * COPYRIGHT: Copyright 1999-2001 Brian Palmer <brianp(a)reactos.org> * Copyright 2009 Maxime Vernier <maxime.vernier(a)gmail.com> * Copyright 2022 Thamatip Chitpong <tangaming123456(a)outlook.com> @@ -797,8 +797,8 @@ int CALLBACK ProcessPageCompareFunc(LPARAM lParam1, LPARAM lParam2, LPARAM lPara if (TaskManagerSettings.SortColumn == COLUMN_IMAGENAME) { - PerfDataGetImageName(IndexParam1, text1, sizeof (text1) / sizeof (*text1)); - PerfDataGetImageName(IndexParam2, text2, sizeof (text2) / sizeof (*text2)); + PerfDataGetImageName(IndexParam1, text1, _countof(text1)); + PerfDataGetImageName(IndexParam2, text2, _countof(text2)); ret = _wcsicmp(text1, text2); } else if (TaskManagerSettings.SortColumn == COLUMN_PID) @@ -809,14 +809,14 @@ int CALLBACK ProcessPageCompareFunc(LPARAM lParam1, LPARAM lParam2, LPARAM lPara } else if (TaskManagerSettings.SortColumn == COLUMN_USERNAME) { - PerfDataGetUserName(IndexParam1, text1, sizeof (text1) / sizeof (*text1)); - PerfDataGetUserName(IndexParam2, text2, sizeof (text2) / sizeof (*text2)); + PerfDataGetUserName(IndexParam1, text1, _countof(text1)); + PerfDataGetUserName(IndexParam2, text2, _countof(text2)); ret = _wcsicmp(text1, text2); } else if (TaskManagerSettings.SortColumn == COLUMN_COMMANDLINE) { - PerfDataGetCommandLine(IndexParam1, text1, sizeof (text1) / sizeof (*text1)); - PerfDataGetCommandLine(IndexParam2, text2, sizeof (text2) / sizeof (*text2)); + PerfDataGetCommandLine(IndexParam1, text1, _countof(text1)); + PerfDataGetCommandLine(IndexParam2, text2, _countof(text2)); ret = _wcsicmp(text1, text2); } else if (TaskManagerSettings.SortColumn == COLUMN_SESSIONID) diff --git a/base/applications/taskmgr/run.c b/base/applications/taskmgr/run.c index 3e210f04415..621858a1e11 100644 --- a/base/applications/taskmgr/run.c +++ b/base/applications/taskmgr/run.c @@ -1,7 +1,7 @@ /* * PROJECT: ReactOS Task Manager * LICENSE: LGPL-2.1-or-later (https://spdx.org/licenses/LGPL-2.1-or-later) - * PURPOSE: Run Task. + * PURPOSE: Run Task * COPYRIGHT: Copyright 1999-2001 Brian Palmer <brianp(a)reactos.org> * Copyright 2005 Klemens Friedl <frik85(a)reactos.at> */ @@ -16,8 +16,8 @@ void TaskManager_OnFileNew(void) WCHAR szText[256]; /* Load language strings from resource file */ - LoadStringW(hInst, IDS_CREATENEWTASK, szTitle, sizeof(szTitle) / sizeof(szTitle[0])); - LoadStringW(hInst, IDS_CREATENEWTASK_DESC, szText, sizeof(szText) / sizeof(szText[0])); + LoadStringW(hInst, IDS_CREATENEWTASK, szTitle, _countof(szTitle)); + LoadStringW(hInst, IDS_CREATENEWTASK_DESC, szText, _countof(szText)); hShell32 = LoadLibraryW(L"SHELL32.DLL"); RunFileDlg = (RUNFILEDLG)(FARPROC)GetProcAddress(hShell32, (LPCSTR)61); diff --git a/base/applications/taskmgr/taskmgr.c b/base/applications/taskmgr/taskmgr.c index bf24eef8b39..9dedb5e1093 100644 --- a/base/applications/taskmgr/taskmgr.c +++ b/base/applications/taskmgr/taskmgr.c @@ -1,7 +1,7 @@ /* * PROJECT: ReactOS Task Manager * LICENSE: LGPL-2.1-or-later (https://spdx.org/licenses/LGPL-2.1-or-later) - * PURPOSE: Application Entry-point. + * PURPOSE: Application Entry-point * COPYRIGHT: Copyright 1999-2001 Brian Palmer <brianp(a)reactos.org> * Copyright 2005 Klemens Friedl <frik85(a)reactos.at> */ @@ -110,7 +110,7 @@ int APIENTRY wWinMain(HINSTANCE hInstance, HWND hTaskMgr; TCHAR szTaskmgr[128]; - LoadString(hInst, IDS_APP_TITLE, szTaskmgr, sizeof(szTaskmgr)/sizeof(TCHAR)); + LoadString(hInst, IDS_APP_TITLE, szTaskmgr, _countof(szTaskmgr)); hTaskMgr = FindWindow(NULL, szTaskmgr); if (hTaskMgr != NULL) @@ -139,10 +139,10 @@ int APIENTRY wWinMain(HINSTANCE hInstance, * so that we can debug processes */ - /* Get a token for this process. */ + /* Get a token for this process. */ if (OpenProcessToken(GetCurrentProcess(), TOKEN_ADJUST_PRIVILEGES | TOKEN_QUERY, &hToken)) { - /* Get the LUID for the debug privilege. */ + /* Get the LUID for the debug privilege. */ if (LookupPrivilegeValueW(NULL, SE_DEBUG_NAME, &tkp.Privileges[0].Luid)) { tkp.PrivilegeCount = 1; /* one privilege to set */ @@ -159,9 +159,7 @@ int APIENTRY wWinMain(HINSTANCE hInstance, /* Initialize perf data */ if (!PerfDataInitialize()) - { return -1; - } /* * Set our shutdown parameters: we want to shutdown the very last, @@ -371,21 +369,14 @@ TaskManagerWndProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam) hPopupMenu = GetSubMenu(hMenu, 0); if(IsWindowVisible(hMainWnd)) - { - DeleteMenu(hPopupMenu, ID_RESTORE, MF_BYCOMMAND); - } + DeleteMenu(hPopupMenu, ID_RESTORE, MF_BYCOMMAND); else - { - SetMenuDefaultItem(hPopupMenu, ID_RESTORE, FALSE); - } + SetMenuDefaultItem(hPopupMenu, ID_RESTORE, FALSE); if(OnTop) - { - CheckMenuItem(hPopupMenu, ID_OPTIONS_ALWAYSONTOP, MF_BYCOMMAND | MF_CHECKED); - } else - { - CheckMenuItem(hPopupMenu, ID_OPTIONS_ALWAYSONTOP, MF_BYCOMMAND | MF_UNCHECKED); - } + CheckMenuItem(hPopupMenu, ID_OPTIONS_ALWAYSONTOP, MF_BYCOMMAND | MF_CHECKED); + else + CheckMenuItem(hPopupMenu, ID_OPTIONS_ALWAYSONTOP, MF_BYCOMMAND | MF_UNCHECKED); SetForegroundWindow(hMainWnd); TrackPopupMenuEx(hPopupMenu, 0, pt.x, pt.y, hMainWnd, NULL); @@ -680,19 +671,19 @@ BOOL OnCreate(HWND hWnd) lpUserName = HeapAlloc(GetProcessHeap(), HEAP_ZERO_MEMORY, len * sizeof(WCHAR)); if (lpUserName && GetUserNameW(lpUserName, &len)) { - _snwprintf(szLogOffItem, sizeof(szLogOffItem)/sizeof(szLogOffItem[0]), szTemp, lpUserName); - szLogOffItem[sizeof(szLogOffItem)/sizeof(szLogOffItem[0]) - 1] = UNICODE_NULL; + _snwprintf(szLogOffItem, _countof(szLogOffItem), szTemp, lpUserName); + szLogOffItem[_countof(szLogOffItem) - 1] = UNICODE_NULL; } else { - _snwprintf(szLogOffItem, sizeof(szLogOffItem)/sizeof(szLogOffItem[0]), szTemp, L"n/a"); + _snwprintf(szLogOffItem, _countof(szLogOffItem), szTemp, L"n/a"); } if (lpUserName) HeapFree(GetProcessHeap(), 0, lpUserName); } else { - _snwprintf(szLogOffItem, sizeof(szLogOffItem)/sizeof(szLogOffItem[0]), szTemp, L"n/a"); + _snwprintf(szLogOffItem, _countof(szLogOffItem), szTemp, L"n/a"); } /* 3- Set the menu item text to its formatted counterpart */ @@ -868,11 +859,8 @@ void SaveSettings(void) void TaskManager_OnRestoreMainWindow(void) { - //HMENU hMenu, hOptionsMenu; BOOL OnTop; - //hMenu = GetMenu(hMainWnd); - //hOptionsMenu = GetSubMenu(hMenu, OPTIONS_MENU_INDEX); OnTop = ((GetWindowLongPtrW(hMainWnd, GWL_EXSTYLE) & WS_EX_TOPMOST) != 0); OpenIcon(hMainWnd);

1 year, 3 months

[reactos] 06/06: [NTOS:KE/x64] Implement detection of more KF_* feature flags

by Timo Kreuzer

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=410b1030c02240e0a711b… commit 410b1030c02240e0a711b0006023451fdd46a6d1 Author: Timo Kreuzer <timo.kreuzer(a)reactos.org> AuthorDate: Sun Aug 27 15:07:30 2023 +0300 Commit: Timo Kreuzer <timo.kreuzer(a)reactos.org> CommitDate: Tue Oct 3 19:45:44 2023 +0300 [NTOS:KE/x64] Implement detection of more KF_* feature flags - Detect KF_SSSE3, KF_SSE4_1, KF_SSE4_2, KF_RDRAND, KF_BRANCH, KF_SLAT, KF_GENUINE_INTEL, KF_AUTHENTICAMD, KF_ACNT2, KF_SMEP, KF_SMAP, KF_RDWRFSGSBASE, KF_XSAVEOPT, KF_XSAVES, KF_HUGEPAGE, KF_RDTSCP --- ntoskrnl/ke/amd64/cpu.c | 159 +++++++++++++++++++++++++++++++++---- sdk/include/ndk/amd64/ketypes.h | 2 +- sdk/include/reactos/x86x64/Cpuid.h | 11 ++- sdk/include/reactos/x86x64/Msr.h | 6 ++ 4 files changed, 156 insertions(+), 22 deletions(-) diff --git a/ntoskrnl/ke/amd64/cpu.c b/ntoskrnl/ke/amd64/cpu.c index f01784f5b07..b2b40b0bf62 100644 --- a/ntoskrnl/ke/amd64/cpu.c +++ b/ntoskrnl/ke/amd64/cpu.c @@ -11,6 +11,7 @@ #include <ntoskrnl.h> #include <x86x64/Cpuid.h> +#include <x86x64/Msr.h> #define NDEBUG #include <debug.h> @@ -146,6 +147,19 @@ KiSetProcessorType(VOID) KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping; } +/*! + \brief Evaluates the KeFeatureFlag bits for the current CPU. + + \return The feature flags for this CPU. + + \see https://www.geoffchappell.com/studies/windows/km/ntoskrnl/structs/kprcb/fea… + + \todo + - KF_VIRT_FIRMWARE_ENABLED 0x08000000 (see notes from Geoff Chappell) + - KF_FPU_LEAKAGE 0x0000020000000000ULL + - KF_CAT 0x0000100000000000ULL + - KF_CET_SS 0x0000400000000000ULL +*/ ULONG64 NTAPI KiGetFeatureBits(VOID) @@ -153,6 +167,7 @@ KiGetFeatureBits(VOID) PKPRCB Prcb = KeGetCurrentPrcb(); ULONG Vendor; ULONG64 FeatureBits = 0; + CPUID_SIGNATURE_REGS signature; CPUID_VERSION_INFO_REGS VersionInfo; CPUID_EXTENDED_FUNCTION_REGS extendedFunction; @@ -160,7 +175,10 @@ KiGetFeatureBits(VOID) Vendor = Prcb->CpuVendor; /* Make sure we got a valid vendor ID at least. */ - if (!Vendor) return FeatureBits; + if (Vendor == CPU_UNKNOWN) return FeatureBits; + + /* Get signature CPUID for the maximum function */ + __cpuid(signature.AsInt32, CPUID_SIGNATURE); /* Get the CPUID Info. */ __cpuid(VersionInfo.AsInt32, CPUID_VERSION_INFO); @@ -189,6 +207,7 @@ KiGetFeatureBits(VOID) if (VersionInfo.Ecx.Bits.CMPXCHG16B) FeatureBits |= KF_CMPXCHG16B; if (VersionInfo.Ecx.Bits.SSE4_1) FeatureBits |= KF_SSE4_1; if (VersionInfo.Ecx.Bits.XSAVE) FeatureBits |= KF_XSTATE; + if (VersionInfo.Ecx.Bits.RDRAND) FeatureBits |= KF_RDRAND; /* Check if the CPU has hyper-threading */ if (VersionInfo.Edx.Bits.HTT) @@ -208,27 +227,115 @@ KiGetFeatureBits(VOID) Prcb->LogicalProcessorsPerPhysicalProcessor = 1; } + /* Check if CPUID_THERMAL_POWER_MANAGEMENT (0x06) is supported */ + if (signature.MaxLeaf >= CPUID_THERMAL_POWER_MANAGEMENT) + { + /* Read CPUID_THERMAL_POWER_MANAGEMENT */ + CPUID_THERMAL_POWER_MANAGEMENT_REGS PowerInfo; + __cpuid(PowerInfo.AsInt32, CPUID_THERMAL_POWER_MANAGEMENT); + + if (PowerInfo.Undoc.Ecx.ACNT2) FeatureBits |= KF_ACNT2; + } + + /* Check if CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07) is supported */ + if (signature.MaxLeaf >= CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS) + { + /* Read CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS */ + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_REGS ExtFlags; + __cpuidex(ExtFlags.AsInt32, + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO); + + if (ExtFlags.Ebx.Bits.SMEP) FeatureBits |= KF_SMEP; + if (ExtFlags.Ebx.Bits.FSGSBASE) FeatureBits |= KF_RDWRFSGSBASE; + if (ExtFlags.Ebx.Bits.SMAP) FeatureBits |= KF_SMAP; + } + + /* Check if CPUID_EXTENDED_STATE (0x0D) is supported */ + if (signature.MaxLeaf >= CPUID_EXTENDED_STATE) + { + /* Read CPUID_EXTENDED_STATE */ + CPUID_EXTENDED_STATE_SUB_LEAF_EAX_REGS ExtStateSub; + __cpuidex(ExtStateSub.AsInt32, + CPUID_EXTENDED_STATE, + CPUID_EXTENDED_STATE_SUB_LEAF); + + if (ExtStateSub.Eax.Bits.XSAVEOPT) FeatureBits |= KF_XSAVEOPT; + if (ExtStateSub.Eax.Bits.XSAVES) FeatureBits |= KF_XSAVES; + } + /* Check extended cpuid features */ __cpuid(extendedFunction.AsInt32, CPUID_EXTENDED_FUNCTION); if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000) { - /* Check if CPUID 0x80000001 is supported */ - if (extendedFunction.MaxLeaf >= 0x80000001) + /* Check if CPUID_EXTENDED_CPU_SIG (0x80000001) is supported */ + if (extendedFunction.MaxLeaf >= CPUID_EXTENDED_CPU_SIG) { - CPUID_EXTENDED_CPU_SIG_REGS extSig; - - /* Check which extended features are available. */ - __cpuid(extSig.AsInt32, CPUID_EXTENDED_CPU_SIG); + /* Read CPUID_EXTENDED_CPU_SIG */ + CPUID_EXTENDED_CPU_SIG_REGS ExtSig; + __cpuid(ExtSig.AsInt32, CPUID_EXTENDED_CPU_SIG); /* Check if NX-bit is supported */ - if (extSig.Intel.Edx.Bits.NX) FeatureBits |= KF_NX_BIT; + if (ExtSig.Intel.Edx.Bits.NX) FeatureBits |= KF_NX_BIT; + if (ExtSig.Intel.Edx.Bits.Page1GB) FeatureBits |= KF_HUGEPAGE; + if (ExtSig.Intel.Edx.Bits.RDTSCP) FeatureBits |= KF_RDTSCP; - /* Now handle each features for each CPU Vendor */ - switch (Vendor) + /* AMD specific */ + if (Vendor == CPU_AMD) { - case CPU_AMD: - if (extSig.Amd.Edx.Bits.ThreeDNow) FeatureBits |= KF_3DNOW; - break; + if (ExtSig.Amd.Edx.Bits.ThreeDNow) FeatureBits |= KF_3DNOW; + } + } + } + + /* Vendor specific */ + if (Vendor == CPU_INTEL) + { + FeatureBits |= KF_GENUINE_INTEL; + + /* Check for models that support LBR */ + if (VersionInfo.Eax.Bits.FamilyId == 6) + { + if ((VersionInfo.Eax.Bits.Model == 15) || + (VersionInfo.Eax.Bits.Model == 22) || + (VersionInfo.Eax.Bits.Model == 23) || + (VersionInfo.Eax.Bits.Model == 26)) + { + FeatureBits |= KF_BRANCH; + } + } + + /* Check if VMX is available */ + if (VersionInfo.Ecx.Bits.VMX) + { + /* Read PROCBASED ctls and check if secondary are allowed */ + MSR_IA32_VMX_PROCBASED_CTLS_REGISTER ProcBasedCtls; + ProcBasedCtls.Uint64 = __readmsr(MSR_IA32_VMX_PROCBASED_CTLS); + if (ProcBasedCtls.Bits.Allowed1.ActivateSecondaryControls) + { + /* Read secondary controls and check if EPT is allowed */ + MSR_IA32_VMX_PROCBASED_CTLS2_REGISTER ProcBasedCtls2; + ProcBasedCtls2.Uint64 = __readmsr(MSR_IA32_VMX_PROCBASED_CTLS2); + if (ProcBasedCtls2.Bits.Allowed1.EPT) + FeatureBits |= KF_SLAT; + } + } + } + else if (Vendor == CPU_AMD) + { + FeatureBits |= KF_AUTHENTICAMD; + FeatureBits |= KF_BRANCH; + + /* Check extended cpuid features */ + if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000) + { + /* Check if CPUID_AMD_SVM_FEATURES (0x8000000A) is supported */ + if (extendedFunction.MaxLeaf >= CPUID_AMD_SVM_FEATURES) + { + /* Read CPUID_AMD_SVM_FEATURES and check if Nested Paging is available */ + CPUID_AMD_SVM_FEATURES_REGS SvmFeatures; + __cpuid(SvmFeatures.AsInt32, CPUID_AMD_SVM_FEATURES); + if (SvmFeatures.Edx.Bits.NP) FeatureBits |= KF_SLAT; } } } @@ -261,22 +368,40 @@ KiReportCpuFeatures(IN PKPRCB Prcb) print_kf_bit(KF_LARGE_PAGE); print_kf_bit(KF_MTRR); print_kf_bit(KF_CMPXCHG8B); - print_kf_bit(KF_CMPXCHG16B); print_kf_bit(KF_MMX); + print_kf_bit(KF_DTS); print_kf_bit(KF_PAT); print_kf_bit(KF_FXSR); print_kf_bit(KF_FAST_SYSCALL); print_kf_bit(KF_XMMI); print_kf_bit(KF_3DNOW); + print_kf_bit(KF_XSAVEOPT); print_kf_bit(KF_XMMI64); - print_kf_bit(KF_DTS); + print_kf_bit(KF_BRANCH); + print_kf_bit(KF_00040000); + print_kf_bit(KF_SSE3); + print_kf_bit(KF_CMPXCHG16B); + print_kf_bit(KF_AUTHENTICAMD); + print_kf_bit(KF_ACNT2); + print_kf_bit(KF_XSTATE); + print_kf_bit(KF_GENUINE_INTEL); + print_kf_bit(KF_SLAT); + print_kf_bit(KF_VIRT_FIRMWARE_ENABLED); + print_kf_bit(KF_RDWRFSGSBASE); print_kf_bit(KF_NX_BIT); print_kf_bit(KF_NX_DISABLED); print_kf_bit(KF_NX_ENABLED); - print_kf_bit(KF_SSE3); + print_kf_bit(KF_RDRAND); + print_kf_bit(KF_SMAP); + print_kf_bit(KF_RDTSCP); + print_kf_bit(KF_HUGEPAGE); + print_kf_bit(KF_XSAVES); + print_kf_bit(KF_FPU_LEAKAGE); + print_kf_bit(KF_CAT); + print_kf_bit(KF_CET_SS); print_kf_bit(KF_SSSE3); print_kf_bit(KF_SSE4_1); - print_kf_bit(KF_XSTATE); + print_kf_bit(KF_SSE4_2); #undef print_kf_bit #define print_cf(cpu_flag) if (CpuFeatures & cpu_flag) DbgPrint(#cpu_flag " ") diff --git a/sdk/include/ndk/amd64/ketypes.h b/sdk/include/ndk/amd64/ketypes.h index 1f306de1d2c..81219a73f82 100644 --- a/sdk/include/ndk/amd64/ketypes.h +++ b/sdk/include/ndk/amd64/ketypes.h @@ -249,7 +249,7 @@ typedef enum #define MSR_GS_SWAP 0xC0000102 #define MSR_MCG_STATUS 0x017A #define MSR_AMD_ACCESS 0x9C5A203A -#define MSR_IA32_MISC_ENABLE 0x01A0 +#define MSR_IA32_MISC_ENABLE 0x000001A0 #define MSR_LAST_BRANCH_FROM 0x01DB #define MSR_LAST_BRANCH_TO 0x01DC #define MSR_LAST_EXCEPTION_FROM 0x01DD diff --git a/sdk/include/reactos/x86x64/Cpuid.h b/sdk/include/reactos/x86x64/Cpuid.h index 0a27d581e17..39ece442c99 100644 --- a/sdk/include/reactos/x86x64/Cpuid.h +++ b/sdk/include/reactos/x86x64/Cpuid.h @@ -1,3 +1,9 @@ +/* + * PROJECT: ReactOS SDK + * LICENSE: MIT (https://spdx.org/licenses/MIT) + * PURPOSE: Provides CPUID structure definitions + * COPYRIGHT: Copyright 2023 Timo Kreuzer <timo.kreuzer(a)reactos.org> + */ #define CHAR8 char @@ -104,10 +110,7 @@ typedef union UINT32 XSaveAreaSize; // The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS. } Ebx; CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx; - struct - { - UINT32 Edx; // Reports the supported bits of the upper 32 bits of the IA32_XSS MSR.IA32_XSS[n + 32] can be set to 1 only if EDX[n] is 1. - } Edx; + UINT32 Edx; // Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n + 32] can be set to 1 only if EDX[n] is 1. }; } CPUID_EXTENDED_STATE_SUB_LEAF_EAX_REGS; diff --git a/sdk/include/reactos/x86x64/Msr.h b/sdk/include/reactos/x86x64/Msr.h index 21e2a4df6ec..98b3e4d9ae1 100644 --- a/sdk/include/reactos/x86x64/Msr.h +++ b/sdk/include/reactos/x86x64/Msr.h @@ -1,3 +1,9 @@ +/* + * PROJECT: ReactOS SDK + * LICENSE: MIT (https://spdx.org/licenses/MIT) + * PURPOSE: Provides CPUID structure definitions + * COPYRIGHT: Copyright 2023 Timo Kreuzer <timo.kreuzer(a)reactos.org> + */ #define SIZE_2KB 2048

1 year, 3 months

[reactos] 05/06: [NTOS:KE/x64] Use structures for CPUID

by Timo Kreuzer

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=1a7ab2fe6826f679d67b8… commit 1a7ab2fe6826f679d67b827eb9e872ae7fa5ed98 Author: Timo Kreuzer <timo.kreuzer(a)reactos.org> AuthorDate: Sun Aug 27 12:08:37 2023 +0300 Commit: Timo Kreuzer <timo.kreuzer(a)reactos.org> CommitDate: Tue Oct 3 19:45:44 2023 +0300 [NTOS:KE/x64] Use structures for CPUID --- ntoskrnl/ke/amd64/cpu.c | 67 ++++++++++++++++++++++++++----------------------- 1 file changed, 36 insertions(+), 31 deletions(-) diff --git a/ntoskrnl/ke/amd64/cpu.c b/ntoskrnl/ke/amd64/cpu.c index d5086b950d3..f01784f5b07 100644 --- a/ntoskrnl/ke/amd64/cpu.c +++ b/ntoskrnl/ke/amd64/cpu.c @@ -10,6 +10,7 @@ /* INCLUDES *****************************************************************/ #include <ntoskrnl.h> +#include <x86x64/Cpuid.h> #define NDEBUG #include <debug.h> @@ -152,7 +153,8 @@ KiGetFeatureBits(VOID) PKPRCB Prcb = KeGetCurrentPrcb(); ULONG Vendor; ULONG64 FeatureBits = 0; - CPU_INFO CpuInfo; + CPUID_VERSION_INFO_REGS VersionInfo; + CPUID_EXTENDED_FUNCTION_REGS extendedFunction; /* Get the Vendor ID */ Vendor = Prcb->CpuVendor; @@ -161,38 +163,39 @@ KiGetFeatureBits(VOID) if (!Vendor) return FeatureBits; /* Get the CPUID Info. */ - KiCpuId(&CpuInfo, 1); + __cpuid(VersionInfo.AsInt32, CPUID_VERSION_INFO); /* Set the initial APIC ID */ - Prcb->InitialApicId = (UCHAR)(CpuInfo.Ebx >> 24); + Prcb->InitialApicId = (UCHAR)VersionInfo.Ebx.Bits.InitialLocalApicId; /* Convert all CPUID Feature bits into our format */ - if (CpuInfo.Edx & X86_FEATURE_VME) FeatureBits |= KF_CR4; - if (CpuInfo.Edx & X86_FEATURE_PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4; - if (CpuInfo.Edx & X86_FEATURE_TSC) FeatureBits |= KF_RDTSC; - if (CpuInfo.Edx & X86_FEATURE_CX8) FeatureBits |= KF_CMPXCHG8B; - if (CpuInfo.Edx & X86_FEATURE_SYSCALL) FeatureBits |= KF_FAST_SYSCALL; - if (CpuInfo.Edx & X86_FEATURE_MTTR) FeatureBits |= KF_MTRR; - if (CpuInfo.Edx & X86_FEATURE_PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4; - if (CpuInfo.Edx & X86_FEATURE_CMOV) FeatureBits |= KF_CMOV; - if (CpuInfo.Edx & X86_FEATURE_PAT) FeatureBits |= KF_PAT; - if (CpuInfo.Edx & X86_FEATURE_DS) FeatureBits |= KF_DTS; - if (CpuInfo.Edx & X86_FEATURE_MMX) FeatureBits |= KF_MMX; - if (CpuInfo.Edx & X86_FEATURE_FXSR) FeatureBits |= KF_FXSR; - if (CpuInfo.Edx & X86_FEATURE_SSE) FeatureBits |= KF_XMMI; - if (CpuInfo.Edx & X86_FEATURE_SSE2) FeatureBits |= KF_XMMI64; - - if (CpuInfo.Ecx & X86_FEATURE_SSE3) FeatureBits |= KF_SSE3; - //if (CpuInfo.Ecx & X86_FEATURE_SSSE3) FeatureBits |= KF_SSSE3; - if (CpuInfo.Ecx & X86_FEATURE_CX16) FeatureBits |= KF_CMPXCHG16B; - //if (CpuInfo.Ecx & X86_FEATURE_SSE41) FeatureBits |= KF_SSE4_1; - if (CpuInfo.Ecx & X86_FEATURE_XSAVE) FeatureBits |= KF_XSTATE; + if (VersionInfo.Edx.Bits.VME) FeatureBits |= KF_CR4; + if (VersionInfo.Edx.Bits.PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4; + if (VersionInfo.Edx.Bits.TSC) FeatureBits |= KF_RDTSC; + if (VersionInfo.Edx.Bits.CX8) FeatureBits |= KF_CMPXCHG8B; + if (VersionInfo.Edx.Bits.SEP) FeatureBits |= KF_FAST_SYSCALL; + if (VersionInfo.Edx.Bits.MTRR) FeatureBits |= KF_MTRR; + if (VersionInfo.Edx.Bits.PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4; + if (VersionInfo.Edx.Bits.CMOV) FeatureBits |= KF_CMOV; + if (VersionInfo.Edx.Bits.PAT) FeatureBits |= KF_PAT; + if (VersionInfo.Edx.Bits.DS) FeatureBits |= KF_DTS; + if (VersionInfo.Edx.Bits.MMX) FeatureBits |= KF_MMX; + if (VersionInfo.Edx.Bits.FXSR) FeatureBits |= KF_FXSR; + if (VersionInfo.Edx.Bits.SSE) FeatureBits |= KF_XMMI; + if (VersionInfo.Edx.Bits.SSE2) FeatureBits |= KF_XMMI64; + + if (VersionInfo.Ecx.Bits.SSE3) FeatureBits |= KF_SSE3; + if (VersionInfo.Ecx.Bits.SSSE3) FeatureBits |= KF_SSSE3; + if (VersionInfo.Ecx.Bits.CMPXCHG16B) FeatureBits |= KF_CMPXCHG16B; + if (VersionInfo.Ecx.Bits.SSE4_1) FeatureBits |= KF_SSE4_1; + if (VersionInfo.Ecx.Bits.XSAVE) FeatureBits |= KF_XSTATE; /* Check if the CPU has hyper-threading */ - if (CpuInfo.Edx & X86_FEATURE_HT) + if (VersionInfo.Edx.Bits.HTT) { /* Set the number of logical CPUs */ - Prcb->LogicalProcessorsPerPhysicalProcessor = (UCHAR)(CpuInfo.Ebx >> 16); + Prcb->LogicalProcessorsPerPhysicalProcessor = + VersionInfo.Ebx.Bits.MaximumAddressableIdsForLogicalProcessors; if (Prcb->LogicalProcessorsPerPhysicalProcessor > 1) { /* We're on dual-core */ @@ -206,23 +209,25 @@ KiGetFeatureBits(VOID) } /* Check extended cpuid features */ - KiCpuId(&CpuInfo, 0x80000000); - if ((CpuInfo.Eax & 0xffffff00) == 0x80000000) + __cpuid(extendedFunction.AsInt32, CPUID_EXTENDED_FUNCTION); + if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000) { /* Check if CPUID 0x80000001 is supported */ - if (CpuInfo.Eax >= 0x80000001) + if (extendedFunction.MaxLeaf >= 0x80000001) { + CPUID_EXTENDED_CPU_SIG_REGS extSig; + /* Check which extended features are available. */ - KiCpuId(&CpuInfo, 0x80000001); + __cpuid(extSig.AsInt32, CPUID_EXTENDED_CPU_SIG); /* Check if NX-bit is supported */ - if (CpuInfo.Edx & X86_FEATURE_NX) FeatureBits |= KF_NX_BIT; + if (extSig.Intel.Edx.Bits.NX) FeatureBits |= KF_NX_BIT; /* Now handle each features for each CPU Vendor */ switch (Vendor) { case CPU_AMD: - if (CpuInfo.Edx & 0x80000000) FeatureBits |= KF_3DNOW; + if (extSig.Amd.Edx.Bits.ThreeDNow) FeatureBits |= KF_3DNOW; break; } }

1 year, 3 months

[reactos] 04/06: [SDK] Add CPUID and MSR definitions for x86/x64

by Timo Kreuzer

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=6048ebeff9988428b795d… commit 6048ebeff9988428b795d177f1fe3dc9fa6e2470 Author: Timo Kreuzer <timo.kreuzer(a)reactos.org> AuthorDate: Sun Aug 27 11:18:40 2023 +0300 Commit: Timo Kreuzer <timo.kreuzer(a)reactos.org> CommitDate: Tue Oct 3 19:45:44 2023 +0300 [SDK] Add CPUID and MSR definitions for x86/x64 - Import definitions from edk2 (see https://github.com/tianocore/edk2/tree/master/MdePkg/Include/Register) - Add additional unions as well as AMD SVM CPUID --- sdk/include/reactos/x86x64/Amd/Cpuid.h | 733 +++ sdk/include/reactos/x86x64/Cpuid.h | 205 + .../reactos/x86x64/Intel/ArchitecturalMsr.h | 6532 ++++++++++++++++++++ sdk/include/reactos/x86x64/Intel/Cpuid.h | 4083 ++++++++++++ sdk/include/reactos/x86x64/Msr.h | 91 + 5 files changed, 11644 insertions(+) diff --git a/sdk/include/reactos/x86x64/Amd/Cpuid.h b/sdk/include/reactos/x86x64/Amd/Cpuid.h new file mode 100644 index 00000000000..d26b8270b73 --- /dev/null +++ b/sdk/include/reactos/x86x64/Amd/Cpuid.h @@ -0,0 +1,733 @@ +/** @file + CPUID leaf definitions. + + Provides defines for CPUID leaf indexes. Data structures are provided for + registers returned by a CPUID leaf that contain one or more bit fields. + If a register returned is a single 32-bit value, then a data structure is + not provided for that register. + + Copyright (c) 2017, Advanced Micro Devices. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34 + +**/ + +#ifndef __AMD_CPUID_H__ +#define __AMD_CPUID_H__ + +/** +CPUID Signature Information + +@param EAX CPUID_SIGNATURE (0x00) + +@retval EAX Returns the highest value the CPUID instruction recognizes for + returning basic processor information. The value is returned is + processor specific. +@retval EBX First 4 characters of a vendor identification string. +@retval ECX Last 4 characters of a vendor identification string. +@retval EDX Middle 4 characters of a vendor identification string. + +**/ + +/// +/// @{ CPUID signature values returned by AMD processors +/// +#define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h') +#define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i') +#define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D') +/// +/// @} +/// + +/** + CPUID Extended Processor Signature and Features + + @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001) + + @retval EAX Extended Family, Model, Stepping Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX. + @retval EBX Brand Identifier + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX. + @retval ECX Extended Feature Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX. + @retval EDX Extended Feature Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX. +**/ + +/** + CPUID Extended Processor Signature and Features EAX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Stepping. + /// + UINT32 Stepping : 4; + /// + /// [Bits 7:4] Base Model. + /// + UINT32 BaseModel : 4; + /// + /// [Bits 11:8] Base Family. + /// + UINT32 BaseFamily : 4; + /// + /// [Bit 15:12] Reserved. + /// + UINT32 Reserved1 : 4; + /// + /// [Bits 19:16] Extended Model. + /// + UINT32 ExtModel : 4; + /// + /// [Bits 27:20] Extended Family. + /// + UINT32 ExtFamily : 8; + /// + /// [Bit 31:28] Reserved. + /// + UINT32 Reserved2 : 4; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EAX; + +/** + CPUID Extended Processor Signature and Features EBX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 27:0] Reserved. + /// + UINT32 Reserved : 28; + /// + /// [Bit 31:28] Package Type. + /// + UINT32 PkgType : 4; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EBX; + +/** + CPUID Extended Processor Signature and Features ECX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LAHF/SAHF available in 64-bit mode. + /// + UINT32 LAHF_SAHF : 1; + /// + /// [Bit 1] Core multi-processing legacy mode. + /// + UINT32 CmpLegacy : 1; + /// + /// [Bit 2] Secure Virtual Mode feature. + /// + UINT32 SVM : 1; + /// + /// [Bit 3] Extended APIC register space. + /// + UINT32 ExtApicSpace : 1; + /// + /// [Bit 4] LOCK MOV CR0 means MOV CR8. + /// + UINT32 AltMovCr8 : 1; + /// + /// [Bit 5] LZCNT instruction support. + /// + UINT32 LZCNT : 1; + /// + /// [Bit 6] SSE4A instruction support. + /// + UINT32 SSE4A : 1; + /// + /// [Bit 7] Misaligned SSE Mode. + /// + UINT32 MisAlignSse : 1; + /// + /// [Bit 8] ThreeDNow Prefetch instructions. + /// + UINT32 PREFETCHW : 1; + /// + /// [Bit 9] OS Visible Work-around support. + /// + UINT32 OSVW : 1; + /// + /// [Bit 10] Instruction Based Sampling. + /// + UINT32 IBS : 1; + /// + /// [Bit 11] Extended Operation Support. + /// + UINT32 XOP : 1; + /// + /// [Bit 12] SKINIT and STGI support. + /// + UINT32 SKINIT : 1; + /// + /// [Bit 13] Watchdog Timer support. + /// + UINT32 WDT : 1; + /// + /// [Bit 14] Reserved. + /// + UINT32 Reserved1 : 1; + /// + /// [Bit 15] Lightweight Profiling support. + /// + UINT32 LWP : 1; + /// + /// [Bit 16] 4-Operand FMA instruction support. + /// + UINT32 FMA4 : 1; + /// + /// [Bit 17] Translation Cache Extension. + /// + UINT32 TCE : 1; + /// + /// [Bit 21:18] Reserved. + /// + UINT32 Reserved2 : 4; + /// + /// [Bit 22] Topology Extensions support. + /// + UINT32 TopologyExtensions : 1; + /// + /// [Bit 23] Core Performance Counter Extensions. + /// + UINT32 PerfCtrExtCore : 1; + /// + /// [Bit 25:24] Reserved. + /// + UINT32 Reserved3 : 2; + /// + /// [Bit 26] Data Breakpoint Extension. + /// + UINT32 DataBreakpointExtension : 1; + /// + /// [Bit 27] Performance Time-Stamp Counter. + /// + UINT32 PerfTsc : 1; + /// + /// [Bit 28] L3 Performance Counter Extensions. + /// + UINT32 PerfCtrExtL3 : 1; + /// + /// [Bit 29] MWAITX and MONITORX capability. + /// + UINT32 MwaitExtended : 1; + /// + /// [Bit 31:30] Reserved. + /// + UINT32 Reserved4 : 2; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_ECX; + +/** + CPUID Extended Processor Signature and Features EDX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] x87 floating point unit on-chip. + /// + UINT32 FPU : 1; + /// + /// [Bit 1] Virtual-mode enhancements. + /// + UINT32 VME : 1; + /// + /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE. + /// + UINT32 DE : 1; + /// + /// [Bit 3] Page-size extensions (4 MB pages). + /// + UINT32 PSE : 1; + /// + /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD. + /// + UINT32 TSC : 1; + /// + /// [Bit 5] MSRs, with RDMSR and WRMSR instructions. + /// + UINT32 MSR : 1; + /// + /// [Bit 6] Physical-address extensions (PAE). + /// + UINT32 PAE : 1; + /// + /// [Bit 7] Machine check exception, CR4.MCE. + /// + UINT32 MCE : 1; + /// + /// [Bit 8] CMPXCHG8B instruction. + /// + UINT32 CMPXCHG8B : 1; + /// + /// [Bit 9] APIC exists and is enabled. + /// + UINT32 APIC : 1; + /// + /// [Bit 10] Reserved. + /// + UINT32 Reserved1 : 1; + /// + /// [Bit 11] SYSCALL and SYSRET instructions. + /// + UINT32 SYSCALL_SYSRET : 1; + /// + /// [Bit 12] Memory-type range registers. + /// + UINT32 MTRR : 1; + /// + /// [Bit 13] Page global extension, CR4.PGE. + /// + UINT32 PGE : 1; + /// + /// [Bit 14] Machine check architecture, MCG_CAP. + /// + UINT32 MCA : 1; + /// + /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV. + /// + UINT32 CMOV : 1; + /// + /// [Bit 16] Page attribute table. + /// + UINT32 PAT : 1; + /// + /// [Bit 17] Page-size extensions. + /// + UINT32 PSE36 : 1; + /// + /// [Bit 19:18] Reserved. + /// + UINT32 Reserved2 : 2; + /// + /// [Bit 20] No-execute page protection. + /// + UINT32 NX : 1; + /// + /// [Bit 21] Reserved. + /// + UINT32 Reserved3 : 1; + /// + /// [Bit 22] AMD Extensions to MMX instructions. + /// + UINT32 MmxExt : 1; + /// + /// [Bit 23] MMX instructions. + /// + UINT32 MMX : 1; + /// + /// [Bit 24] FXSAVE and FXRSTOR instructions. + /// + UINT32 FFSR : 1; + /// + /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations. + /// + UINT32 FFXSR : 1; + /// + /// [Bit 26] 1-GByte large page support. + /// + UINT32 Page1GB : 1; + /// + /// [Bit 27] RDTSCP instructions. + /// + UINT32 RDTSCP : 1; + /// + /// [Bit 28] Reserved. + /// + UINT32 Reserved4 : 1; + /// + /// [Bit 29] Long Mode. + /// + UINT32 LM : 1; + /// + /// [Bit 30] 3DNow! instructions. + /// + UINT32 ThreeDNow : 1; + /// + /// [Bit 31] AMD Extensions to 3DNow! instructions. + /// + UINT32 ThreeDNowExt : 1; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EDX; + +/** +CPUID Linear Physical Address Size + +@param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) + +@retval EAX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX. +@retval EBX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX. +@retval ECX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX. +@retval EDX Reserved. +**/ + +/** + CPUID Linear Physical Address Size EAX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Maximum physical byte address size in bits. + /// + UINT32 PhysicalAddressBits : 8; + /// + /// [Bits 15:8] Maximum linear byte address size in bits. + /// + UINT32 LinearAddressBits : 8; + /// + /// [Bits 23:16] Maximum guest physical byte address size in bits. + /// + UINT32 GuestPhysAddrSize : 8; + /// + /// [Bit 31:24] Reserved. + /// + UINT32 Reserved : 8; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX; + +/** + CPUID Linear Physical Address Size EBX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 0] Clear Zero Instruction. + /// + UINT32 CLZERO : 1; + /// + /// [Bits 1] Instructions retired count support. + /// + UINT32 IRPerf : 1; + /// + /// [Bits 2] Restore error pointers for XSave instructions. + /// + UINT32 XSaveErPtr : 1; + /// + /// [Bit 31:3] Reserved. + /// + UINT32 Reserved : 29; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX; + +/** + CPUID Linear Physical Address Size ECX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Number of threads - 1. + /// + UINT32 NC : 8; + /// + /// [Bit 11:8] Reserved. + /// + UINT32 Reserved1 : 4; + /// + /// [Bits 15:12] APIC ID size. + /// + UINT32 ApicIdCoreIdSize : 4; + /// + /// [Bits 17:16] Performance time-stamp counter size. + /// + UINT32 PerfTscSize : 2; + /// + /// [Bit 31:18] Reserved. + /// + UINT32 Reserved2 : 14; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX; + +/** + CPUID AMD Processor Topology + + @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E) + + @retval EAX Extended APIC ID described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_EAX. + @retval EBX Core Identifiers described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX. + @retval ECX Node Identifiers described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX. + @retval EDX Reserved. +**/ +#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E + +/** + CPUID AMD Processor Topology EAX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] Extended APIC Id. + /// + UINT32 ExtendedApicId; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX; + +/** + CPUID AMD Processor Topology EBX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Core Id. + /// + UINT32 CoreId : 8; + /// + /// [Bits 15:8] Threads per core. + /// + UINT32 ThreadsPerCore : 8; + /// + /// [Bit 31:16] Reserved. + /// + UINT32 Reserved : 16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX; + +/** + CPUID AMD Processor Topology ECX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Node Id. + /// + UINT32 NodeId : 8; + /// + /// [Bits 10:8] Nodes per processor. + /// + UINT32 NodesPerProcessor : 3; + /// + /// [Bit 31:11] Reserved. + /// + UINT32 Reserved : 21; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX; + +/** + CPUID Memory Encryption Information + + @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F) + + @retval EAX Returns the memory encryption feature support status. + @retval EBX If memory encryption feature is present then return + the page table bit number used to enable memory encryption support + and reducing of physical address space in bits. + @retval ECX Returns number of encrypted guest supported simultaneously. + @retval EDX Returns minimum SEV enabled and SEV disabled ASID. + + Example usage + @code + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + + AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx); + @endcode +**/ + +#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F + +/** + CPUID Memory Encryption support information EAX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Secure Memory Encryption (Sme) Support + /// + UINT32 SmeBit : 1; + + /// + /// [Bit 1] Secure Encrypted Virtualization (Sev) Support + /// + UINT32 SevBit : 1; + + /// + /// [Bit 2] Page flush MSR support + /// + UINT32 PageFlushMsrBit : 1; + + /// + /// [Bit 3] Encrypted state support + /// + UINT32 SevEsBit : 1; + + /// + /// [Bit 31:4] Reserved + /// + UINT32 ReservedBits : 28; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EAX; + +/** + CPUID Memory Encryption support information EBX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 5:0] Page table bit number used to enable memory encryption + /// + UINT32 PtePosBits : 6; + + /// + /// [Bit 11:6] Reduction of system physical address space bits when + /// memory encryption is enabled + /// + UINT32 ReducedPhysBits : 5; + + /// + /// [Bit 31:12] Reserved + /// + UINT32 ReservedBits : 21; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EBX; + +/** + CPUID Memory Encryption support information ECX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] Number of encrypted guest supported simultaneously + /// + UINT32 NumGuests; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_ECX; + +/** + CPUID Memory Encryption support information EDX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID + /// + UINT32 MinAsid; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EDX; + +#endif diff --git a/sdk/include/reactos/x86x64/Cpuid.h b/sdk/include/reactos/x86x64/Cpuid.h new file mode 100644 index 00000000000..0a27d581e17 --- /dev/null +++ b/sdk/include/reactos/x86x64/Cpuid.h @@ -0,0 +1,205 @@ + +#define CHAR8 char + +#include "Intel/Cpuid.h" +#include "Amd/Cpuid.h" + +// CPUID_SIGNATURE (0) +typedef union +{ + INT32 AsInt32[4]; + struct + { + UINT32 MaxLeaf; + CHAR SignatureScrambled[12]; + }; +} CPUID_SIGNATURE_REGS; + +// CPUID_VERSION_INFO (1) +typedef union +{ + INT32 AsInt32[4]; + struct + { + CPUID_VERSION_INFO_EAX Eax; + CPUID_VERSION_INFO_EBX Ebx; + CPUID_VERSION_INFO_ECX Ecx; + CPUID_VERSION_INFO_EDX Edx; + }; +} CPUID_VERSION_INFO_REGS; + +// CPUID_EXTENDED_FUNCTION (0x80000000) +typedef union +{ + INT32 AsInt32[4]; + struct + { + UINT32 MaxLeaf; + UINT32 ReservedEbx; + UINT32 ReservedEcx; + UINT32 ReservedEdx; + }; +} CPUID_EXTENDED_FUNCTION_REGS; + +// CPUID_THERMAL_POWER_MANAGEMENT (6) +typedef union +{ + INT32 AsInt32[4]; + struct + { + CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax; + CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx; + CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx; + UINT32 ReservedEdx; + }; + struct + { + UINT32 Eax; + UINT32 Ebx; + struct + { + UINT32 HardwareCoordinationFeedback : 1; + UINT32 ACNT2 : 1; // See https://en.wikipedia.org/wiki/CPUID + } Ecx; + } Undoc; +} CPUID_THERMAL_POWER_MANAGEMENT_REGS; + +// CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07) +typedef union +{ + INT32 AsInt32[4]; + struct + { + UINT32 Eax; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx; + }; +} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_REGS; + +// CPUID_EXTENDED_STATE (0x0D) +// CPUID_EXTENDED_STATE_MAIN_LEAF (0x00) +typedef union +{ + INT32 AsInt32[4]; + struct + { + CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + }; +} CPUID_EXTENDED_STATE_MAIN_LEAF_REGS; + +// CPUID_EXTENDED_STATE (0x0D) +// CPUID_EXTENDED_STATE_SUB_LEAF (0x01) +typedef union +{ + INT32 AsInt32[4]; + struct + { + CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax; + struct + { + UINT32 XSaveAreaSize; // The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS. + } Ebx; + CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx; + struct + { + UINT32 Edx; // Reports the supported bits of the upper 32 bits of the IA32_XSS MSR.IA32_XSS[n + 32] can be set to 1 only if EDX[n] is 1. + } Edx; + }; +} CPUID_EXTENDED_STATE_SUB_LEAF_EAX_REGS; + +// CPUID_EXTENDED_CPU_SIG (0x80000001) +typedef union +{ + INT32 AsInt32[4]; + struct + { + UINT32 Signature; + UINT32 ReservedEbx; + CPUID_EXTENDED_CPU_SIG_ECX Ecx; + CPUID_EXTENDED_CPU_SIG_EDX Edx; + } Intel; + struct + { + CPUID_AMD_EXTENDED_CPU_SIG_EAX Eax; + CPUID_AMD_EXTENDED_CPU_SIG_EBX Ebx; + CPUID_AMD_EXTENDED_CPU_SIG_ECX Ecx; + CPUID_AMD_EXTENDED_CPU_SIG_EDX Edx; + } Amd; +} CPUID_EXTENDED_CPU_SIG_REGS; + + +// Additional AMD specific CPUID: +// See +// - AMD64 Architecture Programmer’s Manual Volume 2: System Programming (https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/progra…) +// - http://www.flounder.com/cpuid_explorer2.htm#CPUID(0x8000000A) +// - https://www.spinics.net/lists/kvm/msg279165.html +// - https://qemu-devel.nongnu.narkive.com/zgmvxGLq/patch-0-3-svm-feature-suppor… +// - https://github.com/torvalds/linux/blob/28f20a19294da7df158dfca259d0e2b5866b… + +#define CPUID_AMD_SVM_FEATURES 0x8000000A + +typedef union +{ + struct + { + UINT SVMRev : 8; // EAX[7..0] + UINT Reserved : 24; // EAX[31..8] + } Bits; + + UINT32 Uint32; +} CPUID_AMD_SVM_FEATURES_EAX; + +typedef union +{ + struct + { + UINT32 NP : 1; // EDX[0] Nested paging support + UINT32 LbrVirt : 1; // EDX[1] LBR virtualization + UINT32 SVML : 1; // EDX[2] SVM Lock + UINT32 NRIPS : 1; // EDX[3] Next RIP save on VMEXIT + UINT32 TscRateMsr : 1; // EDX[4] MSR based TSC ratio control + UINT32 VmcbClean : 1; // EDX[5] VMCB Clean bits support + UINT32 FlushByAsid : 1; // EDX[6] Flush by ASID support + UINT32 DecodeAssists : 1; // EDX[7] Decode assists support + UINT32 Reserved1 : 2; // EDX[9:8] Reserved + UINT32 PauseFilter : 1; // EDX[10] Pause filter support + UINT32 Reserved2 : 1; // EDX[11] Reserved + UINT32 PauseFilterThreshold : 1; // EDX[12] Pause filter threshold support + UINT32 AVIC : 1; // EDX[13:13] Advanced Virtual Interrupt Controller + UINT32 Unknown14 : 1; // EDX[14] Unknown. Described in AMD doc as X2AVIC, but that was probably a typo, since x2AVIC is bit 18. + UINT32 VMSAVEVirt : 1; // EDX[15] MSAVE and VMLOAD Virtualization + UINT32 VGIF : 1; // EDX[16] Virtual Global-Interrupt Flag + UINT32 GMET : 1; // EDX[17] Guest Mode Execute Trap Extension + UINT32 x2AVIC : 1; // EDX[18] Virtual x2APIC + UINT32 SSSCheck : 1; // EDX[19] AKA SupervisorShadowStack + UINT32 V_SPEC_CTRL : 1; // EDX[20] Virtual SPEC_CTRL + UINT32 ROGPT : 1; // EDX[21] + UINT32 Unknown22 : 1; // EDX[22] + UINT32 HOST_MCE_OVERRIDE : 1; // EDX[23] + UINT32 TLBSYNC : 1; // EDX[24] TLBSYNC instruction can be intercepted + UINT32 VNMI : 1; // EDX[25] NMI Virtualization support + UINT32 IbsVirt : 1; // EDX[26] Instruction Based Sampling Virtualization + UINT32 LVTReadAllowed : 1; // EDX[27] + UINT32 Unknown28 : 1; // EDX[28] + UINT32 BusLockThreshold : 1; // EDX[29] + } Bits; + + UINT32 Uint32; +} CPUID_AMD_SVM_FEATURES_EDX; + +// CPUID_AMD_SVM_FEATURES (0x8000000A) +typedef union +{ + INT32 AsInt32[4]; + struct + { + CPUID_AMD_SVM_FEATURES_EAX Eax; + UINT32 NumberOfSupportedASIDs; + UINT32 Ecx; + CPUID_AMD_SVM_FEATURES_EDX Edx; + }; +} CPUID_AMD_SVM_FEATURES_REGS; diff --git a/sdk/include/reactos/x86x64/Intel/ArchitecturalMsr.h b/sdk/include/reactos/x86x64/Intel/ArchitecturalMsr.h new file mode 100644 index 00000000000..26bc6ba3138 --- /dev/null +++ b/sdk/include/reactos/x86x64/Intel/ArchitecturalMsr.h @@ -0,0 +1,6532 @@ +/** @file + Intel Architectural MSR Definitions. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __INTEL_ARCHITECTURAL_MSR_H__ +#define __INTEL_ARCHITECTURAL_MSR_H__ + +/** + See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H). + + @param ECX MSR_IA32_P5_MC_ADDR (0x00000000) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR); + AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr); + @endcode + @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM. +**/ +#define MSR_IA32_P5_MC_ADDR 0x00000000 + +/** + See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H. + + @param ECX MSR_IA32_P5_MC_TYPE (0x00000001) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE); + AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr); + @endcode + @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM. +**/ +#define MSR_IA32_P5_MC_TYPE 0x00000001 + +/** + See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced + at Display Family / Display Model 0F_03H. + + @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE); + AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr); + @endcode + @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM. +**/ +#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006 + +/** + See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family / + Display Model 05_01H. + + @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER); + AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr); + @endcode + @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM. +**/ +#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010 + +/** + Platform ID (RO) The operating system can use this MSR to determine "slot" + information for the processor and the proper microcode update to load. + Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_PLATFORM_ID (0x00000017) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PLATFORM_ID_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PLATFORM_ID_REGISTER. + + Example usage + @code + MSR_IA32_PLATFORM_ID_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID); + @endcode + @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM. +**/ +#define MSR_IA32_PLATFORM_ID 0x00000017 + +/** + MSR information returned for MSR index #MSR_IA32_PLATFORM_ID +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1 : 32; + UINT32 Reserved2 : 18; + /// + /// [Bits 52:50] Platform Id (RO) Contains information concerning the + /// intended platform for the processor. + /// 52 51 50 + /// -- -- -- + /// 0 0 0 Processor Flag 0. + /// 0 0 1 Processor Flag 1 + /// 0 1 0 Processor Flag 2 + /// 0 1 1 Processor Flag 3 + /// 1 0 0 Processor Flag 4 + /// 1 0 1 Processor Flag 5 + /// 1 1 0 Processor Flag 6 + /// 1 1 1 Processor Flag 7 + /// + UINT32 PlatformId : 3; + UINT32 Reserved3 : 11; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PLATFORM_ID_REGISTER; + +/** + 06_01H. + + @param ECX MSR_IA32_APIC_BASE (0x0000001B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_APIC_BASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_APIC_BASE_REGISTER. + + Example usage + @code + MSR_IA32_APIC_BASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); + AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64); + @endcode + @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM. +**/ +#define MSR_IA32_APIC_BASE 0x0000001B + +/** + MSR information returned for MSR index #MSR_IA32_APIC_BASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1 : 8; + /// + /// [Bit 8] BSP flag (R/W). + /// + UINT32 BSP : 1; + UINT32 Reserved2 : 1; + /// + /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display + /// Model 06_1AH. + /// + UINT32 EXTD : 1; + /// + /// [Bit 11] APIC Global Enable (R/W). + /// + UINT32 EN : 1; + /// + /// [Bits 31:12] APIC Base (R/W). + /// + UINT32 ApicBase : 20; + /// + /// [Bits 63:32] APIC Base (R/W). + /// + UINT32 ApicBaseHi : 32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_APIC_BASE_REGISTER; + +/** + Control Features in Intel 64 Processor (R/W). If any one enumeration + condition for defined bit field holds. + + @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. + + Example usage + @code + MSR_IA32_FEATURE_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL); + AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64); + @endcode + @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM. +**/ +#define MSR_IA32_FEATURE_CONTROL 0x0000003A + +/** + MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from + /// being written, writes to this bit will result in GP(0). Note: Once the + /// Lock bit is set, the contents of this register cannot be modified. + /// Therefore the lock bit must be set after configuring support for Intel + /// Virtualization Technology and prior to transferring control to an + /// option ROM or the OS. Hence, once the Lock bit is set, the entire + /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD + /// is not deasserted. If any one enumeration condition for defined bit + /// field position greater than bit 0 holds. + /// + UINT32 Lock : 1; + /// + /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a + /// system executive to use VMX in conjunction with SMX to support + /// Intel(R) Trusted Execution Technology. BIOS must set this bit only + /// when the CPUID function 1 returns VMX feature flag and SMX feature + /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 && + /// CPUID.01H:ECX[6] = 1. + /// + UINT32 EnableVmxInsideSmx : 1; + /// + /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX + /// for system executive that do not require SMX. BIOS must set this bit + /// only when the CPUID function 1 returns VMX feature flag set (ECX bit + /// 5). If CPUID.01H:ECX[5] = 1. + /// + UINT32 EnableVmxOutsideSmx : 1; + UINT32 Reserved1 : 5; + /// + /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit + /// in the field represents an enable control for a corresponding SENTER + /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If + /// CPUID.01H:ECX[6] = 1. + /// + UINT32 SenterLocalFunctionEnables : 7; + /// + /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable + /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit + /// 6] is set. If CPUID.01H:ECX[6] = 1. + /// + UINT32 SenterGlobalEnable : 1; + UINT32 Reserved2 : 1; + /// + /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to + /// enable runtime reconfiguration of SGX Launch Control via + /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1. + /// + UINT32 SgxLaunchControlEnable : 1; + /// + /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX + /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1. + /// + UINT32 SgxEnable : 1; + UINT32 Reserved3 : 1; + /// + /// [Bit 20] LMCE On (R/WL): When set, system software can program the + /// MSRs associated with LMCE to configure delivery of some machine check + /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1. + /// + UINT32 LmceOn : 1; + UINT32 Reserved4 : 11; + UINT32 Reserved5 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_FEATURE_CONTROL_REGISTER; + +/** + Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H, + ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for + a logical processor. Reset value is Zero. A write to IA32_TSC will modify + the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does + not affect the internal invariant TSC hardware. + + @param ECX MSR_IA32_TSC_ADJUST (0x0000003B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST); + AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr); + @endcode + @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM. +**/ +#define MSR_IA32_TSC_ADJUST 0x0000003B + +/** + BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a + microcode update to be loaded into the processor. See Section 9.11.6, + "Microcode Update Loader." A processor may prevent writing to this MSR when + loading guest states on VM entries or saving guest states on VM exits. + Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = 0; + AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr); + @endcode + @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM. +**/ +#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 + +/** + BIOS Update Signature (RO) Returns the microcode update signature following + the execution of CPUID.01H. A processor may prevent writing to this MSR when + loading guest states on VM entries or saving guest states on VM exits. + Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. + + Example usage + @code + MSR_IA32_BIOS_SIGN_ID_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID); + @endcode + @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM. +**/ +#define MSR_IA32_BIOS_SIGN_ID 0x0000008B + +/** + MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved : 32; + /// + /// [Bits 63:32] Microcode update signature. This field contains the + /// signature of the currently loaded microcode update when read following + /// the execution of the CPUID instruction, function 1. It is required + /// that this register field be pre-loaded with zero prior to executing + /// the CPUID, function 1. If the field remains equal to zero, then there + /// is no microcode update loaded. Another nonzero value will be the + /// signature. + /// + UINT32 MicrocodeUpdateSignature : 32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_BIOS_SIGN_ID_REGISTER; + +/** + IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the + SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the + default value is the digest of Intel's signing key. Read permitted If + CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H): + EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1. + + @param ECX MSR_IA32_SGXLEPUBKEYHASHn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn); + AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr); + @endcode + @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM. + MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM. + MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM. + MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM. + @{ +**/ +#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C +#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D +#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E +#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F +/// @} + +/** + SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] = + 1. + + @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. + + Example usage + @code + MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL); + AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64); + @endcode + @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM. +**/ +#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B + +/** + MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this + /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment + /// (see Section 34.15.6), the dual-monitor treatment cannot be activated + /// if the bit is 0. This bit is cleared when the logical processor is + /// reset. + /// + UINT32 Valid : 1; + UINT32 Reserved1 : 1; + /// + /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If + /// IA32_VMX_MISC[28]. + /// + UINT32 BlockSmi : 1; + UINT32 Reserved2 : 9; + /// + /// [Bits 31:12] MSEG Base (R/W). + /// + UINT32 MsegBase : 20; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_SMM_MONITOR_CTL_REGISTER; + +/** + MSEG header that is located at the physical address specified by the MsegBase + field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER. +**/ +typedef struct { + /// + /// Different processors may use different MSEG revision identifiers. These + /// identifiers enable software to avoid using an MSEG header formatted for + /// one processor on a processor that uses a different format. Software can + /// discover the MSEG revision identifier that a processor uses by reading + /// the VMX capability MSR IA32_VMX_MISC. + // + UINT32 MsegHeaderRevision; + /// + /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field + /// is the IA-32e mode SMM feature bit. It indicates whether the logical + /// processor will be in IA-32e mode after the STM is activated. + /// + UINT32 MonitorFeatures; + UINT32 GdtrLimit; + UINT32 GdtrBaseOffset; + UINT32 CsSelector; + UINT32 EipOffset; + UINT32 EspOffset; + UINT32 Cr3Offset; + /// + /// Pad header so total size is 2KB + /// + UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)]; +} MSEG_HEADER; + +/// +/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER +/// +#define STM_FEATURES_IA32E 0x1 +/// +/// @} +/// + +/** + Base address of the logical processor's SMRAM image (RO, SMM only). If + IA32_VMX_MISC[15]. + + @param ECX MSR_IA32_SMBASE (0x0000009E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_SMBASE); + @endcode + @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM. +**/ +#define MSR_IA32_SMBASE 0x0000009E + +/** + General Performance Counters (R/W). + MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n. + + @param ECX MSR_IA32_PMCn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_PMC0); + AsmWriteMsr64 (MSR_IA32_PMC0, Msr); + @endcode + @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM. + MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM. + MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM. + MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM. + MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM. + MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM. + MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM. + MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM. + @{ +**/ +#define MSR_IA32_PMC0 0x000000C1 +#define MSR_IA32_PMC1 0x000000C2 +#define MSR_IA32_PMC2 0x000000C3 +#define MSR_IA32_PMC3 0x000000C4 +#define MSR_IA32_PMC4 0x000000C5 +#define MSR_IA32_PMC5 0x000000C6 +#define MSR_IA32_PMC6 0x000000C7 +#define MSR_IA32_PMC7 0x000000C8 +/// @} + +/** + TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1. + C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative + to TSC freq.) when the logical processor is in C0. Cleared upon overflow / + wrap-around of IA32_APERF. + + @param ECX MSR_IA32_MPERF (0x000000E7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MPERF); + AsmWriteMsr64 (MSR_IA32_MPERF, Msr); + @endcode + @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM. +**/ +#define MSR_IA32_MPERF 0x000000E7 + +/** + Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = + 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at + the coordinated clock frequency, when the logical processor is in C0. + Cleared upon overflow / wrap-around of IA32_MPERF. + + @param ECX MSR_IA32_APERF (0x000000E8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_APERF); + AsmWriteMsr64 (MSR_IA32_APERF, Msr); + @endcode + @note MSR_IA32_APERF is defined as IA32_APERF in SDM. +**/ +#define MSR_IA32_APERF 0x000000E8 + +/** + MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.". + Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_MTRRCAP (0x000000FE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MTRRCAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MTRRCAP_REGISTER. + + Example usage + @code + MSR_IA32_MTRRCAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP); + @endcode + @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM. +**/ +#define MSR_IA32_MTRRCAP 0x000000FE + +/** + MSR information returned for MSR index #MSR_IA32_MTRRCAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] VCNT: The number of variable memory type ranges in the + /// processor. + /// + UINT32 VCNT : 8; + /// + /// [Bit 8] Fixed range MTRRs are supported when set. + /// + UINT32 FIX : 1; + UINT32 Reserved1 : 1; + /// + /// [Bit 10] WC Supported when set. + /// + UINT32 WC : 1; + /// + /// [Bit 11] SMRR Supported when set. + /// + UINT32 SMRR : 1; + UINT32 Reserved2 : 20; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MTRRCAP_REGISTER; + +/** + SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_SYSENTER_CS (0x00000174) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_SYSENTER_CS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_SYSENTER_CS_REGISTER. + + Example usage + @code + MSR_IA32_SYSENTER_CS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS); + AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64); + @endcode + @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM. +**/ +#define MSR_IA32_SYSENTER_CS 0x00000174 + +/** + MSR information returned for MSR index #MSR_IA32_SYSENTER_CS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] CS Selector. + /// + UINT32 CS : 16; + UINT32 Reserved1 : 16; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_SYSENTER_CS_REGISTER; + +/** + SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_SYSENTER_ESP (0x00000175) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP); + AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr); + @endcode + @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM. +**/ +#define MSR_IA32_SYSENTER_ESP 0x00000175 + +/** + SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_SYSENTER_EIP (0x00000176) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP); + AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr); + @endcode + @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM. +**/ +#define MSR_IA32_SYSENTER_EIP 0x00000176 + +/** + Global Machine Check Capability (RO). Introduced at Display Family / Display + Model 06_01H. + + @param ECX MSR_IA32_MCG_CAP (0x00000179) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MCG_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MCG_CAP_REGISTER. + + Example usage + @code + MSR_IA32_MCG_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); + @endcode + @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM. +**/ +#define MSR_IA32_MCG_CAP 0x00000179 + +/** + MSR information returned for MSR index #MSR_IA32_MCG_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Count: Number of reporting banks. + /// + UINT32 Count : 8; + /// + /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set. + /// + UINT32 MCG_CTL_P : 1; + /// + /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present + /// if this bit is set. + /// + UINT32 MCG_EXT_P : 1; + /// + /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present. + /// Introduced at Display Family / Display Model 06_01H. + /// + UINT32 MCP_CMCI_P : 1; + /// + /// [Bit 11] MCG_TES_P: Threshold-based error status register are present + /// if this bit is set. + /// + UINT32 MCG_TES_P : 1; + UINT32 Reserved1 : 4; + /// + /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state + /// registers present. + /// + UINT32 MCG_EXT_CNT : 8; + /// + /// [Bit 24] MCG_SER_P: The processor supports software error recovery if + /// this bit is set. + /// + UINT32 MCG_SER_P : 1; + UINT32 Reserved2 : 1; + /// + /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform + /// firmware to be invoked when an error is detected so that it may + /// provide additional platform specific information in an ACPI format + /// "Generic Error Data Entry" that augments the data included in machine + /// check bank registers. Introduced at Display Family / Display Model + /// 06_3EH. + /// + UINT32 MCG_ELOG_P : 1; + /// + /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended + /// state in IA32_MCG_STATUS and associated MSR necessary to configure + /// Local Machine Check Exception (LMCE). Introduced at Display Family / + /// Display Model 06_3EH. + /// + UINT32 MCG_LMCE_P : 1; + UINT32 Reserved3 : 4; + UINT32 Reserved4 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MCG_CAP_REGISTER; + +/** + Global Machine Check Status (R/W0). Introduced at Display Family / Display + Model 06_01H. + + @param ECX MSR_IA32_MCG_STATUS (0x0000017A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MCG_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MCG_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_MCG_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS); + AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64); + @endcode + @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM. +**/ +#define MSR_IA32_MCG_STATUS 0x0000017A + +/** + MSR information returned for MSR index #MSR_IA32_MCG_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display + /// Model 06_01H. + /// + UINT32 RIPV : 1; + /// + /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display + /// Model 06_01H. + /// + UINT32 EIPV : 1; + /// + /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family + /// / Display Model 06_01H. + /// + UINT32 MCIP : 1; + /// + /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1. + /// + UINT32 LMCE_S : 1; + UINT32 Reserved1 : 28; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MCG_STATUS_REGISTER; + +/** + Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1. + + @param ECX MSR_IA32_MCG_CTL (0x0000017B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL); + AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr); + @endcode + @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM. +**/ +#define MSR_IA32_MCG_CTL 0x0000017B + +/** + Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n. + + @param ECX MSR_IA32_PERFEVTSELn + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERFEVTSEL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERFEVTSEL_REGISTER. + + Example usage + @code + MSR_IA32_PERFEVTSEL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0); + AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64); + @endcode + @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. + MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. + MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM. + MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM. + @{ +**/ +#define MSR_IA32_PERFEVTSEL0 0x00000186 +#define MSR_IA32_PERFEVTSEL1 0x00000187 +#define MSR_IA32_PERFEVTSEL2 0x00000188 +#define MSR_IA32_PERFEVTSEL3 0x00000189 +/// @} + +/** + MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to + #MSR_IA32_PERFEVTSEL3 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Event Select: Selects a performance event logic unit. + /// + UINT32 EventSelect : 8; + /// + /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to + /// detect on the selected event logic. + /// + UINT32 UMASK : 8; + /// + /// [Bit 16] USR: Counts while in privilege level is not ring 0. + /// + UINT32 USR : 1; + /// + /// [Bit 17] OS: Counts while in privilege level is ring 0. + /// + UINT32 OS : 1; + /// + /// [Bit 18] Edge: Enables edge detection if set. + /// + UINT32 E : 1; + /// + /// [Bit 19] PC: enables pin control. + /// + UINT32 PC : 1; + /// + /// [Bit 20] INT: enables interrupt on counter overflow. + /// + UINT32 INT : 1; + /// + /// [Bit 21] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. + /// + UINT32 ANY : 1; + /// + /// [Bit 22] EN: enables the corresponding performance counter to commence + /// counting when this bit is set. + /// + UINT32 EN : 1; + /// + /// [Bit 23] INV: invert the CMASK. + /// + UINT32 INV : 1; + /// + /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding + /// performance counter increments each cycle if the event count is + /// greater than or equal to the CMASK. + /// + UINT32 CMASK : 8; + UINT32 Reserved : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERFEVTSEL_REGISTER; + +/** + Current performance state(P-State) operating point (RO). Introduced at + Display Family / Display Model 0F_03H. + + @param ECX MSR_IA32_PERF_STATUS (0x00000198) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_PERF_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS); + @endcode + @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM. +**/ +#define MSR_IA32_PERF_STATUS 0x00000198 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Current performance State Value. + /// + UINT32 State : 16; + UINT32 Reserved1 : 16; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_STATUS_REGISTER; + +/** + (R/W). Introduced at Display Family / Display Model 0F_03H. + + @param ECX MSR_IA32_PERF_CTL (0x00000199) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_CTL_REGISTER. + + Example usage + @code + MSR_IA32_PERF_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL); + AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM. +**/ +#define MSR_IA32_PERF_CTL 0x00000199 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Target performance State Value. + /// + UINT32 TargetState : 16; + UINT32 Reserved1 : 16; + /// + /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH + /// (Mobile only). + /// + UINT32 IDA : 1; + UINT32 Reserved2 : 31; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_CTL_REGISTER; + +/** + Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled + Clock Modulation.". If CPUID.01H:EDX[22] = 1. + + @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER. + + Example usage + @code + MSR_IA32_CLOCK_MODULATION_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION); + AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64); + @endcode + @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM. +**/ +#define MSR_IA32_CLOCK_MODULATION 0x0000019A + +/** + MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If + /// CPUID.06H:EAX[5] = 1. + /// + UINT32 ExtendedOnDemandClockModulationDutyCycle : 1; + /// + /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded + /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1. + /// + UINT32 OnDemandClockModulationDutyCycle : 3; + /// + /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation. + /// If CPUID.01H:EDX[22] = 1. + /// + UINT32 OnDemandClockModulationEnable : 1; + UINT32 Reserved1 : 27; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_CLOCK_MODULATION_REGISTER; + +/** + Thermal Interrupt Control (R/W) Enables and disables the generation of an + interrupt on temperature transitions detected with the processor's thermal + sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.". + If CPUID.01H:EDX[22] = 1 + + @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER. + + Example usage + @code + MSR_IA32_THERM_INTERRUPT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT); + AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64); + @endcode + @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM. +**/ +#define MSR_IA32_THERM_INTERRUPT 0x0000019B + +/** + MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 HighTempEnable : 1; + /// + /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 LowTempEnable : 1; + /// + /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 PROCHOT_Enable : 1; + /// + /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 FORCEPR_Enable : 1; + /// + /// [Bit 4] Critical Temperature Interrupt Enable. + /// If CPUID.01H:EDX[22] = 1. + /// + UINT32 CriticalTempEnable : 1; + UINT32 Reserved1 : 3; + /// + /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1. + /// + UINT32 Threshold1 : 7; + /// + /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 Threshold1Enable : 1; + /// + /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1. + /// + UINT32 Threshold2 : 7; + /// + /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 Threshold2Enable : 1; + /// + /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1. + /// + UINT32 PowerLimitNotificationEnable : 1; + UINT32 Reserved2 : 7; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_THERM_INTERRUPT_REGISTER; + +/** + Thermal Status Information (RO) Contains status information about the + processor's thermal sensor and automatic thermal monitoring facilities. See + Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1. + + @param ECX MSR_IA32_THERM_STATUS (0x0000019C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_THERM_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_THERM_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_THERM_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS); + @endcode + @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM. +**/ +#define MSR_IA32_THERM_STATUS 0x0000019C + +/** + MSR information returned for MSR index #MSR_IA32_THERM_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1. + /// + UINT32 ThermalStatus : 1; + /// + /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1. + /// + UINT32 ThermalStatusLog : 1; + /// + /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1. + /// + UINT32 PROCHOT_FORCEPR_Event : 1; + /// + /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1. + /// + UINT32 PROCHOT_FORCEPR_Log : 1; + /// + /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1. + /// + UINT32 CriticalTempStatus : 1; + /// + /// [Bit 5] Critical Temperature Status log (R/WC0). + /// If CPUID.01H:EDX[22] = 1. + /// + UINT32 CriticalTempStatusLog : 1; + /// + /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1. + /// + UINT32 ThermalThreshold1Status : 1; + /// + /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1. + /// + UINT32 ThermalThreshold1Log : 1; + /// + /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1. + /// + UINT32 ThermalThreshold2Status : 1; + /// + /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1. + /// + UINT32 ThermalThreshold2Log : 1; + /// + /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1. + /// + UINT32 PowerLimitStatus : 1; + /// + /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1. + /// + UINT32 PowerLimitLog : 1; + /// + /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1. + /// + UINT32 CurrentLimitStatus : 1; + /// + /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1. + /// + UINT32 CurrentLimitLog : 1; + /// + /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1. + /// + UINT32 CrossDomainLimitStatus : 1; + /// + /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1. + /// + UINT32 CrossDomainLimitLog : 1; + /// + /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1. + /// + UINT32 DigitalReadout : 7; + UINT32 Reserved1 : 4; + /// + /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] = + /// 1. + /// + UINT32 ResolutionInDegreesCelsius : 4; + /// + /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1. + /// + UINT32 ReadingValid : 1; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_THERM_STATUS_REGISTER; + +/** + Enable Misc. Processor Features (R/W) Allows a variety of processor + functions to be enabled and disabled. + + @param ECX MSR_IA32_MISC_ENABLE (0x000001A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MISC_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MISC_ENABLE_REGISTER. + + Example usage + @code + MSR_IA32_MISC_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE); + AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64); + @endcode + @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. +**/ +#define MSR_IA32_MISC_ENABLE 0x000001A0 + +/** + MSR information returned for MSR index #MSR_IA32_MISC_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for + /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings + /// are disabled. Introduced at Display Family / Display Model 0F_0H. + /// + UINT32 FastStrings : 1; + UINT32 Reserved1 : 2; + /// + /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting + /// this bit enables the thermal control circuit (TCC) portion of the + /// Intel Thermal Monitor feature. This allows the processor to + /// automatically reduce power consumption in response to TCC activation. + /// 0 = Disabled. Note: In some products clearing this bit might be + /// ignored in critical thermal conditions, and TM1, TM2 and adaptive + /// thermal throttling will still be activated. The default value of this + /// field varies with product. See respective tables where default value is + /// listed. Introduced at Display Family / Display Model 0F_0H. + /// + UINT32 AutomaticThermalControlCircuit : 1; + UINT32 Reserved2 : 3; + /// + /// [Bit 7] Performance Monitoring Available (R) 1 = Performance + /// monitoring enabled 0 = Performance monitoring disabled. Introduced at + /// Display Family / Display Model 0F_0H. + /// + UINT32 PerformanceMonitoring : 1; + UINT32 Reserved3 : 3; + /// + /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't + /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at + /// Display Family / Display Model 0F_0H. + /// + UINT32 BTS : 1; + /// + /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 = + /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display + /// Family / Display Model 06_0FH. + /// + UINT32 PEBS : 1; + UINT32 Reserved4 : 3; + /// + /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced + /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep + /// Technology enabled. If CPUID.01H: ECX[7] =1. + /// + UINT32 EIST : 1; + UINT32 Reserved5 : 1; + /// + /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the + /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This + /// indicates that MONITOR/MWAIT are not supported. Software attempts to + /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit + /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit + /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit + /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it + /// in the default state. Writing this bit when the SSE3 feature flag is + /// set to 0 may generate a #GP exception. Introduced at Display Family / + /// Display Model 0F_03H. + /// + UINT32 MONITOR : 1; + UINT32 Reserved6 : 3; + /// + /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H + /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup + /// question that allows users to specify when the installed OS does not + /// support CPUID functions greater than 2. Before setting this bit, BIOS + /// must execute the CPUID.0H and examine the maximum value returned in + /// EAX[7:0]. If the maximum value is greater than 2, this bit is + /// supported. Otherwise, this bit is not supported. Setting this bit when + /// the maximum value is not greater than 2 may generate a #GP exception. + /// Setting this bit may cause unexpected behavior in software that + /// depends on the availability of CPUID leaves greater than 2. Introduced + /// at Display Family / Display Model 0F_03H. + /// + UINT32 LimitCpuidMaxval : 1; + /// + /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are + /// disabled. xTPR messages are optional messages that allow the processor + /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1. + /// + UINT32 xTPR_Message_Disable : 1; + UINT32 Reserved7 : 8; + UINT32 Reserved8 : 2; + /// + /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit + /// feature (XD Bit) is disabled and the XD Bit extended feature flag will + /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the + /// Execute Disable Bit feature (if available) allows the OS to enable PAE + /// paging and take advantage of data only pages. BIOS must not alter the + /// contents of this bit location, if XD bit is not supported. Writing + /// this bit to 1 when the XD Bit extended feature flag is set to 0 may + /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1. + /// + UINT32 XD : 1; + UINT32 Reserved9 : 29; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MISC_ENABLE_REGISTER; + +/** + Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1. + + @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER. + + Example usage + @code + MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS); + AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64); + @endcode + @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM. +**/ +#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0 + +/** + MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest + /// performance. 15 indicates preference to maximize energy saving. + /// + UINT32 PowerPolicyPreference : 4; + UINT32 Reserved1 : 28; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_ENERGY_PERF_BIAS_REGISTER; + +/** + Package Thermal Status Information (RO) Contains status information about + the package's thermal sensor. See Section 14.8, "Package Level Thermal + Management.". If CPUID.06H: EAX[6] = 1. + + @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS); + @endcode + @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM. +**/ +#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1 + +/** + MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Pkg Thermal Status (RO):. + /// + UINT32 ThermalStatus : 1; + /// + /// [Bit 1] Pkg Thermal Status Log (R/W):. + /// + UINT32 ThermalStatusLog : 1; + /// + /// [Bit 2] Pkg PROCHOT # event (RO). + /// + UINT32 PROCHOT_Event : 1; + /// + /// [Bit 3] Pkg PROCHOT # log (R/WC0). + /// + UINT32 PROCHOT_Log : 1; + /// + /// [Bit 4] Pkg Critical Temperature Status (RO). + /// + UINT32 CriticalTempStatus : 1; + /// + /// [Bit 5] Pkg Critical Temperature Status log (R/WC0). + /// + UINT32 CriticalTempStatusLog : 1; + /// + /// [Bit 6] Pkg Thermal Threshold #1 Status (RO). + /// + UINT32 ThermalThreshold1Status : 1; + /// + /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0). + /// + UINT32 ThermalThreshold1Log : 1; + /// + /// [Bit 8] Pkg Thermal Threshold #2 Status (RO). + /// + UINT32 ThermalThreshold2Status : 1; + /// + /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0). + /// + UINT32 ThermalThreshold2Log : 1; + /// + /// [Bit 10] Pkg Power Limitation Status (RO). + /// + UINT32 PowerLimitStatus : 1; + /// + /// [Bit 11] Pkg Power Limitation log (R/WC0). + /// + UINT32 PowerLimitLog : 1; + UINT32 Reserved1 : 4; + /// + /// [Bits 22:16] Pkg Digital Readout (RO). + /// + UINT32 DigitalReadout : 7; + UINT32 Reserved2 : 9; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER; + +/** + Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of + an interrupt on temperature transitions detected with the package's thermal + sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H: + EAX[6] = 1. + + @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER. + + Example usage + @code + MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT); + AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64); + @endcode + @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM. +**/ +#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2 + +/** + MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Pkg High-Temperature Interrupt Enable. + /// + UINT32 HighTempEnable : 1; + /// + /// [Bit 1] Pkg Low-Temperature Interrupt Enable. + /// + UINT32 LowTempEnable : 1; + /// + /// [Bit 2] Pkg PROCHOT# Interrupt Enable. + /// + UINT32 PROCHOT_Enable : 1; + UINT32 Reserved1 : 1; + /// + /// [Bit 4] Pkg Overheat Interrupt Enable. + /// + UINT32 OverheatEnable : 1; + UINT32 Reserved2 : 3; + /// + /// [Bits 14:8] Pkg Threshold #1 Value. + /// + UINT32 Threshold1 : 7; + /// + /// [Bit 15] Pkg Threshold #1 Interrupt Enable. + /// + UINT32 Threshold1Enable : 1; + /// + /// [Bits 22:16] Pkg Threshold #2 Value. + /// + UINT32 Threshold2 : 7; + /// + /// [Bit 23] Pkg Threshold #2 Interrupt Enable. + /// + UINT32 Threshold2Enable : 1; + /// + /// [Bit 24] Pkg Power Limit Notification Enable. + /// + UINT32 PowerLimitNotificationEnable : 1; + UINT32 Reserved3 : 7; + UINT32 Reserved4 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER; + +/** + Trace/Profile Resource Control (R/W). Introduced at Display Family / Display + Model 06_0EH. + + @param ECX MSR_IA32_DEBUGCTL (0x000001D9) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_DEBUGCTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_DEBUGCTL_REGISTER. + + Example usage + @code + MSR_IA32_DEBUGCTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL); + AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64); + @endcode + @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM. +**/ +#define MSR_IA32_DEBUGCTL 0x000001D9 + +/** + MSR information returned for MSR index #MSR_IA32_DEBUGCTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a + /// running trace of the most recent branches taken by the processor in + /// the LBR stack. Introduced at Display Family / Display Model 06_01H. + /// + UINT32 LBR : 1; + /// + /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat + /// EFLAGS.TF as single-step on branches instead of single-step on + /// instructions. Introduced at Display Family / Display Model 06_01H. + /// + UINT32 BTF : 1; + UINT32 Reserved1 : 4; + /// + /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be + /// sent. Introduced at Display Family / Display Model 06_0EH. + /// + UINT32 TR : 1; + /// + /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to + /// be logged in a BTS buffer. Introduced at Display Family / Display + /// Model 06_0EH. + /// + UINT32 BTS : 1; + /// + /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular + /// fashion. When this bit is set, an interrupt is generated by the BTS + /// facility when the BTS buffer is full. Introduced at Display Family / + /// Display Model 06_0EH. + /// + UINT32 BTINT : 1; + /// + /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0. + /// Introduced at Display Family / Display Model 06_0FH. + /// + UINT32 BTS_OFF_OS : 1; + /// + /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0. + /// Introduced at Display Family / Display Model 06_0FH. + /// + UINT32 BTS_OFF_USR : 1; + /// + /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a + /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 FREEZE_LBRS_ON_PMI : 1; + /// + /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the + /// global counter control MSR are frozen (address 38FH) on a PMI request. + /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 FREEZE_PERFMON_ON_PMI : 1; + /// + /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to + /// receive and generate PMI on behalf of the uncore. Introduced at + /// Display Family / Display Model 06_1AH. + /// + UINT32 ENABLE_UNCORE_PMI : 1; + /// + /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace + /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1. + /// + UINT32 FREEZE_WHILE_SMM : 1; + /// + /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If + /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1). + /// + UINT32 RTM_DEBUG : 1; + UINT32 Reserved2 : 16; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_DEBUGCTL_REGISTER; + +/** + SMRR Base Address (Writeable only in SMM) Base address of SMM memory range. + If IA32_MTRRCAP.SMRR[11] = 1. + + @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER. + + Example usage + @code + MSR_IA32_SMRR_PHYSBASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE); + AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64); + @endcode + @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM. +**/ +#define MSR_IA32_SMRR_PHYSBASE 0x000001F2 + +/** + MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Type. Specifies memory type of the range. + /// + UINT32 Type : 8; + UINT32 Reserved1 : 4; + /// + /// [Bits 31:12] PhysBase. SMRR physical Base Address. + /// + UINT32 PhysBase : 20; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_SMRR_PHYSBASE_REGISTER; + +/** + SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If + IA32_MTRRCAP[SMRR] = 1. + + @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER. + + Example usage + @code + MSR_IA32_SMRR_PHYSMASK_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK); + AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64); + @endcode + @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM. +**/ +#define MSR_IA32_SMRR_PHYSMASK 0x000001F3 + +/** + MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1 : 11; + /// + /// [Bit 11] Valid Enable range mask. + /// + UINT32 Valid : 1; + /// + /// [Bits 31:12] PhysMask SMRR address range mask. + /// + UINT32 PhysMask : 20; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_SMRR_PHYSMASK_REGISTER; + +/** + DCA Capability (R). If CPUID.01H: ECX[18] = 1. + + @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP); + @endcode + @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM. +**/ +#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8 + +/** + If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1. + + @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP); + AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr); + @endcode + @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM. +**/ +#define MSR_IA32_CPU_DCA_CAP 0x000001F9 + +/** + DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1. + + @param ECX MSR_IA32_DCA_0_CAP (0x000001FA) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_DCA_0_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_DCA_0_CAP_REGISTER. + + Example usage + @code + MSR_IA32_DCA_0_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP); + AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64); + @endcode + @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM. +**/ +#define MSR_IA32_DCA_0_CAP 0x000001FA + +/** + MSR information returned for MSR index #MSR_IA32_DCA_0_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no + /// defeatures are set. + /// + UINT32 DCA_ACTIVE : 1; + /// + /// [Bits 2:1] TRANSACTION. + /// + UINT32 TRANSACTION : 2; + /// + /// [Bits 6:3] DCA_TYPE. + /// + UINT32 DCA_TYPE : 4; + /// + /// [Bits 10:7] DCA_QUEUE_SIZE. + /// + UINT32 DCA_QUEUE_SIZE : 4; + UINT32 Reserved1 : 2; + /// + /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW + /// side-effect. + /// + UINT32 DCA_DELAY : 4; + UINT32 Reserved2 : 7; + /// + /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit. + /// + UINT32 SW_BLOCK : 1; + UINT32 Reserved3 : 1; + /// + /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1). + /// + UINT32 HW_BLOCK : 1; + UINT32 Reserved4 : 5; + UINT32 Reserved5 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_DCA_0_CAP_REGISTER; + +/** + MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". + If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n. + + @param ECX MSR_IA32_MTRR_PHYSBASEn + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER. + + Example usage + @code + MSR_IA32_MTRR_PHYSBASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0); + AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64); + @endcode + @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. + MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. + MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. + MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. + MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. + MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. + MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. + MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. + MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. + MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM. + @{ +**/ +#define MSR_IA32_MTRR_PHYSBASE0 0x00000200 +#define MSR_IA32_MTRR_PHYSBASE1 0x00000202 +#define MSR_IA32_MTRR_PHYSBASE2 0x00000204 +#define MSR_IA32_MTRR_PHYSBASE3 0x00000206 +#define MSR_IA32_MTRR_PHYSBASE4 0x00000208 +#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A +#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C +#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E +#define MSR_IA32_MTRR_PHYSBASE8 0x00000210 +#define MSR_IA32_MTRR_PHYSBASE9 0x00000212 +/// @} + +/** + MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to + #MSR_IA32_MTRR_PHYSBASE9 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Type. Specifies memory type of the range. + /// + UINT32 Type : 8; + UINT32 Reserved1 : 4; + /// + /// [Bits 31:12] PhysBase. MTRR physical Base Address. + /// + UINT32 PhysBase : 20; + /// + /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address. + /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the + /// maximum physical address range supported by the processor. It is + /// reported by CPUID leaf function 80000008H. If CPUID does not support + /// leaf 80000008H, the processor supports 36-bit physical address size, + /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved. + /// + UINT32 PhysBaseHi : 32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MTRR_PHYSBASE_REGISTER; + +/** + MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". + If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n. + + @param ECX MSR_IA32_MTRR_PHYSMASKn + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER. + + Example usage + @code + MSR_IA32_MTRR_PHYSMASK_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0); + AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64); + @endcode + @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. + MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. + MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. + MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. + MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. + MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. + MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. + MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. + MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. + MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM. + @{ +**/ +#define MSR_IA32_MTRR_PHYSMASK0 0x00000201 +#define MSR_IA32_MTRR_PHYSMASK1 0x00000203 +#define MSR_IA32_MTRR_PHYSMASK2 0x00000205 +#define MSR_IA32_MTRR_PHYSMASK3 0x00000207 +#define MSR_IA32_MTRR_PHYSMASK4 0x00000209 +#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B +#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D +#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F +#define MSR_IA32_MTRR_PHYSMASK8 0x00000211 +#define MSR_IA32_MTRR_PHYSMASK9 0x00000213 +/// @} + +/** + MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to + #MSR_IA32_MTRR_PHYSMASK9 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1 : 11; + /// + /// [Bit 11] Valid Enable range mask. + /// + UINT32 V : 1; + /// + /// [Bits 31:12] PhysMask. MTRR address range mask. + /// + UINT32 PhysMask : 20; + /// + /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask. + /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the + /// maximum physical address range supported by the processor. It is + /// reported by CPUID leaf function 80000008H. If CPUID does not support + /// leaf 80000008H, the processor supports 36-bit physical address size, + /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved. + /// + UINT32 PhysMaskHi : 32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MTRR_PHYSMASK_REGISTER; + +/** + MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX64K_00000 0x00000250 + +/** + MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX16K_80000 0x00000258 + +/** + MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259 + +/** + See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268 + +/** + MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269 + +/** + MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A + +/** + MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B + +/** + MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C + +/** + MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D + +/** + MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E + +/** + MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F + +/** + IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1. + + @param ECX MSR_IA32_PAT (0x00000277) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PAT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PAT_REGISTER. + + Example usage + @code + MSR_IA32_PAT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT); + AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64); + @endcode + @note MSR_IA32_PAT is defined as IA32_PAT in SDM. +**/ +#define MSR_IA32_PAT 0x00000277 + +/** + MSR information returned for MSR index #MSR_IA32_PAT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] PA0. + /// + UINT32 PA0 : 3; + UINT32 Reserved1 : 5; + /// + /// [Bits 10:8] PA1. + /// + UINT32 PA1 : 3; + UINT32 Reserved2 : 5; + /// + /// [Bits 18:16] PA2. + /// + UINT32 PA2 : 3; + UINT32 Reserved3 : 5; + /// + /// [Bits 26:24] PA3. + /// + UINT32 PA3 : 3; + UINT32 Reserved4 : 5; + /// + /// [Bits 34:32] PA4. + /// + UINT32 PA4 : 3; + UINT32 Reserved5 : 5; + /// + /// [Bits 42:40] PA5. + /// + UINT32 PA5 : 3; + UINT32 Reserved6 : 5; + /// + /// [Bits 50:48] PA6. + /// + UINT32 PA6 : 3; + UINT32 Reserved7 : 5; + /// + /// [Bits 58:56] PA7. + /// + UINT32 PA7 : 3; + UINT32 Reserved8 : 5; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PAT_REGISTER; + +/** + Provides the programming interface to use corrected MC error signaling + capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n. + + @param ECX MSR_IA32_MCn_CTL2 + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MC_CTL2_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MC_CTL2_REGISTER. + + Example usage + @code + MSR_IA32_MC_CTL2_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2); + AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64); + @endcode + @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. + MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. + MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. + MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. + MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. + MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. + MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. + MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. + MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. + MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. + MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. + MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. + MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. + MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. + MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. + MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. + MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. + MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. + MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. + MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. + MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. + MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. + MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. + MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. + MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. + MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. + MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. + MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. + MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. + MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. + MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. + MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM. + @{ +**/ +#define MSR_IA32_MC0_CTL2 0x00000280 +#define MSR_IA32_MC1_CTL2 0x00000281 +#define MSR_IA32_MC2_CTL2 0x00000282 +#define MSR_IA32_MC3_CTL2 0x00000283 +#define MSR_IA32_MC4_CTL2 0x00000284 +#define MSR_IA32_MC5_CTL2 0x00000285 +#define MSR_IA32_MC6_CTL2 0x00000286 +#define MSR_IA32_MC7_CTL2 0x00000287 +#define MSR_IA32_MC8_CTL2 0x00000288 +#define MSR_IA32_MC9_CTL2 0x00000289 +#define MSR_IA32_MC10_CTL2 0x0000028A +#define MSR_IA32_MC11_CTL2 0x0000028B +#define MSR_IA32_MC12_CTL2 0x0000028C +#define MSR_IA32_MC13_CTL2 0x0000028D +#define MSR_IA32_MC14_CTL2 0x0000028E +#define MSR_IA32_MC15_CTL2 0x0000028F +#define MSR_IA32_MC16_CTL2 0x00000290 +#define MSR_IA32_MC17_CTL2 0x00000291 +#define MSR_IA32_MC18_CTL2 0x00000292 +#define MSR_IA32_MC19_CTL2 0x00000293 +#define MSR_IA32_MC20_CTL2 0x00000294 +#define MSR_IA32_MC21_CTL2 0x00000295 +#define MSR_IA32_MC22_CTL2 0x00000296 +#define MSR_IA32_MC23_CTL2 0x00000297 +#define MSR_IA32_MC24_CTL2 0x00000298 +#define MSR_IA32_MC25_CTL2 0x00000299 +#define MSR_IA32_MC26_CTL2 0x0000029A +#define MSR_IA32_MC27_CTL2 0x0000029B +#define MSR_IA32_MC28_CTL2 0x0000029C +#define MSR_IA32_MC29_CTL2 0x0000029D +#define MSR_IA32_MC30_CTL2 0x0000029E +#define MSR_IA32_MC31_CTL2 0x0000029F +/// @} + +/** + MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2 + to #MSR_IA32_MC31_CTL2 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 14:0] Corrected error count threshold. + /// + UINT32 CorrectedErrorCountThreshold : 15; + UINT32 Reserved1 : 15; + /// + /// [Bit 30] CMCI_EN. + /// + UINT32 CMCI_EN : 1; + UINT32 Reserved2 : 1; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MC_CTL2_REGISTER; + +/** + MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER. + + Example usage + @code + MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE); + AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64); + @endcode + @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM. +**/ +#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF + +/** + MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Default Memory Type. + /// + UINT32 Type : 3; + UINT32 Reserved1 : 7; + /// + /// [Bit 10] Fixed Range MTRR Enable. + /// + UINT32 FE : 1; + /// + /// [Bit 11] MTRR Enable. + /// + UINT32 E : 1; + UINT32 Reserved2 : 20; + UINT32 Reserved3 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MTRR_DEF_TYPE_REGISTER; + +/** + Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If + CPUID.0AH: EDX[4:0] > 0. + + @param ECX MSR_IA32_FIXED_CTR0 (0x00000309) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0); + AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr); + @endcode + @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM. +**/ +#define MSR_IA32_FIXED_CTR0 0x00000309 + +/** + Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If + CPUID.0AH: EDX[4:0] > 1. + + @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1); + AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr); + @endcode + @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM. +**/ +#define MSR_IA32_FIXED_CTR1 0x0000030A + +/** + Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If + CPUID.0AH: EDX[4:0] > 2. + + @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2); + AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr); + @endcode + @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM. +**/ +#define MSR_IA32_FIXED_CTR2 0x0000030B + +/** + RO. If CPUID.01H: ECX[15] = 1. + + @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER. + + Example usage + @code + MSR_IA32_PERF_CAPABILITIES_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES); + AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM. +**/ +#define MSR_IA32_PERF_CAPABILITIES 0x00000345 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 5:0] LBR format. + /// + UINT32 LBR_FMT : 6; + /// + /// [Bit 6] PEBS Trap. + /// + UINT32 PEBS_TRAP : 1; + /// + /// [Bit 7] PEBSSaveArchRegs. + /// + UINT32 PEBS_ARCH_REG : 1; + /// + /// [Bits 11:8] PEBS Record Format. + /// + UINT32 PEBS_REC_FMT : 4; + /// + /// [Bit 12] 1: Freeze while SMM is supported. + /// + UINT32 SMM_FREEZE : 1; + /// + /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx. + /// + UINT32 FW_WRITE : 1; + UINT32 Reserved1 : 18; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_CAPABILITIES_REGISTER; + +/** + Fixed-Function Performance Counter Control (R/W) Counter increments while + the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with + the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0] + > 1. + + @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER. + + Example usage + @code + MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL); + AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64); + @endcode + @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM. +**/ +#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D + +/** + MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0. + /// + UINT32 EN0_OS : 1; + /// + /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0. + /// + UINT32 EN0_Usr : 1; + /// + /// [Bit 2] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. + /// + UINT32 AnyThread0 : 1; + /// + /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows. + /// + UINT32 EN0_PMI : 1; + /// + /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0. + /// + UINT32 EN1_OS : 1; + /// + /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0. + /// + UINT32 EN1_Usr : 1; + /// + /// [Bit 6] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. + /// + UINT32 AnyThread1 : 1; + /// + /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows. + /// + UINT32 EN1_PMI : 1; + /// + /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0. + /// + UINT32 EN2_OS : 1; + /// + /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0. + /// + UINT32 EN2_Usr : 1; + /// + /// [Bit 10] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. + /// + UINT32 AnyThread2 : 1; + /// + /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows. + /// + UINT32 EN2_PMI : 1; + UINT32 Reserved1 : 20; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_FIXED_CTR_CTRL_REGISTER; + +/** + Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0. + + @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS); + @endcode + @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH: + /// EAX[15:8] > 0. + /// + UINT32 Ovf_PMC0 : 1; + /// + /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH: + /// EAX[15:8] > 1. + /// + UINT32 Ovf_PMC1 : 1; + /// + /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH: + /// EAX[15:8] > 2. + /// + UINT32 Ovf_PMC2 : 1; + /// + /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH: + /// EAX[15:8] > 3. + /// + UINT32 Ovf_PMC3 : 1; + UINT32 Reserved1 : 28; + /// + /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If + /// CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 Ovf_FixedCtr0 : 1; + /// + /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If + /// CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 Ovf_FixedCtr1 : 1; + /// + /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If + /// CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 Ovf_FixedCtr2 : 1; + UINT32 Reserved2 : 20; + /// + /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory + /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) + /// && IA32_RTIT_CTL.ToPA = 1. + /// + UINT32 Trace_ToPA_PMI : 1; + UINT32 Reserved3 : 2; + /// + /// [Bit 58] LBR_Frz: LBRs are frozen due to - + /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If + /// CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 LBR_Frz : 1; + /// + /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due + /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU + /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 CTR_Frz : 1; + /// + /// [Bit 60] ASCI: Data in the performance counters in the core PMU may + /// include contributions from the direct or indirect operation intel SGX + /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1. + /// + UINT32 ASCI : 1; + /// + /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH: + /// EAX[7:0] > 2. + /// + UINT32 Ovf_Uncore : 1; + /// + /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH: + /// EAX[7:0] > 0. + /// + UINT32 OvfBuf : 1; + /// + /// [Bit 63] CondChgd: status bits of this register has changed. If + /// CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 CondChgd : 1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER; + +/** + Global Performance Counter Control (R/W) Counter increments while the result + of ANDing respective enable bit in this MSR with the corresponding OS or USR + bits in the general-purpose or fixed counter control MSR is true. If + CPUID.0AH: EAX[7:0] > 0. + + @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL); + AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n. + /// Enable bitmask. Only the first n-1 bits are valid. + /// Bits n..31 are reserved. + /// + UINT32 EN_PMCn : 32; + /// + /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n. + /// Enable bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 EN_FIXED_CTRn : 32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER; + +/** + Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] > + 0 && CPUID.0AH: EAX[7:0] <= 3. + + @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL); + AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. + /// Clear bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 Ovf_PMCn : 32; + /// + /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. + /// If CPUID.0AH: EDX[4:0] > n. + /// Clear bitmask. Only the first n-1 bits are valid. + /// Bits 22:n are reserved. + /// + UINT32 Ovf_FIXED_CTRn : 23; + /// + /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, + /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1. + /// + UINT32 Trace_ToPA_PMI : 1; + UINT32 Reserved2 : 5; + /// + /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / + /// Display Model 06_2EH. + /// + UINT32 Ovf_Uncore : 1; + /// + /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 OvfBuf : 1; + /// + /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 CondChgd : 1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER; + +/** + Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH: + EAX[7:0] > 3. + + @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET); + AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. + /// Clear bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 Ovf_PMCn : 32; + /// + /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. + /// If CPUID.0AH: EDX[4:0] > n. + /// Clear bitmask. Only the first n-1 bits are valid. + /// Bits 22:n are reserved. + /// + UINT32 Ovf_FIXED_CTRn : 23; + /// + /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, + /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1. + /// + UINT32 Trace_ToPA_PMI : 1; + UINT32 Reserved2 : 2; + /// + /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 LBR_Frz : 1; + /// + /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 CTR_Frz : 1; + /// + /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 ASCI : 1; + /// + /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / + /// Display Model 06_2EH. + /// + UINT32 Ovf_Uncore : 1; + /// + /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 OvfBuf : 1; + /// + /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 CondChgd : 1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER; + +/** + Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH: + EAX[7:0] > 3. + + @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET); + AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n. + /// Set bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 Ovf_PMCn : 32; + /// + /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1. + /// If CPUID.0AH: EAX[7:0] > n. + /// Set bitmask. Only the first n-1 bits are valid. + /// Bits 22:n are reserved. + /// + UINT32 Ovf_FIXED_CTRn : 23; + /// + /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 Trace_ToPA_PMI : 1; + UINT32 Reserved2 : 2; + /// + /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 LBR_Frz : 1; + /// + /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 CTR_Frz : 1; + /// + /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 ASCI : 1; + /// + /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 Ovf_Uncore : 1; + /// + /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 OvfBuf : 1; + UINT32 Reserved3 : 1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER; + +/** + Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] > + 3. + + @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE); + @endcode + @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n. + /// Status bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 IA32_PERFEVTSELn : 32; + /// + /// [Bits 62:32] IA32_FIXED_CTRn in use. + /// If CPUID.0AH: EAX[7:0] > n. + /// Status bitmask. Only the first n-1 bits are valid. + /// Bits 30:n are reserved. + /// + UINT32 IA32_FIXED_CTRn : 31; + /// + /// [Bit 63] PMI in use. + /// + UINT32 PMI : 1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER; + +/** + PEBS Control (R/W). + + @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PEBS_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PEBS_ENABLE_REGISTER. + + Example usage + @code + MSR_IA32_PEBS_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE); + AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64); + @endcode + @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM. +**/ +#define MSR_IA32_PEBS_ENABLE 0x000003F1 + +/** + MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family / + /// Display Model 06_0FH. + /// + UINT32 Enable : 1; + /// + /// [Bits 3:1] Reserved or Model specific. + /// + UINT32 Reserved1 : 3; + UINT32 Reserved2 : 28; + /// + /// [Bits 35:32] Reserved or Model specific. + /// + UINT32 Reserved3 : 4; + UINT32 Reserved4 : 28; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PEBS_ENABLE_REGISTER; + +/** + MCn_CTL. If IA32_MCG_CAP.CNT > n. + + @param ECX MSR_IA32_MCn_CTL + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL); + AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr); + @endcode + @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. + MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. + MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. + MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. + MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. + MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. + MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. + MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. + MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. + MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. + MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. + MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. + MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. + MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. + MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. + MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. + MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. + MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. + MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. + MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. + MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. + MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. + MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. + MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. + MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. + MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. + MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. + MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. + MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM. + @{ +**/ +#define MSR_IA32_MC0_CTL 0x00000400 +#define MSR_IA32_MC1_CTL 0x00000404 +#define MSR_IA32_MC2_CTL 0x00000408 +#define MSR_IA32_MC3_CTL 0x0000040C +#define MSR_IA32_MC4_CTL 0x00000410 +#define MSR_IA32_MC5_CTL 0x00000414 +#define MSR_IA32_MC6_CTL 0x00000418 +#define MSR_IA32_MC7_CTL 0x0000041C +#define MSR_IA32_MC8_CTL 0x00000420 +#define MSR_IA32_MC9_CTL 0x00000424 +#define MSR_IA32_MC10_CTL 0x00000428 +#define MSR_IA32_MC11_CTL 0x0000042C +#define MSR_IA32_MC12_CTL 0x00000430 +#define MSR_IA32_MC13_CTL 0x00000434 +#define MSR_IA32_MC14_CTL 0x00000438 +#define MSR_IA32_MC15_CTL 0x0000043C +#define MSR_IA32_MC16_CTL 0x00000440 +#define MSR_IA32_MC17_CTL 0x00000444 +#define MSR_IA32_MC18_CTL 0x00000448 +#define MSR_IA32_MC19_CTL 0x0000044C +#define MSR_IA32_MC20_CTL 0x00000450 +#define MSR_IA32_MC21_CTL 0x00000454 +#define MSR_IA32_MC22_CTL 0x00000458 +#define MSR_IA32_MC23_CTL 0x0000045C +#define MSR_IA32_MC24_CTL 0x00000460 +#define MSR_IA32_MC25_CTL 0x00000464 +#define MSR_IA32_MC26_CTL 0x00000468 +#define MSR_IA32_MC27_CTL 0x0000046C +#define MSR_IA32_MC28_CTL 0x00000470 +/// @} + +/** + MCn_STATUS. If IA32_MCG_CAP.CNT > n. + + @param ECX MSR_IA32_MCn_STATUS + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS); + AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr); + @endcode + @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. + MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. + MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. + MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. + MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. + MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. + MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. + MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. + MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. + MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. + MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. + MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. + MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. + MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. + MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. + MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. + MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. + MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. + MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. + MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. + MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. + MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. + MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. + MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. + MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. + MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. + MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. + MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. + MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM. + @{ +**/ +#define MSR_IA32_MC0_STATUS 0x00000401 +#define MSR_IA32_MC1_STATUS 0x00000405 +#define MSR_IA32_MC2_STATUS 0x00000409 +#define MSR_IA32_MC3_STATUS 0x0000040D +#define MSR_IA32_MC4_STATUS 0x00000411 +#define MSR_IA32_MC5_STATUS 0x00000415 +#define MSR_IA32_MC6_STATUS 0x00000419 +#define MSR_IA32_MC7_STATUS 0x0000041D +#define MSR_IA32_MC8_STATUS 0x00000421 +#define MSR_IA32_MC9_STATUS 0x00000425 +#define MSR_IA32_MC10_STATUS 0x00000429 +#define MSR_IA32_MC11_STATUS 0x0000042D +#define MSR_IA32_MC12_STATUS 0x00000431 +#define MSR_IA32_MC13_STATUS 0x00000435 +#define MSR_IA32_MC14_STATUS 0x00000439 +#define MSR_IA32_MC15_STATUS 0x0000043D +#define MSR_IA32_MC16_STATUS 0x00000441 +#define MSR_IA32_MC17_STATUS 0x00000445 +#define MSR_IA32_MC18_STATUS 0x00000449 +#define MSR_IA32_MC19_STATUS 0x0000044D +#define MSR_IA32_MC20_STATUS 0x00000451 +#define MSR_IA32_MC21_STATUS 0x00000455 +#define MSR_IA32_MC22_STATUS 0x00000459 +#define MSR_IA32_MC23_STATUS 0x0000045D +#define MSR_IA32_MC24_STATUS 0x00000461 +#define MSR_IA32_MC25_STATUS 0x00000465 +#define MSR_IA32_MC26_STATUS 0x00000469 +#define MSR_IA32_MC27_STATUS 0x0000046D +#define MSR_IA32_MC28_STATUS 0x00000471 +/// @} + +/** + MCn_ADDR. If IA32_MCG_CAP.CNT > n. + + @param ECX MSR_IA32_MCn_ADDR + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR); + AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr); + @endcode + @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. + MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. + MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. + MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. + MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. + MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. + MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. + MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. + MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. + MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. + MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. + MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. + MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. + MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. + MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. + MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. + MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. + MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. + MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. + MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. + MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. + MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. + MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. + MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. + MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. + MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. + MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. + MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. + MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM. + @{ +**/ +#define MSR_IA32_MC0_ADDR 0x00000402 +#define MSR_IA32_MC1_ADDR 0x00000406 +#define MSR_IA32_MC2_ADDR 0x0000040A +#define MSR_IA32_MC3_ADDR 0x0000040E +#define MSR_IA32_MC4_ADDR 0x00000412 +#define MSR_IA32_MC5_ADDR 0x00000416 +#define MSR_IA32_MC6_ADDR 0x0000041A +#define MSR_IA32_MC7_ADDR 0x0000041E +#define MSR_IA32_MC8_ADDR 0x00000422 +#define MSR_IA32_MC9_ADDR 0x00000426 +#define MSR_IA32_MC10_ADDR 0x0000042A +#define MSR_IA32_MC11_ADDR 0x0000042E +#define MSR_IA32_MC12_ADDR 0x00000432 +#define MSR_IA32_MC13_ADDR 0x00000436 +#define MSR_IA32_MC14_ADDR 0x0000043A +#define MSR_IA32_MC15_ADDR 0x0000043E +#define MSR_IA32_MC16_ADDR 0x00000442 +#define MSR_IA32_MC17_ADDR 0x00000446 +#define MSR_IA32_MC18_ADDR 0x0000044A +#define MSR_IA32_MC19_ADDR 0x0000044E +#define MSR_IA32_MC20_ADDR 0x00000452 +#define MSR_IA32_MC21_ADDR 0x00000456 +#define MSR_IA32_MC22_ADDR 0x0000045A +#define MSR_IA32_MC23_ADDR 0x0000045E +#define MSR_IA32_MC24_ADDR 0x00000462 +#define MSR_IA32_MC25_ADDR 0x00000466 +#define MSR_IA32_MC26_ADDR 0x0000046A +#define MSR_IA32_MC27_ADDR 0x0000046E +#define MSR_IA32_MC28_ADDR 0x00000472 +/// @} + +/** + MCn_MISC. If IA32_MCG_CAP.CNT > n. + + @param ECX MSR_IA32_MCn_MISC + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC); + AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr); + @endcode + @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. + MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. + MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. + MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. + MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. + MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. + MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. + MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. + MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. + MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. + MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. + MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. + MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. + MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. + MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. + MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. + MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. + MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. + MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. + MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. + MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. + MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. + MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. + MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. + MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. + MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. + MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. + MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. + MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM. + @{ +**/ +#define MSR_IA32_MC0_MISC 0x00000403 +#define MSR_IA32_MC1_MISC 0x00000407 +#define MSR_IA32_MC2_MISC 0x0000040B +#define MSR_IA32_MC3_MISC 0x0000040F +#define MSR_IA32_MC4_MISC 0x00000413 +#define MSR_IA32_MC5_MISC 0x00000417 +#define MSR_IA32_MC6_MISC 0x0000041B +#define MSR_IA32_MC7_MISC 0x0000041F +#define MSR_IA32_MC8_MISC 0x00000423 +#define MSR_IA32_MC9_MISC 0x00000427 +#define MSR_IA32_MC10_MISC 0x0000042B +#define MSR_IA32_MC11_MISC 0x0000042F +#define MSR_IA32_MC12_MISC 0x00000433 +#define MSR_IA32_MC13_MISC 0x00000437 +#define MSR_IA32_MC14_MISC 0x0000043B +#define MSR_IA32_MC15_MISC 0x0000043F +#define MSR_IA32_MC16_MISC 0x00000443 +#define MSR_IA32_MC17_MISC 0x00000447 +#define MSR_IA32_MC18_MISC 0x0000044B +#define MSR_IA32_MC19_MISC 0x0000044F +#define MSR_IA32_MC20_MISC 0x00000453 +#define MSR_IA32_MC21_MISC 0x00000457 +#define MSR_IA32_MC22_MISC 0x0000045B +#define MSR_IA32_MC23_MISC 0x0000045F +#define MSR_IA32_MC24_MISC 0x00000463 +#define MSR_IA32_MC25_MISC 0x00000467 +#define MSR_IA32_MC26_MISC 0x0000046B +#define MSR_IA32_MC27_MISC 0x0000046F +#define MSR_IA32_MC28_MISC 0x00000473 +/// @} + +/** + Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic + VMX Information.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_BASIC (0x00000480) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + MSR_IA32_VMX_BASIC_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC); + @endcode + @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM. +**/ +#define MSR_IA32_VMX_BASIC 0x00000480 + +/** + MSR information returned for MSR index #MSR_IA32_VMX_BASIC +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 30:0] VMCS revision identifier used by the processor. Processors + /// that use the same VMCS revision identifier use the same size for VMCS + /// regions (see subsequent item on bits 44:32). + /// + /// @note Earlier versions of this manual specified that the VMCS revision + /// identifier was a 32-bit field in bits 31:0 of this MSR. For all + /// processors produced prior to this change, bit 31 of this MSR was read + /// as 0. + /// + UINT32 VmcsRevisonId : 31; + UINT32 MustBeZero : 1; + /// + /// [Bit 44:32] Reports the number of bytes that software should allocate + /// for the VMXON region and any VMCS region. It is a value greater than + /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear). + /// + UINT32 VmcsSize : 13; + UINT32 Reserved1 : 3; + /// + /// [Bit 48] Indicates the width of the physical addresses that may be used + /// for the VMXON region, each VMCS, and data structures referenced by + /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX + /// transitions). If the bit is 0, these addresses are limited to the + /// processor's physical-address width. If the bit is 1, these addresses + /// are limited to 32 bits. This bit is always 0 for processors that + /// support Intel 64 architecture. + /// + /// @note On processors that support Intel 64 architecture, the pointer + /// must not set bits beyond the processor's physical address width. + /// + UINT32 VmcsAddressWidth : 1; + /// + /// [Bit 49] If bit 49 is read as 1, the logical processor supports the + /// dual-monitor treatment of system-management interrupts and + /// system-management mode. See Section 34.15 for details of this treatment. + /// + UINT32 DualMonitor : 1; + /// + /// [Bit 53:50] report the memory type that should be used for the VMCS, + /// for data structures referenced by pointers in the VMCS (I/O bitmaps, + /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG + /// header. If software needs to access these data structures (e.g., to + /// modify the contents of the MSR bitmaps), it can configure the paging + /// structures to map them into the linear-address space. If it does so, + /// it should establish mappings that use the memory type reported bits + /// 53:50 in this MSR. + /// + /// As of this writing, all processors that support VMX operation indicate + /// the write-back type. + /// + /// If software needs to access these data structures (e.g., to modify + /// the contents of the MSR bitmaps), it can configure the paging + /// structures to map them into the linear-address space. If it does so, + /// it should establish mappings that use the memory type reported in this + /// MSR. + /// + /// @note Alternatively, software may map any of these regions or + /// structures with the UC memory type. (This may be necessary for the MSEG + /// header.) Doing so is discouraged unless necessary as it will cause the + /// performance of software accesses to those structures to suffer. + /// + /// + UINT32 MemoryType : 4; + /// + /// [Bit 54] If bit 54 is read as 1, the processor reports information in + /// the VM-exit instruction-information field on VM exitsdue to execution + /// of the INS and OUTS instructions (see Section 27.2.4). This reporting + /// is done only if this bit is read as 1. + /// + UINT32 InsOutsReporting : 1; + /// + /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may + /// be cleared to 0. See Appendix A.2 for details. It also reports support + /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS, + /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and + /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2, + /// Appendix A.4, and Appendix A.5 for details. + /// + UINT32 VmxControls : 1; + UINT32 Reserved2 : 8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_VMX_BASIC_REGISTER; + +/// +/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType +/// +#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00 +#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06 +/// +/// @} +/// + +/** + Capability Reporting Register of Pinbased VM-execution Controls (R/O) See + Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS); + @endcode + @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM. +**/ +#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 + +/** + Capability Reporting Register of Primary Processor-based VM-execution + Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution + Controls.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS); + @endcode + @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM. +**/ +#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 + +/** + Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4, + "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS); + @endcode + @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM. +**/ +#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 + +/** + Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5, + "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS); + @endcode + @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM. +**/ +#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 + +/** + Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6, + "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_MISC (0x00000485) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + IA32_VMX_MISC_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC); + @endcode + @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM. +**/ +#define MSR_IA32_VMX_MISC 0x00000485 + +/** + MSR information returned for MSR index #IA32_VMX_MISC +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 4:0] Reports a value X that specifies the relationship between the + /// rate of the VMX-preemption timer and that of the timestamp counter (TSC). + /// Specifically, the VMX-preemption timer (if it is active) counts down by + /// 1 every time bit X in the TSC changes due to a TSC increment. + /// + UINT32 VmxTimerRatio : 5; + /// + /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA + /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more + /// details. This bit is read as 1 on any logical processor that supports + /// the 1-setting of the "unrestricted guest" VM-execution control. + /// + UINT32 VmExitEferLma : 1; + /// + /// [Bit 6] reports (if set) the support for activity state 1 (HLT). + /// + UINT32 HltActivityStateSupported : 1; + /// + /// [Bit 7] reports (if set) the support for activity state 2 (shutdown). + /// + UINT32 ShutdownActivityStateSupported : 1; + /// + /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI). + /// + UINT32 WaitForSipiActivityStateSupported : 1; + UINT32 Reserved1 : 5; + /// + /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used + /// in VMX operation. If the processor supports Intel PT but does not allow + /// it to be used in VMX operation, execution of VMXON clears + /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30); + /// any attempt to set that bit while in VMX operation (including VMX root + /// operation) using the WRMSR instruction causes a general-protection + /// exception. + /// + UINT32 ProcessorTraceSupported : 1; + /// + /// [Bit 15] If read as 1, the RDMSR instruction can be used in system- + /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH). + /// See Section 34.15.6.3. + /// + UINT32 SmBaseMsrSupported : 1; + /// + /// [Bits 24:16] Indicate the number of CR3-target values supported by the + /// processor. This number is a value between 0 and 256, inclusive (bit 24 + /// is set if and only if bits 23:16 are clear). + /// + UINT32 NumberOfCr3TargetValues : 9; + /// + /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum + /// number of MSRs that should appear in the VM-exit MSR-store list, the + /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if + /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the + /// recommended maximum number of MSRs to be included in each list. If the + /// limit is exceeded, undefined processor behavior may result (including a + /// machine check during the VMX transition). + /// + UINT32 MsrStoreListMaximum : 3; + /// + /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set + /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1 + /// (see Section 34.14.4). + /// + UINT32 BlockSmiSupported : 1; + /// + /// [Bit 29] read as 1, software can use VMWRITE to write to any supported + /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit + /// information fields. + /// + UINT32 VmWriteSupported : 1; + /// + /// [Bit 30] If read as 1, VM entry allows injection of a software + /// interrupt, software exception, or privileged software exception with an + /// instruction length of 0. + /// + UINT32 VmInjectSupported : 1; + UINT32 Reserved2 : 1; + /// + /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the + /// processor. + /// + UINT32 MsegRevisionIdentifier : 32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} IA32_VMX_MISC_REGISTER; + +/** + Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7, + "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0); + @endcode + @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM. +**/ +#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 + +/** + Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7, + "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1); + @endcode + @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM. +**/ +#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 + +/** + Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8, + "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488) ... 6692 lines suppressed ...

1 year, 3 months

[reactos] 03/06: [NTOS:KE/x64] Improve CPU feature detection

by Timo Kreuzer

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=70f6ed8ee35b638285f40… commit 70f6ed8ee35b638285f40ee8231c0dffa3052c0a Author: Timo Kreuzer <timo.kreuzer(a)reactos.org> AuthorDate: Sat Aug 26 16:15:38 2023 +0300 Commit: Timo Kreuzer <timo.kreuzer(a)reactos.org> CommitDate: Tue Oct 3 19:45:44 2023 +0300 [NTOS:KE/x64] Improve CPU feature detection - Use 64 bit feature flags (with a hack in the PRCB) - Improve setting up SharedUserData->ProcessorFeatures --- ntoskrnl/include/internal/amd64/ke.h | 2 +- ntoskrnl/ke/amd64/cpu.c | 4 +-- ntoskrnl/ke/amd64/kiinit.c | 59 +++++++++++++++++++++++++++--------- sdk/include/ndk/amd64/ketypes.h | 3 ++ 4 files changed, 50 insertions(+), 18 deletions(-) diff --git a/ntoskrnl/include/internal/amd64/ke.h b/ntoskrnl/include/internal/amd64/ke.h index 3287e7567c2..84246690638 100644 --- a/ntoskrnl/include/internal/amd64/ke.h +++ b/ntoskrnl/include/internal/amd64/ke.h @@ -418,7 +418,7 @@ VOID Ki386InitializeLdt(VOID); VOID Ki386SetProcessorFeatures(VOID); VOID KiGetCacheInformation(VOID); VOID KiSetProcessorType(VOID); -ULONG KiGetFeatureBits(VOID); +ULONG64 KiGetFeatureBits(VOID); VOID KiInitializeCpuFeatures(VOID); #if DBG VOID KiReportCpuFeatures(IN PKPRCB Prcb); diff --git a/ntoskrnl/ke/amd64/cpu.c b/ntoskrnl/ke/amd64/cpu.c index 075326d91ce..d5086b950d3 100644 --- a/ntoskrnl/ke/amd64/cpu.c +++ b/ntoskrnl/ke/amd64/cpu.c @@ -145,13 +145,13 @@ KiSetProcessorType(VOID) KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping; } -ULONG +ULONG64 NTAPI KiGetFeatureBits(VOID) { PKPRCB Prcb = KeGetCurrentPrcb(); ULONG Vendor; - ULONG FeatureBits = 0; + ULONG64 FeatureBits = 0; CPU_INFO CpuInfo; /* Get the Vendor ID */ diff --git a/ntoskrnl/ke/amd64/kiinit.c b/ntoskrnl/ke/amd64/kiinit.c index a0dc2c5c5b8..6d6ffbd3f2a 100644 --- a/ntoskrnl/ke/amd64/kiinit.c +++ b/ntoskrnl/ke/amd64/kiinit.c @@ -170,7 +170,7 @@ NTAPI KiInitializeCpu(PKIPCR Pcr) { ULONG64 Pat; - ULONG FeatureBits; + ULONG64 FeatureBits; /* Initialize gs */ KiInitializeSegments(); @@ -199,7 +199,8 @@ KiInitializeCpu(PKIPCR Pcr) FeatureBits |= KF_NX_ENABLED; /* Save feature bits */ - Pcr->Prcb.FeatureBits = FeatureBits; + Pcr->Prcb.FeatureBits = (ULONG)FeatureBits; + Pcr->Prcb.FeatureBitsHigh = FeatureBits >> 32; /* Enable fx save restore support */ __writecr4(__readcr4() | CR4_FXSR); @@ -283,6 +284,8 @@ KiInitializeKernelMachineDependent( IN PKPRCB Prcb, IN PLOADER_PARAMETER_BLOCK LoaderBlock) { + ULONG64 FeatureBits; + /* Set boot-level flags */ KeI386CpuType = Prcb->CpuType; KeI386CpuStep = Prcb->CpuStep; @@ -291,26 +294,52 @@ KiInitializeKernelMachineDependent( if (Prcb->CpuID) KeProcessorRevision = Prcb->CpuStep; + FeatureBits = Prcb->FeatureBits | (ULONG64)Prcb->FeatureBitsHigh << 32; + /* Set basic CPU Features that user mode can read */ + SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_PRECISION_ERRATA] = FALSE; + SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_EMULATED] = FALSE; SharedUserData->ProcessorFeatures[PF_COMPARE_EXCHANGE_DOUBLE] = TRUE; - SharedUserData->ProcessorFeatures[PF_RDTSC_INSTRUCTION_AVAILABLE] = TRUE; - SharedUserData->ProcessorFeatures[PF_PPC_MOVEMEM_64BIT_OK] = TRUE; - SharedUserData->ProcessorFeatures[PF_PAE_ENABLED] = TRUE; // ??? - SharedUserData->ProcessorFeatures[PF_NX_ENABLED] = TRUE; - SharedUserData->ProcessorFeatures[PF_FASTFAIL_AVAILABLE] = TRUE; - SharedUserData->ProcessorFeatures[PF_XSAVE_ENABLED] = TRUE; SharedUserData->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] = - (Prcb->FeatureBits & KF_MMX) ? TRUE: FALSE; + (FeatureBits & KF_MMX) ? TRUE : FALSE; SharedUserData->ProcessorFeatures[PF_XMMI_INSTRUCTIONS_AVAILABLE] = - ((Prcb->FeatureBits & KF_FXSR) && (Prcb->FeatureBits & KF_XMMI)) ? TRUE: FALSE; - SharedUserData->ProcessorFeatures[PF_XMMI64_INSTRUCTIONS_AVAILABLE] = - ((Prcb->FeatureBits & KF_FXSR) && (Prcb->FeatureBits & KF_XMMI64)) ? TRUE: FALSE; + ((FeatureBits & KF_FXSR) && (FeatureBits & KF_XMMI)) ? TRUE : FALSE; SharedUserData->ProcessorFeatures[PF_3DNOW_INSTRUCTIONS_AVAILABLE] = - (Prcb->FeatureBits & KF_3DNOW) ? TRUE: FALSE; + (FeatureBits & KF_3DNOW) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_RDTSC_INSTRUCTION_AVAILABLE] = TRUE; + SharedUserData->ProcessorFeatures[PF_PAE_ENABLED] = TRUE; // ??? + SharedUserData->ProcessorFeatures[PF_XMMI64_INSTRUCTIONS_AVAILABLE] = + ((FeatureBits & KF_FXSR) && (FeatureBits & KF_XMMI64)) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_SSE_DAZ_MODE_AVAILABLE] = FALSE; // ??? + SharedUserData->ProcessorFeatures[PF_NX_ENABLED] = TRUE; SharedUserData->ProcessorFeatures[PF_SSE3_INSTRUCTIONS_AVAILABLE] = - (Prcb->FeatureBits & KF_SSE3) ? TRUE: FALSE; + (FeatureBits & KF_SSE3) ? TRUE : FALSE; SharedUserData->ProcessorFeatures[PF_COMPARE_EXCHANGE128] = - (Prcb->FeatureBits & KF_CMPXCHG16B) ? TRUE: FALSE; + (FeatureBits & KF_CMPXCHG16B) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_COMPARE64_EXCHANGE128] = FALSE; // ??? + SharedUserData->ProcessorFeatures[PF_CHANNELS_ENABLED] = FALSE; // ??? + SharedUserData->ProcessorFeatures[PF_XSAVE_ENABLED] = FALSE; // FIXME + SharedUserData->ProcessorFeatures[PF_SECOND_LEVEL_ADDRESS_TRANSLATION] = + (FeatureBits & KF_SLAT) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_VIRT_FIRMWARE_ENABLED] = + (FeatureBits & KF_VIRT_FIRMWARE_ENABLED) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_RDWRFSGSBASE_AVAILABLE] = + (FeatureBits & KF_RDWRFSGSBASE) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_FASTFAIL_AVAILABLE] = TRUE; + SharedUserData->ProcessorFeatures[PF_RDRAND_INSTRUCTION_AVAILABLE] = + (FeatureBits & KF_RDRAND) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_RDTSCP_INSTRUCTION_AVAILABLE] = + (FeatureBits & KF_RDTSCP) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_RDPID_INSTRUCTION_AVAILABLE] = FALSE; // ??? + SharedUserData->ProcessorFeatures[PF_SSSE3_INSTRUCTIONS_AVAILABLE] = + (FeatureBits & KF_SSSE3) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_SSE4_1_INSTRUCTIONS_AVAILABLE] = + (FeatureBits & KF_SSE4_1) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_SSE4_2_INSTRUCTIONS_AVAILABLE] = + (FeatureBits & KF_SSE4_2) ? TRUE : FALSE; + SharedUserData->ProcessorFeatures[PF_AVX_INSTRUCTIONS_AVAILABLE] = FALSE; // FIXME + SharedUserData->ProcessorFeatures[PF_AVX2_INSTRUCTIONS_AVAILABLE] = FALSE; // FIXME + SharedUserData->ProcessorFeatures[PF_AVX512F_INSTRUCTIONS_AVAILABLE] = FALSE; // FIXME /* Set the default NX policy (opt-in) */ SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_OPTIN; diff --git a/sdk/include/ndk/amd64/ketypes.h b/sdk/include/ndk/amd64/ketypes.h index 553c3bdb956..1f306de1d2c 100644 --- a/sdk/include/ndk/amd64/ketypes.h +++ b/sdk/include/ndk/amd64/ketypes.h @@ -910,6 +910,9 @@ typedef struct _KPRCB CACHE_DESCRIPTOR Cache[5]; ULONG CacheCount; #endif +#ifdef __REACTOS__ + ULONG FeatureBitsHigh; +#endif } KPRCB, *PKPRCB; //

1 year, 3 months

[reactos] 02/06: [NDK] Update kernel feature bits constants

by Timo Kreuzer

https://git.reactos.org/?p=reactos.git;a=commitdiff;h=47c1dcd023b7f31c8b901… commit 47c1dcd023b7f31c8b9016477c2652e6ffbb8ac8 Author: Timo Kreuzer <timo.kreuzer(a)reactos.org> AuthorDate: Sat Aug 26 12:10:04 2023 +0300 Commit: Timo Kreuzer <timo.kreuzer(a)reactos.org> CommitDate: Tue Oct 3 19:45:44 2023 +0300 [NDK] Update kernel feature bits constants - Move them into architecture specific headers. - Add missing constants based on https://www.geoffchappell.com/studies/windows/km/ntoskrnl/structs/kprcb/fea… - Yes, they are 64 bits --- ntoskrnl/ke/amd64/cpu.c | 19 ++++++-------- sdk/include/ndk/amd64/ketypes.h | 56 +++++++++++++++++++++++++++++++++++++++++ sdk/include/ndk/i386/ketypes.h | 46 +++++++++++++++++++++++++++++++++ sdk/include/ndk/ketypes.h | 33 ------------------------ 4 files changed, 109 insertions(+), 45 deletions(-) diff --git a/ntoskrnl/ke/amd64/cpu.c b/ntoskrnl/ke/amd64/cpu.c index 274320c1b12..075326d91ce 100644 --- a/ntoskrnl/ke/amd64/cpu.c +++ b/ntoskrnl/ke/amd64/cpu.c @@ -151,7 +151,7 @@ KiGetFeatureBits(VOID) { PKPRCB Prcb = KeGetCurrentPrcb(); ULONG Vendor; - ULONG FeatureBits = KF_WORKING_PTE; + ULONG FeatureBits = 0; CPU_INFO CpuInfo; /* Get the Vendor ID */ @@ -167,7 +167,7 @@ KiGetFeatureBits(VOID) Prcb->InitialApicId = (UCHAR)(CpuInfo.Ebx >> 24); /* Convert all CPUID Feature bits into our format */ - if (CpuInfo.Edx & X86_FEATURE_VME) FeatureBits |= KF_V86_VIS | KF_CR4; + if (CpuInfo.Edx & X86_FEATURE_VME) FeatureBits |= KF_CR4; if (CpuInfo.Edx & X86_FEATURE_PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4; if (CpuInfo.Edx & X86_FEATURE_TSC) FeatureBits |= KF_RDTSC; if (CpuInfo.Edx & X86_FEATURE_CX8) FeatureBits |= KF_CMPXCHG8B; @@ -183,11 +183,9 @@ KiGetFeatureBits(VOID) if (CpuInfo.Edx & X86_FEATURE_SSE2) FeatureBits |= KF_XMMI64; if (CpuInfo.Ecx & X86_FEATURE_SSE3) FeatureBits |= KF_SSE3; - //if (CpuInfo.Ecx & X86_FEATURE_MONITOR) FeatureBits |= KF_MONITOR; - //if (CpuInfo.Ecx & X86_FEATURE_SSSE3) FeatureBits |= KF_SSE3SUP; + //if (CpuInfo.Ecx & X86_FEATURE_SSSE3) FeatureBits |= KF_SSSE3; if (CpuInfo.Ecx & X86_FEATURE_CX16) FeatureBits |= KF_CMPXCHG16B; - //if (CpuInfo.Ecx & X86_FEATURE_SSE41) FeatureBits |= KF_SSE41; - //if (CpuInfo.Ecx & X86_FEATURE_POPCNT) FeatureBits |= KF_POPCNT; + //if (CpuInfo.Ecx & X86_FEATURE_SSE41) FeatureBits |= KF_SSE4_1; if (CpuInfo.Ecx & X86_FEATURE_XSAVE) FeatureBits |= KF_XSTATE; /* Check if the CPU has hyper-threading */ @@ -250,7 +248,7 @@ KiReportCpuFeatures(IN PKPRCB Prcb) DPRINT1("Supported CPU features: "); #define print_kf_bit(kf_value) if (Prcb->FeatureBits & kf_value) DbgPrint(#kf_value " ") - print_kf_bit(KF_V86_VIS); + print_kf_bit(KF_SMEP); print_kf_bit(KF_RDTSC); print_kf_bit(KF_CR4); print_kf_bit(KF_CMOV); @@ -260,7 +258,6 @@ KiReportCpuFeatures(IN PKPRCB Prcb) print_kf_bit(KF_CMPXCHG8B); print_kf_bit(KF_CMPXCHG16B); print_kf_bit(KF_MMX); - print_kf_bit(KF_WORKING_PTE); print_kf_bit(KF_PAT); print_kf_bit(KF_FXSR); print_kf_bit(KF_FAST_SYSCALL); @@ -272,10 +269,8 @@ KiReportCpuFeatures(IN PKPRCB Prcb) print_kf_bit(KF_NX_DISABLED); print_kf_bit(KF_NX_ENABLED); print_kf_bit(KF_SSE3); - //print_kf_bit(KF_SSE3SUP); - //print_kf_bit(KF_SSE41); - //print_kf_bit(KF_MONITOR); - //print_kf_bit(KF_POPCNT); + print_kf_bit(KF_SSSE3); + print_kf_bit(KF_SSE4_1); print_kf_bit(KF_XSTATE); #undef print_kf_bit diff --git a/sdk/include/ndk/amd64/ketypes.h b/sdk/include/ndk/amd64/ketypes.h index e09c0a884ce..553c3bdb956 100644 --- a/sdk/include/ndk/amd64/ketypes.h +++ b/sdk/include/ndk/amd64/ketypes.h @@ -24,6 +24,62 @@ Author: // Dependencies // +// +// Kernel Feature Bits +// See https://www.geoffchappell.com/studies/windows/km/ntoskrnl/structs/kprcb/fea… +// +#define KF_SMEP 0x00000001 // Win 6.2 +#define KF_RDTSC 0x00000002 // From ks386.inc, ksamd64.inc +#define KF_CR4 0x00000004 // From ks386.inc, ksamd64.inc +#define KF_CMOV 0x00000008 +#define KF_GLOBAL_PAGE 0x00000010 // From ks386.inc, ksamd64.inc +#define KF_LARGE_PAGE 0x00000020 // From ks386.inc, ksamd64.inc +#define KF_MTRR 0x00000040 +#define KF_CMPXCHG8B 0x00000080 // From ks386.inc, ksamd64.inc +#define KF_MMX 0x00000100 +#define KF_DTS 0x00000200 // Win 5.2-6.2 +#define KF_PAT 0x00000400 +#define KF_FXSR 0x00000800 +#define KF_FAST_SYSCALL 0x00001000 // From ks386.inc, ksamd64.inc +#define KF_XMMI 0x00002000 // SSE +#define KF_3DNOW 0x00004000 +#define KF_AMDK6MTRR 0x00008000 // Win 5.0-6.1 +#define KF_XSAVEOPT 0x00008000 // From KF_XSAVEOPT_BIT +#define KF_XMMI64 0x00010000 // SSE2 +#define KF_BRANCH 0x00020000 // From ksamd64.inc, Win 6.1-6.2 +#define KF_00040000 0x00040000 // Unclear +#define KF_SSE3 0x00080000 // Win 6.0+ +#define KF_CMPXCHG16B 0x00100000 // Win 6.0-6.2 +#define KF_AUTHENTICAMD 0x00200000 // Win 6.1+ +#define KF_ACNT2 0x00400000 // Win 6.1+ +#define KF_XSTATE 0x00800000 // From ksamd64.inc, Win 6.1+ +#define KF_GENUINE_INTEL 0x01000000 // Win 6.1+ +#define KF_02000000 0x02000000 // Unclear +#define KF_SLAT 0x04000000 // Win 6.2+, Intel: EPT supported +#define KF_VIRT_FIRMWARE_ENABLED 0x08000000 // Win 6.2+ +#define KF_RDWRFSGSBASE 0x10000000 // From ksamd64.inc KF_RDWRFSGSBASE_BIT (0x1C) +#define KF_NX_BIT 0x20000000 +#define KF_NX_DISABLED 0x40000000 +#define KF_NX_ENABLED 0x80000000 +#define KF_RDRAND 0x0000000100000000ULL // Win 10.0+ +#define KF_SMAP 0x0000000200000000ULL // From ksamd64.inc +#define KF_RDTSCP 0x0000000400000000ULL // Win 10.0+ +#define KF_HUGEPAGE 0x0000002000000000ULL // Win 10.0 1607+ +#define KF_XSAVES 0x0000004000000000ULL // From ksamd64.inc KF_XSAVES_BIT (0x26) +#define KF_FPU_LEAKAGE 0x0000020000000000ULL // From ksamd64.inc KF_FPU_LEAKAGE_BIT (0x29) +#define KF_CAT 0x0000100000000000ULL // From ksamd64.inc KF_CAT_BIT (0x02C) +#define KF_CET_SS 0x0000400000000000ULL // From ksamd64.inc +#define KF_SSSE3 0x0000800000000000ULL +#define KF_SSE4_1 0x0001000000000000ULL +#define KF_SSE4_2 0x0002000000000000ULL + +#define KF_XSAVEOPT_BIT 15 // From ksamd64.inc (0x0F -> 0x8000) +#define KF_XSTATE_BIT 23 // From ksamd64.inc (0x17 -> 0x800000) +#define KF_RDWRFSGSBASE_BIT 28 // From ksamd64.inc (0x1C -> 0x10000000) +#define KF_XSAVES_BIT 38 // From ksamd64.inc (0x26 -> 0x4000000000) +#define KF_FPU_LEAKAGE_BIT 41 // From ksamd64.inc (0x29 -> 0x20000000000) +#define KF_CAT_BIT 44 // From ksamd64.inc (0x2C -> 0x100000000000) + // // KPCR Access for non-IA64 builds // diff --git a/sdk/include/ndk/i386/ketypes.h b/sdk/include/ndk/i386/ketypes.h index 8a9ea4c2ad5..6eb97d81ba0 100644 --- a/sdk/include/ndk/i386/ketypes.h +++ b/sdk/include/ndk/i386/ketypes.h @@ -23,6 +23,52 @@ Author: // Dependencies // +// +// Kernel Feature Bits +// See https://www.geoffchappell.com/studies/windows/km/ntoskrnl/structs/kprcb/fea… +// +#define KF_V86_VIS 0x00000001 // From ks386.inc +#define KF_RDTSC 0x00000002 // From ks386.inc, ksamd64.inc +#define KF_CR4 0x00000004 // From ks386.inc, ksamd64.inc +#define KF_CMOV 0x00000008 +#define KF_GLOBAL_PAGE 0x00000010 // From ks386.inc, ksamd64.inc +#define KF_LARGE_PAGE 0x00000020 // From ks386.inc, ksamd64.inc +#define KF_MTRR 0x00000040 +#define KF_CMPXCHG8B 0x00000080 // From ks386.inc, ksamd64.inc +#define KF_MMX 0x00000100 +#define KF_WORKING_PTE 0x00000200 +#define KF_PAT 0x00000400 +#define KF_FXSR 0x00000800 +#define KF_FAST_SYSCALL 0x00001000 // From ks386.inc, ksamd64.inc +#define KF_XMMI 0x00002000 // SSE +#define KF_3DNOW 0x00004000 +#define KF_AMDK6MTRR 0x00008000 // Win 5.0-6.1 +#define KF_XSAVEOPT 0x00008000 // From KF_XSAVEOPT_BIT +#define KF_XMMI64 0x00010000 // SSE2 +#define KF_DTS 0x00020000 +#define KF_CLFLUSH 0x00040000 // Win 6.0+ +#define KF_SSE3 0x00080000 // Win 6.0+ +#define KF_AUTHENTICAMD 0x00100000 // Win 6.1+ (family 5+) +#define KF_ACNT2 0x00200000 // Win 6.1+ +#define KF_XSTATE 0x00400000 // From ks386.inc, Win 6.1+ +#define KF_GENUINE_INTEL 0x00800000 // Win 6.1+ +#define KF_SMEP 0x01000000 // Win 6.2+ +#define KF_RDRAND 0x02000000 // Win 6.3+ +#define KF_SLAT 0x04000000 // Win 6.2+, Intel: EPT supported +#define KF_08000000 0x08000000 // Win 6.2+ +#define KF_NX_BIT 0x20000000 +#define KF_NX_DISABLED 0x40000000 +#define KF_NX_ENABLED 0x80000000 +#define KF_RDTSCP 0x0000000100000000ULL // Win 10.0+ +#define KF_CLFLUSHOPT 0x0000000200000000ULL // Win 10.0+ +#define KF_HDC 0x0000000400000000ULL // Win 10.0+ +#define KF_FPU_LEAKAGE 0x0000001000000000ULL // From ks386.inc KF_FPU_LEAKAGE_BIT +#define KF_SSSE3 0x0000004000000000ULL +#define KF_SSE4_1 0x0000008000000000ULL +#define KF_SSE4_2 0x0000010000000000ULL + +#define KF_FPU_LEAKAGE_BIT 36 // From ks386.inc (0x24 -> 0x1000000000) + // // KPCR Access for non-IA64 builds // diff --git a/sdk/include/ndk/ketypes.h b/sdk/include/ndk/ketypes.h index d54b9ffa131..37627fc39a4 100644 --- a/sdk/include/ndk/ketypes.h +++ b/sdk/include/ndk/ketypes.h @@ -137,39 +137,6 @@ Author: #define WAIT_QUANTUM_DECREMENT 1 #define CLOCK_QUANTUM_DECREMENT 3 -// -// Kernel Feature Bits -// -#define KF_V86_VIS 0x00000001 -#define KF_RDTSC 0x00000002 -#define KF_CR4 0x00000004 -#define KF_CMOV 0x00000008 -#define KF_GLOBAL_PAGE 0x00000010 -#define KF_LARGE_PAGE 0x00000020 -#define KF_MTRR 0x00000040 -#define KF_CMPXCHG8B 0x00000080 -#define KF_MMX 0x00000100 -#define KF_WORKING_PTE 0x00000200 -#define KF_PAT 0x00000400 -#define KF_FXSR 0x00000800 -#define KF_FAST_SYSCALL 0x00001000 -#define KF_XMMI 0x00002000 -#define KF_3DNOW 0x00004000 -#define KF_AMDK6MTRR 0x00008000 -#define KF_XMMI64 0x00010000 -#define KF_DTS 0x00020000 -#define KF_BRANCH 0x00020000 // from ksamd64.inc -#define KF_SSE3 0x00080000 -#define KF_CMPXCHG16B 0x00100000 -#define KF_XSTATE 0x00800000 // from ks386.inc, ksamd64.inc -#define KF_NX_BIT 0x20000000 -#define KF_NX_DISABLED 0x40000000 -#define KF_NX_ENABLED 0x80000000 - -#define KF_XSAVEOPT_BIT 15 -#define KF_XSTATE_BIT 23 -#define KF_RDWRFSGSBASE_BIT 28 - // // Internal Exception Codes //

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